CN116107943A

CN116107943A - Signal transmission circuit and computing equipment

Info

Publication number: CN116107943A
Application number: CN202310088660.9A
Authority: CN
Inventors: 徐肖
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-01-19
Filing date: 2023-01-19
Publication date: 2023-05-12

Abstract

The embodiment of the application discloses a signal transmission circuit and a computing device, which are characterized in that the signal transmission circuit comprises a first circuit board, a joint bus UBC connector and a power connector; a power interface of the first circuit board is connected with the first end of the power connector, and a peripheral component interconnect express (PCIe) interface of the first circuit board is connected with the first end of the UBC connector; the second end of the power connector is used for being connected with the first PCIe device through the peripheral component interconnect express (PCI express) connector to supply power for the first PCIe device; the second end of the UBC connector is configured to connect with the first PCIe device through the PCIe connector to transmit PCIe signals to the first PCIe device. According to the embodiment of the application, the UBC connector and the power connector are adopted, so that the wiring difficulty of the main board can be reduced, and hardware resources are saved.

Description

Signal transmission circuit and computing equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a signal transmission circuit and a computing device.

Background

With the progress of computer technology, the functions and performances of the server are continuously improved and perfected, and the server plays an increasingly important role in the fields of cloud computing, data centers, big data and the like. In order to meet the increasing data processing demands, the computing performance of processing chips such as a central processing unit (central processing unit, CPU) in a server is also increasing, and in order to fully develop the computing power of the processing chips such as the CPU, the bandwidth requirements for data transmission are also increasing. Accordingly, data transfer protocols (standards) have also evolved, and peripheral component interconnect express (peripheral component interconnect express, PCIe) technology has evolved from PCIe version 1.0 to PCIe version 5.0 (generation 5 PCIe technology).

For transmission of PCIe high speed signals, dual density unified bus (union bus connector double density, UBCDD) connectors may be implemented by way of printed circuit board (print circuit board, PCB) routing to PCIe connectors. In this way, a plurality of UBCDD connectors are usually required to be disposed on the motherboard of the server, and the UBCDD connectors occupy a larger area of the motherboard of the server, which has a larger influence on wiring, resulting in difficulty in wiring.

Disclosure of Invention

The embodiment of the application discloses a signal transmission circuit and a computing device, which can reduce the wiring difficulty of a main board, save hardware resources and expand application scenes.

The first aspect discloses a signal transmission circuit, the signal transmission circuit includes a first circuit board, a joint bus UBC connector and a power connector, a power interface of the first circuit board is connected with a first end of the power connector, and a peripheral component interconnect express (PCIe) interface of the first circuit board is connected with the first end of the UBC connector; the second end of the power connector is used for being connected with the first PCIe device through the peripheral component interconnect express (PCI express) connector to supply power for the first PCIe device; the second end of the UBC connector is configured to connect with the first PCIe device through the PCIe connector to transmit PCIe signals to the first PCIe device.

In this embodiment of the present application, the first PCIe device may be connected by converting the UBC connector and the power connector to PCIe connectors. Compared with the UBCD connector, the UBC connector and the power connector occupy smaller area of the main board of the computing device, so that the wiring difficulty of the main board can be reduced. Meanwhile, the UBC connector can support X8 transmission at maximum, so that hardware resources can be saved by changing the UBCDD connector into a UBC high-speed connector and a power connector under the condition that X16 transmission is not needed (such as the condition that a PCIe connector is connected with an X8 network card). And compared with UBCD connectors, UBC connectors have more application scenes and higher flexibility.

As a possible implementation manner, the second end of the UBC connector is further used to connect to the second PCIe device.

In this embodiment of the present application, the second end of the UBC connector may also be connected to a second PCIe device or the like, and may not be connected to the first PCIe device through the PCIe connector, so that flexibility of application may be improved.

As a possible implementation manner, the first circuit board further comprises a power module and a controller, wherein the power module is used for transmitting a first power supply to the power connector, and the controller is used for transmitting a PCIe signal to the UBC connector; the power connector is used for outputting the first power supply to the PCIe connector, and the UBC connector is used for outputting the PCIe signal to the PCIe connector; the PCIe connector is to output the first power supply and the PCIe signal to the first PCIe device.

In the embodiment of the application, the power supply signal can be transmitted through the power supply connector, the PCIe signal can be transmitted through the UBC connector, and the power supply connector and the UBC connector can be flexibly arranged on different boards of the computing device.

As a possible embodiment, the UBC connector and the power connector are provided on the first circuit board, and/or on the second circuit board; when the UBC connector and the power connector are arranged on the first circuit board, the power interface of the first circuit board is connected with the first end of the power connector through a cable or a Printed Circuit Board (PCB) wiring, and the PCIe interface of the first circuit board is connected with the first end of the UBC connector through the cable or the Printed Circuit Board (PCB) wiring; when the UBC connector and the power connector are arranged on the second circuit board, the power interface of the first circuit board is connected with the first end of the power connector through a cable, and the PCIe interface of the first circuit board is connected with the first end of the UBC connector through a cable.

In this embodiment of the present application, the PCIe interface of the first circuit board may be connected to the first end of the UBC connector by a cable, and the UBC connector may be connected to the PCIe connector by a cable, so that transmission loss of PCIe signals may be reduced.

As a possible implementation manner, the PCIe interface of the first circuit board is connected to the first end of the UBC connector through a first cable, and/or the second end of the UBC connector is connected to the first end of the PCIe connector through a second cable.

As a possible implementation, when the UBC connector is disposed on the first circuit board, the PCIe interface of the first circuit board is connected to the first end of the UBC connector through internal traces on the first circuit board.

As a possible implementation manner, the second end of the power connector is connected with the first end of the PCIe connector through a third cable.

As one possible implementation, the first end of the PCIe connector includes at least one first pin and at least one second pin, the at least one first pin is soldered to one end of the second cable, the other end of the second cable forms a first plug, and the first plug is configured to plug into the second end of the UBC connector; the at least one second pin is welded with one end of the third cable, and the other end of the third cable forms a second plug which is used for being spliced with the second end of the power connector.

In this embodiment of the application, the pin that PCIe connector is used for transmitting PCIe signal can be welded with the one end of second cable, and the other end of second cable can form first plug, and the pin that PCIe connector is used for transmitting power supply number can be welded with the one end of third cable, and the other end of third cable can form the second plug, so when needs insert computing device with first PCIe equipment, can insert first plug and second plug respectively to UBC connector's second end and power supply connector's second end in a flexible way to insert first PCIe equipment in PCIe connector's slot.

As one possible implementation, the first end of the UBC connector and the first end of the power connector are soldered to the first circuit board.

As a possible implementation manner, the PCIe connector is fixedly disposed on the first circuit board or the second circuit board.

As a possible implementation manner, the first PCIe device is a network card, a redundant array of independent disks card, or a display card.

As one possible implementation, the second PCIe device is an open computing item card or a hard disk adapter board.

A second aspect discloses a computing device comprising a first circuit board having a power module, a controller, a power connector, and a joint bus UBC connector disposed thereon, and a second circuit board having a peripheral component interconnect express (PCIe) connector and PCIe device disposed thereon; the power module is connected with the first end of the power connector through a cable or a Printed Circuit Board (PCB) wiring, the controller is connected with the first end of the UBC connector through a cable or a PCB wiring, the second end of the UBC connector is connected with the first end of the PCIe connector through a second cable, the second end of the power connector is connected with the first end of the PCIe connector through a third cable, and the second end of the PCIe connector is connected with the PCIe device.

A third aspect discloses a computing device that may comprise the signal transmission circuit provided in the first aspect and any one of the possible implementations of the first aspect.

It should be appreciated that the implementation and benefits of the various aspects or any of the possible embodiments described above may be referenced with respect to each other.

Drawings

The drawings in the following description will be presented to more clearly illustrate the embodiments of the present application and to provide a brief description of the drawings, it being apparent that the drawings in the following description are only some of the embodiments of the present application and that other drawings may be obtained from these drawings by those skilled in the art without inventive faculty.

FIG. 1 is a schematic diagram of a computing device disclosed in an embodiment of the present application;

FIG. 2 is a schematic dimensional view of a UBCD connector according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another computing device disclosed in an embodiment of the present application;

FIG. 4 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the present application;

FIG. 5A is a schematic diagram of a 2Pin power connector according to an embodiment of the present disclosure;

FIG. 5B is a schematic diagram of a 4Pin power connector according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the present application;

FIG. 7 is a schematic diagram illustrating connection between a Controller (CPU) and a PCIe switch chip according to an embodiment of the present disclosure;

FIG. 8 is a schematic dimensional view of a UBC connector in accordance with an embodiment of the present disclosure;

fig. 9 is a schematic dimensional view of a 2pin power connector disclosed in an embodiment of the present application;

FIG. 10 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the present application;

FIG. 11 is a schematic diagram of a cable connection to a PCIe connector according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a configuration of yet another computing device disclosed in an embodiment of the present application;

Fig. 13 is a schematic structural diagram of yet another computing device disclosed in an embodiment of the present application.

Detailed Description

The embodiment of the application discloses a signal transmission circuit and a computing device, which can reduce the wiring difficulty of a main board, save hardware resources and expand application scenes. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

For a better understanding of the embodiments of the present application, the related art of the embodiments of the present application will be described first.

With the progress of computer technology, the functions and performances of the server are continuously improved and perfected, and the server plays an increasingly important role in the fields of cloud computing, data centers, big data and the like. In order to meet the increasing data processing demands, the computing performance of processing chips such as a central processing unit (central processing unit, CPU) in a server is also increasing, and in order to fully develop the computing power of the processing chips such as the CPU, the bandwidth requirements for data transmission are also increasing. Accordingly, data transfer protocols (standards) have also evolved, and peripheral component interconnect express (peripheral component interconnect express, PCIe) technology has evolved from PCIe version 1.0 to PCIe version 5.0 (generation 5 PCIe technology). Currently, the data link speed of PCIe 5.0 can reach 32 gigabit transmission/second (giga transmission per second, GT/s), twice that of PCIe 4.0, and has downward compatibility.

PCIe is a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and connected devices allocate exclusive channel bandwidths and do not share bus bandwidths. To meet the transmission requirements of different devices (including low-speed devices and high-speed devices), PCIe data transmissions include different specifications of X1, X4, X8, X16, and the like. X1 represents 1 Lane, which can transmit 1 pair of differential signals. Similarly, X2 represents 2 Lane, may transmit 2 pairs of differential signals, X8 represents 8 Lane, may transmit 8 pairs of differential signals, X16 represents 16 Lane, may transmit 16 pairs of differential signals. Wherein, the more Lane number, the faster the data transmission rate. For example, X1 under the PCIe 5.0 standard may reach 4 gigabytes per second (GB/s), X4 may reach 16GB/s, X8 may reach 32GB/s, and X16 may reach 64GB/s, with the actual data transfer rate also being dependent on the encoding scheme employed.

Currently, for transmitting PCIe 5.0 signals, a dual-density unified bus (union bus connector double density, UBCDD) connector (high-speed connector) is implemented by a cable-to-PCIe connector, in this manner, a plurality of UBCDD connectors are usually required to be disposed on a motherboard of a server, so that enough connectors can be extended later, and PCIe devices such as a network card, a graphics card, a redundant array of independent disks (redundant array of independent disks, RAID) card, a graphics processor (graphics processing unit, GPU) card and the like are connected.

In particular, referring to fig. 1, fig. 1 is a schematic structural diagram of a computing device according to an embodiment of the present application. As shown in fig. 1, computing device 100 may include a circuit board 101, UBCDD connector 102, PCIe connector 103, PCIe device 104, controller 105. The controller 105 on the circuit board 101 and the UBCDD connector 102 may be wired through a printed circuit board (print circuit board, PCB), and the UBCDD connector 102 and the PCIe connector 103 may be wired through a cable. The PCIe connector 103 may include a slot, and the PCIe device 104 may be inserted in the slot of the PCIe connector 103. The circuit board 101 may be a motherboard and the controller 105 may be a CPU.

The circuit board 101 may further include a power module thereon, where the power module and the controller 105 may transmit power and high speed signals (PCIe signals) to the UBCDD connector 102 via PCB traces, respectively, the UBCDD connector 102 may transmit power and high speed signals to the PCIe connector 103 via cables, and the PCIe connector 103 may transmit power and high speed signals to the PCIe device 104. In this way, power (e.g., 12V power) may be provided to the PCIe device 104 as needed so that the PCIe device 104 may function properly. And, high speed signals may also be transmitted through UBCDD connector 102, PCIe connector 103, and PCB trace. However, because PCIe 5.0 transmission rate is relatively high, transmission through PCB traces is also more lossy. PCIe device 104 may be a network card, GPU card, or the like.

In addition, UBCDD connectors are bulky and occupy a large area of the server motherboard, so that the area available for wiring is relatively small, which can have a large impact on wiring, resulting in wiring difficulties. For example, referring to fig. 2, fig. 2 is a schematic dimensional diagram of a UBCDD connector according to an embodiment of the present application. As shown in fig. 2, the UBCDD connector has a length and width of 36 millimeters (mm) and 12.5mm, respectively, so that one UBCDD connector needs to occupy a 12.5mm area of 36mm of the motherboard.

Further, the UBCDD connector supports X16 transmission, and in a practical scenario, X16 transmission may not be needed, and X8 and X4 may be used for transmission, which may result in waste of hardware resources. For example, in the configuration shown in fig. 1, the PCIe connector 103 may be connected to an X8 network card, so that the PCIe connector 103 may use X8 (8 differential pairs) for transmission, and the capability of the UBCDD connector 102 for maximally supporting X16 may not be fully utilized, which may result in resource waste.

In order to solve the above-mentioned problem, in the embodiment of the present application, a network card, a RAID card, etc. may be connected by adopting a mode of converting a combined bus (union bus connector, UBC) connector (high-speed connector) +power connector into a PCIe connector. Because the UBC connector and the power connector occupy a smaller area of the main board of the computing device, the wiring difficulty of the main board can be reduced. Meanwhile, the UBC connector can support X8 transmission at maximum, so that hardware resources can be saved by changing the UBCDD connector into a UBC high-speed connector and a power connector under the condition that X16 transmission is not needed (such as the condition that a PCIe connector is connected with an X8 network card). And compared with UBCD connectors, UBC connectors have more application scenes and higher flexibility. In addition, a cable can be used for transmitting PCIe signals between the UBC connector and the PCIe connector, so that transmission loss can be reduced.

The configuration of the computing device and associated connector provided herein is illustrated below in conjunction with fig. 3-13.

Referring to fig. 3, fig. 3 is a schematic structural diagram of another computing device according to an embodiment of the present application. As shown in fig. 3, computing device 200 may include a first circuit board 201, a power connector 202, a UBC connector 203, a PCIe connector 204, a first PCIe device 205, a power module 206, a controller 207, and a second circuit board 208. The PCIe connector 204 may be a PCIe in-line connector, and the first PCIe device 205 may be a network card, a RAID card, or the like. The first circuit board 201 may be a motherboard of a computing device. In some embodiments, computing device 200 may be a heterogeneous server, rack server, high-density server, or the like.

The power supply connector 202 and the UBC connector 203 may be disposed on the first circuit board 201, the first circuit board 201 may be further provided with a power supply module 206 and a controller 207, signal transmission between the power supply module 206 and the power supply connector 202 may be achieved through a PCB wiring or a cable inside the first circuit board 201, signal transmission between the controller 207 and the UBC connector 203 may also be achieved through a PCB wiring or a cable inside the first circuit board 201, specifically, an output end of the power supply module 206 may be connected to a first end of the power supply connector 202 through a power supply interface, and an output end of the controller 207 may be connected to the UBC connector 203 through a PCIe interface of the first circuit board, where the power supply interface may be disposed on the first circuit board, and the power supply interface may be a pin or a connector of the power supply module, and the PCIe interface may be a PCIe pin of the controller or a connector connected to a PCIe pin of the controller. The first terminal of the power connector 202 is connected, and the output terminal of the controller 207 is connected to the first terminal of the UBC connector 203, thereby transmitting power (first power) to the power connector 202 and transmitting a high-speed signal to the UBC connector 203. The PCIe connector 204 may be disposed on the second circuit board 208, and the second end of the power connector 202 and the second end of the UBC connector 203 may be connected to the first end of the PCIe connector 204, outputting power and high speed signals to the PCIe connector 204. Specifically, the second end of the power connector 202 and the second end of the UBC connector 203 may be connected to the first end of the PCIe connector 204 by cables, respectively. The second end of the PCIe connector 204 may be connected to the first PCIe device 205, for example, the first PCIe device 205 may be inserted into a slot of the PCIe connector 204 through its own gold finger, thereby implementing an electrical connection of the first PCIe device 205 to the PCIe connector 204, such that the power module 206 and the controller 207 on the first circuit board 201 output power and high speed signals to the first PCIe device 205. The first circuit board 201 may be a motherboard or other circuit board provided with a processor/controller and the second circuit board 208 may be a switch board, backplane, or riser card of a computing device.

In some embodiments, the power connector 202 and UBC connector 203 may also be disposed on the second circuit board 208 (not shown in fig. 3).

The controller 207 may be a processor (e.g., CPU), a complex programmable logic device (complex programmable logic device, CPLD), etc., which is not limited herein.

Alternatively, the first circuit board 201 and the power connector 202 may be connected by a cable, and power (e.g., 12V or 5V dc) may be output to the power connector 202 through the cable. In some embodiments, the first circuit board 201 may further include a power inlet connector that may be connected to an output interface of the power module, such as an output interface of a power supply unit (power supply unit, PSU) of the server, through a cable so that 12V direct current or the like output after conversion by the power module may be received. The first circuit board 201 may directly transfer the 12V DC power output by the power module to the power connector 202, or the first circuit board 201 may transfer the 12V DC power output by the power module to the power connector 202 after conversion, for example, transfer the 12V DC power to the power connector 202 after conversion into 5V DC power by a direct current/direct current (DC/DC) module. Accordingly, a power output interface (e.g., a 12V or 5V power output interface) on the first circuit board 201 may be connected to the first end of the power connector 202 by a cable.

Illustratively, as shown in FIG. 4, the computing device 200 may also include a PSU 209 and a power inlet connector 210. The power inlet connector 210 may also be disposed on the first circuit board 201. A first end (input) of PSU 209 may receive a 220V ac or 380V ac input and PSU 209 may convert the 220V ac or 380V ac to 48V dc or 12V dc output through a second end (output) of PSU 209. The second end of PSU 209 may be connected to the first end of power inlet connector 210 by a cable, and the second end of power inlet connector 210 may be connected to the first end of power connector 202 by a PCB trace internal to first circuit board 201, or by a cable, to power first PCIe device 205. In some embodiments, other circuit units may also be provided on the first circuit board 201, by which the electricity output by the PSU 209 may be converted. For example, the first circuit board 201 may further be provided with a voltage reducing module 211, where a first end of the voltage reducing module 211 and a second end of the power inlet connector 210 may be connected through a PCB wiring inside the first circuit board 201, or may be connected through a cable. The second end of the buck module 211 may be connected to the first end of the power connector 202 via a PCB trace within the first circuit board 201, or may be connected via a cable to power the first PCIe device 205.

In some embodiments, PSU 209 may be disposed on a fifth circuit board, which may be a power backplane.

In some embodiments, the power connector 202 may be a 2pin power connector or a 4pin power connector, and accordingly, the power connector 202 may be connected with a 2pin power output interface on the first circuit board 201 through 2 cables, or with a 4pin power output interface on the first circuit board 201 through 4 cables. Similarly, the power connector may be connected to the first end of the PCIe connector 204 by 2 cables or 4 cables. For example, as shown in fig. 5A, when the power connector 202 is a 2pin power connector, the first end of the power connector 202 may be connected to the second end of the power module 206 through 2 cables, and the second end of the power connector 202 may also be connected to the first end of the PCIe connector through 2 cables. As shown in fig. 5B, when the power connector 202 is a 4pin power connector, the first end of the power connector 202 may be connected to the second end of the power module 206 through 4 cables, and the second end of the power connector 202 may also be connected to the first end of the PCIe connector through 4 cables.

It should be noted that, the power module 206 in the above embodiment may be a power inlet connector 210 as shown in fig. 4, and may also include a power inlet connector 210 and a voltage reducing module 211, and may also include a PSU 209, a power inlet connector 210 and a voltage reducing module 211, where the above components may be connected by cables, or may be connected by internal wiring of a PCB.

The controller 207 on the first circuit board 201 may also be connected to the UBC connector 203 through a cable (i.e., a first cable), and output a high-speed signal (e.g., a PCIe signal) to the UBC connector 203 through the cable. It should be appreciated that PCIe signals may be used for communication between the controller 207 on the first circuit board and PCIe devices (e.g., GPU cards, network cards, RAID cards, etc.). Accordingly, a pin (pin) for transmitting a PCIe signal on the first end of the UBC connector 203 may be connected with a pin (PCIe interface) for transmitting a PCIe signal output by the controller 207 corresponding to the first circuit board through a cable, and the controller 207 may output a high-speed signal to the UBC connector 203 through the cable. It should be appreciated that other chips or chipsets may also be included on the first circuit board that can also output PCIe signals over the cable to UBC connector 203.

In some real-time modes, the connection between the power module 206 and the power connector 202, the connection between the controller 207 and the UBC connector 203 may also be through an internal PCB trace connection of the first circuit board 201. In some embodiments, PCIe links may be extended through a switch chip, providing more PCIe ports for connecting PCIe devices. Accordingly, pin pins on the first end of the UBC connector 203 for transmitting PCIe signals may be connected to corresponding pin pins on the switch chip for transmitting PCIe signals through cables, or may be connected through PCB traces inside the first circuit board 201. It should be appreciated that the number of cables required for transmission may be different for different PCIE signals such as X4, X8, etc., e.g., the number of cables required for transmission of PCIE signals for X8 may be 2 times the number of cables required for transmission of PCIE signals for X4.

It should be appreciated that PCIe switch chips may be disposed on a switch board, as shown in fig. 6, in one possible implementation, computing device 200 may include a third circuit board 212, on which UBC connector 213, PCIe switch chip 214, UBC connector 215, and UBCDD connector 216 may be disposed. The first end of the UBC connector 213 may be connected to the second end of the UBC connector 203 through a cable, and the second end of the UBC connector 213 may be connected to the first end (input end) of the PCIe switch chip 214 through a PCB trace inside the third circuit board 212, or may be connected through a cable, so as to transmit PCIe signals. The second end (output end) of the PCIe switch chip 214 may be connected to the first end of the UBC connector 215 through a PCB trace inside the third circuit board 212, or may be connected through a cable, the second end of the PCIe switch chip 214 may also be connected to the UBCDD connector 216, and the second end of the PCIe switch chip may be connected to the UBCDD connector 216 through a PCB trace inside the third circuit board 212, or may be connected through a cable. A second end of UBC connector 215 and a first end of PCIe connector 204 may be connected by a cable for transmitting PCIe signals. It should be appreciated that UBCDD connector 216 may also connect to PCIe devices through PCIe connectors, not illustrated in fig. 6.

The signal transmission circuit shown in fig. 6 is merely illustrative, and is not limited to the configuration. In other embodiments of the present application, the number of UBC connectors and UBCDD connectors connected to the PCIe chip may be flexibly configured according to actual requirements. For example, UBCDD connector 216 shown in fig. 6 may also be configured as a UBC connector.

Referring to fig. 7, fig. 7 is a schematic connection diagram of a Controller (CPU) and a PCIe switching chip according to an embodiment of the present application. As shown in fig. 7, when the controller 207 is a CPU, the CPU 207 may include a plurality of Root Ports (RPs), 2 RPs (RP 0 and RP 1) being exemplified in fig. 7. RP0 may be connected to an End Point (EP) device or a bridge device (not shown in fig. 7), RP1 may be connected to an Upstream Port (UP) of PCIe switch chip 214 (switch), PCIe switch chip 214 may include m+1 Downstream Ports (DP) that may be labeled dp_0, dp_1, …, dp_m, respectively, and one end point device may be connected under each downstream port, respectively labeled ep_0, ep_1, …, ep_m, as shown in fig. 7. Illustratively, the root port RP1, which connects upstream ports UP, may occupy bus X and the connection (link) between RP1 and UP may occupy bus N. At this time, the connection from the upstream port to the m+1 downstream ports inside the PCIe switch chip 214 may occupy bus n+1, and the connection between each downstream port and the corresponding endpoint device may occupy bus n+2, bus n+3, …, bus n+2+m, respectively.

As shown in fig. 3, the power connector 202 and the PCIe connector 204 may be connected by a cable (i.e., a third cable) through which an electrical connection with the PCIe connector 204 is made, such that the PCIe connector 204 is used to transmit power (e.g., 12V or 5V dc) signals. In some embodiments, the power connector 202 may be a 2pin power connector or a 4pin power connector, and accordingly, the corresponding power pin pins of the power connector 202 and PCIe connector 204 may be connected by 2 or 4 cables.

UBC connector 203 and PCIe connector 204 may be connected by a cable (i.e., a second cable) through which electrical connection to PCIe connector 204 is made, such that PCIe connector 204 may also be used to transmit high speed signals.

The PCIe connector 204 may include a slot, mainly for receiving a PCIe device, and the first PCIe device 205 may be inserted into the slot of the PCIe connector 204, so that the PCIe connector 204 may output power and PCIe signals to the first PCIe device 205, so that the network card/RAID card 20 may work normally. It should be appreciated that the transmission of PCIe signals may be bi-directional, and that the first PCIe device 205 may also output PCIe signals to the first circuit board 201 (the CPU on the first circuit board 201). It should also be appreciated that PCIe connector 204 may include a variety of different specifications, such as X4, X8, etc., and that the pin count of the PCIe connectors of different specifications may be different and may be used to transmit different PCIe signals, such as X4, X8, etc., supporting different PCIe devices.

It should be appreciated that in general, multiple UBC connectors and multiple power connectors and multiple PCIe connectors may be provided in computing device 200 so that more PCIe devices, such as network cards, RAID cards, etc., may be accessed to extend the functionality of computing device 200. Since the UBC connector and the power connector occupy a smaller area than the UBCDD connector, wiring difficulty can be reduced. For example, referring to fig. 8 and 9, fig. 8 is a schematic size diagram of a UBC connector according to an embodiment of the present application, and fig. 9 is a schematic size diagram of a 2pin power connector according to an embodiment of the present application. The UBC connector has a length and width of about 25.2mm and 11mm as shown in fig. 8, the 2pin power connector has a length of about 11.6mm and a pin width of about 3.0mm, and the power connector may have an actual board area of less than 11.6mm by 3.0mm because only the pin of the power connector is in contact with the board surface as shown in fig. 9. It can be seen that the overall footprint of the UBC connector shown in fig. 8 and the 2pin power connector shown in fig. 9 is less than the UBCDD connector shown in fig. 2.

Further, the cost of UBCDD connectors is higher than the cost of UBC connectors+power connectors, and therefore, employing UBC connectors+power connectors to PCIE connectors may reduce the overall cost of the computing device. And, the reduction in footprint may also save PCB board area, which may further reduce the overall cost of the computing device.

It should be noted that, when the UBCDD connector is changed to the UBC high-speed connector+power connector, a small number of UBCDD connectors may be disposed on the first circuit board 201 so as to support PCIe devices of X16.

It should be noted that the computing device 200 shown in fig. 3 is merely illustrative and not limiting. In other embodiments of the present application, the computing device 200 shown in fig. 3 may include more or fewer devices or modules than illustrated, and is not limited to including only the first circuit board 201, the power connector 202, the UBC connector 203, the PCIe connector 204, the first PCIe device 205, etc. shown in fig. 3. For example, computing device 200 may also include one or more memories (e.g., hard disk), one or more fans, and the like. As another example, the PCIe connector 204, the first PCIe device 205, etc. may not belong to the computing device 200.

In this embodiment, UBC connector 203 may further include a power pin for transmitting power, in addition to a pin for transmitting PCIe signals. Referring to fig. 10, fig. 10 is a schematic structural diagram of another computing device according to an embodiment of the present disclosure. The same parts as those in fig. 3 in fig. 10 are not repeated.

As shown in fig. 10, in one possible implementation, a power module a 217 and a power module b 218 may be disposed on the first circuit board 201. The first ends of the power module a 217 and the power module b 218 may respectively receive different power signals, e.g., the power module a 217 may receive a 12V power signal and the power module b 218 may receive a 5V power signal. The second end of the power module a 217 and the first end of the power connector 202 may be connected by a PCB trace or cable inside the first circuit board 201, and the second end of the power module b 218 and the first end of the UBC connector 203 may also be connected by a PCB trace or cable inside the first circuit board 201 to transmit power signals. The power connector 202 and UBC connector 203 may forward power signals to the PCIe connector 204, which may transmit power signals to the first PCIe device 205. The power signals between UBC connector 203 and PCIe connector 204 may be transmitted through a cable.

It should be noted that, the power supply module a 217 and the power supply module b 218 may be, for example, the power supply inlet connector 210 in fig. 4, or may include the power supply inlet connector 210 and the voltage reducing module 211, or may include the PSU 209, the power supply inlet connector 210 and the voltage reducing module 211, and these components may be connected by cables or may be connected by internal wiring of the PCB.

In some embodiments, the power output by the first circuit board 201 to the power connector 202 and UBC connector 203 may be different. In one possible implementation, the power output by the first circuit board 201 to the power connector 202 and the UBC connector 203 may be direct current of different voltages. For example, the power output from the first circuit board 201 to the power connector 202 may be 12V dc, and the power output from the first circuit board 201 to the UBC connector 203 may be 3.3V dc. Thus, the power that the PCIe connector switches to the first PCIe device 205 may include 12V dc power and 3.3V dc power, which are respectively provided to the corresponding power pin pins of different first PCIe devices 205. In some embodiments, different power signals at different voltages transmitted by power connector 202 and UBC connector 203 may power different PCIe devices.

It should be appreciated that UBC connector 203 typically transmits a smaller power supply that may not meet the power rating requirements of first PCIe device 205, and thus, the purpose of adapting power supply using power connector 202 in fig. 3 is primarily to meet the power rating requirements of first PCIe device 205. In addition, in a practical application scenario, the power connector 202 may be flexibly disposed at a suitable position, not limited to the side of the UBC connector 203, or even limited to the first circuit board 201, so as to improve layout flexibility.

It should be noted that, in one possible implementation, the first end of the power connector 202 and the first end of the UBC connector 203 may be soldered to the first circuit board 201 (e.g., a motherboard) in advance. Also, the pin of the power connector 202 and the power interface (pin) on the first circuit board 201 may be connected together by a cable, and the pin of the UBC connector 203 and the PCIe interface on the first circuit board 201 may be connected together by a cable. The power connector 202 may further reserve a power connector female connector, and the UBC connector 203 may further reserve a UBC connector female connector.

The first pin of the PCIe connector 204 may be soldered to one end of the second cable and the third cable, and the other end of the cable for transmitting PCIe signals (i.e., the second cable) and the cable for partially transmitting power signals (i.e., the second cable) may be packaged as a UBC connector male (i.e., the first plug), and the other end of the cable for transmitting power (i.e., the third cable) may be packaged as a power connector male (i.e., the second plug). Thus, when external PCIe devices are required, the power connector male head of PCIe connector 204 may be plugged with the power connector female head of power connector 202, and the UBC connector male head of PCIe connector 204 may be plugged with the UBC connector female head of UBC connector 203. Meanwhile, the PCIe connector 204 may also reserve an interface (slot), which may be used to connect to PCIe devices (such as a network card, a RAID card, etc.).

Illustratively, as shown in fig. 11, the second cable includes an A2 end and a B2 end, and the third cable includes an A1 end and a B1 end. Wherein, the B2 end of the second cable and the B1 end of the third cable may be soldered with the first end of the PCIe connector 204, the A2 end of the second cable may be packaged as a first plug, and the A1 end of the third cable may be packaged as a second plug. The first PCIe device 205 may be inserted into a slot of the PCIe connector 204 through its own gold finger. It should be appreciated that in some embodiments, the first plug may be a male head, in which case the connection end corresponding to the first plug (e.g., the second end of UBC connector 203 described above) may be a female head. In other embodiments, the first plug may also be a female plug, and in this case, the connection end corresponding to the first plug (such as the second end of the UBC connector 203 described above) may be a male plug. Similarly, the second plug may be a male or female plug.

It should be appreciated that the first, second and third cables described above may include a plurality of wires.

In one possible implementation, PCIe connector 204 may be secured by screws internal to computing device 200, such as on first circuit board 201, or on second circuit board 208, or on another board card of computing device 200. It should be appreciated that the PCIe connector 204 may also be secured within the computing device 200 by other means (e.g., a securing groove), without limitation.

It should be appreciated that UBC connectors have more application scenarios and flexibility than UBCDD connectors, e.g., UBC connectors may be attached to open computing item (open compute project, OCP) cards, m.2 patch panels, etc., while UBCDD connectors may not be attached. In addition, since the power connector female head of the power connector 202 and the power connector male head of the PCIe connector 204 can be flexibly plugged and unplugged, and the UBC connector female head of the UBC connector 203 and the UBC connector male head of the PCIe connector 204 can be flexibly plugged and unplugged, the UBC connector 203 can be flexibly used in a practical application scenario. For example, if PCIe devices such as a network card and a RAID card are required, UBC connector 203 may be connected to a PCIe connector, and then PCIe devices such as a network card and a RAID card may be connected to the PCIe connector via the PCIe connector, and the PCIe connector may be fixed to a circuit board (e.g., first circuit board 201 or second circuit board 208) of the computing device by screws. The circuit board of the computing device may also be secured in the computing device by screws. For another example, if it is necessary to connect an OCP card, an m.2 patch panel (hard disk patch panel), etc., the UBC connector 203 and the OCP card, the m.2 patch panel, etc. may be directly connected by a cable.

Referring to fig. 12, fig. 12 is a schematic structural diagram of another computing device according to an embodiment of the present disclosure. As shown in fig. 12, in this scenario, the second end of UBC connector 203 and the first end of UBC connector 221 may be connected by a cable, and the second end of power connector 202 and the first end of power connector 220 may be connected by a cable. The power connector 220 and UBC connector 221 may be disposed on a fourth circuit board 222, and a 4c+ connector 223 and an OCP card 224 (second PCIe device) may be further disposed on the fourth circuit board 222. The second end of the power connector 220 and the first end of the 4c+ connector 223 may be connected by PCB traces or cables inside the fourth circuit board 222, and the second end of the UBC connector 221 and the first end of the 4c+ connector 223 may also be connected by PCB traces or cables inside the fourth circuit board 222. The OCP card 224 may be connected to the second end of the 4c+ connector 223, for example, the OCP card 224 may be inserted into a slot of the 4c+ connector 223 by its own gold finger. It should be appreciated that in some embodiments, the 4c+ connector 223 may also be replaced with a 4C connector and a 4c+ connector. OCP NIC (network interface card ) 3.0 specification defines two sizes of OCP cards, namely a large card (large form factor, LFF) and a small card (small form factor, SFF), wherein the SFF network card may be a 4c+ interface, and the LFF network card may be a 4c interface and a 4c+ interface. The fourth circuit board 222 may be a back plane of the computing device.

In some embodiments, a re card 219 may also be provided on the first circuit board 201 of the computing device. The repeater card 219 is used primarily for signal relay in computing devices, and may equalize and enhance signals. When the signal transmission distance between the computing device and the PCIe device is long, the signal may be transferred with assistance of the Retimer card 219. Specifically, the output of the controller 207 and the first end of the re-timer card 219 may be connected through a PCB trace or cable inside the first circuit board 201, thereby transmitting a high-speed signal to the re-timer card 219. The second end of the re-timer card 219 and the first end of the UBC connector 203 may be connected by PCB traces or cables inside the first circuit board 201 to transmit high-speed signals to the UBC connector 203.

It can be seen that the UBC connector 203 can be flexibly used according to different scenarios by converting the UBC connector+the power connector into the PCIe connector. For example, if more hard disks need to be attached to the computing device, UBC connector 203 may be attached to an m.2 adapter, and the m.2 adapter may be attached to one or more m.2 Solid State Disks (SSDs), which may extend the storage capacity of computing device 200. As shown in fig. 13, the second end of UBC connector 203 and the first end of UBC connector 226 may be connected by a cable, and the second end of power connector 202 and the first end of power connector 225 may be connected by a cable. The power connector 225 and UBC connector 226 may be provided on the m.2 patch panel 227. The m.2 patch panel 227 may be used to connect one or more m.2 hard disks (second PCIe devices). Specifically, one or more m.2 connectors (such as m.2 connector a 228 and m.2 connector b 229 shown in fig. 13) may also be disposed on the m.2 patch panel 227. The second end of the power connector 225 and the first ends of the m.2 connector a 228 and the m.2 connector b 229 may be connected by PCB traces or cables within the m.2 patch panel 227, and the second end of the UBC connector 226 and the first ends of the m.2 connector a 228 and the m.2 connector b 229 may also be connected by PCB traces or cables within the m.2 patch panel 227. A second end of m.2 hard disk a 230 and m.2 connector a 228 may be connected, and a second end of m.2 hard disk b 231 and m.2 connector b 229 may be connected, for example, m.2 hard disk a 230 may be inserted into a slot of m.2 connector a 228 by its own gold finger, and m.2 hard disk b 231 may be inserted into a slot of m.2 connector b 229 by its own gold finger.

It will be appreciated that UBCDD connectors are typically provided on larger space motherboards because of their relatively large size. The UBC connector and the power connector are relatively small, so the UBC connector and the power connector can be flexibly arranged according to practical situations and can be arranged on other boards, such as a switch board, a power backboard and the like. Specifically, in some embodiments, UBC connector 203 and power connector 202 may be disposed on the same board. For example, UBC connector 203 and power connector 202 may each be disposed on first circuit board 201 of computing device 200. As another example, UBC connector 203 and power connector 202 may both be disposed on a switch board (i.e., a board card on which a switch chip resides) of computing device 200. In other embodiments, UBC connector 203 and power connector 202 may be disposed on different boards, e.g., UBC connector 203 may be disposed on first circuit board 201 of computing device 200 and power connector 202 may be disposed on a power backplane of computing device 200. As another example, UBC connector 203 may be disposed on a switch board of computing device 200 and power connector 202 may be disposed on a power backplane of computing device 200.

Different computing device models may include different hardware devices. For example, assume that machine type a includes a RAID card, not including an OCP card, and machine type B includes an OCP card, not including a RAID card. Therefore, for a motherboard including only UBCDD connectors, two models may not be adapted. And if UBCDD connector on the motherboard is changed to UBC connector + power connector, it can be adapted to both models. For model a, UBC connectors may be connected to OCP cards through 4c+ connectors, as described above with respect to fig. 12. For model B, UBC connectors and power connectors may be attached to PCIe connectors and then to RAID cards through PCIe connectors, and PCIe connectors may be screwed to a circuit board of a computing device, such as first circuit board 201 or second circuit board 208 described above. It should be appreciated that, by adopting the manner of converting the UBC connector and the power connector into the PCIe connector, the UBC connector may be shared under different models, so that development of a motherboard may be reduced, and a development period of the computing device may be shortened.

It should be noted that the computing device 200 shown in fig. 6 and 7 is merely exemplary and not limiting.

In the implementation manner, the PCB area can be saved and the wiring difficulty can be reduced by adopting the manner of converting the UBC connector and the power connector into the PCIe connector. And by adopting the UBC connector, the application scene can be expanded, and the flexibility of application is improved. In addition, in the embodiment of the application, the loss can be reduced and the signal quality can be improved by transmitting the high-speed signal (PCIe signal) through the cable.

It should be noted that, the related information (i.e., the same information or similar information) and the related description in the above different embodiments may refer to each other.

It is to be understood that "connected" in this application may be understood as directly connected (i.e., electrically connected); it is also to be understood that the connection is indirect, i.e., through other devices, elements, modules, means, etc.

The technical terms used in the embodiments of the present invention are only used to illustrate specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Further, as used in the specification, the terms "comprises" and/or "comprising" mean that there is a stated feature, integer, step, operation, element, and/or component, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components.

It should also be understood that in various embodiments of the present application, "at least one", "one or more" means one, two or more than two. The term "and/or" is used to describe an association relationship of associated objects, meaning that there may be three relationships; for example, a and/or B may represent: a alone, a and B together, and B alone, wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements, if any, in the claims below are intended to include any structure, material, or act for performing the function in combination with other specifically claimed elements. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed.

The foregoing embodiments have been provided for the purpose of illustrating the technical solution and advantageous effects of the present application in further detail, and it should be understood that the foregoing embodiments are merely illustrative of the present application and are not intended to limit the scope of the present application, and any modifications, equivalents, improvements, etc. made on the basis of the technical solution of the present application should be included in the scope of the present application.

Claims

1. The signal transmission circuit is characterized by comprising a first circuit board, a combined bus UBC connector and a power connector;

the power interface of the first circuit board is connected with the first end of the power connector, and the peripheral component interconnect express (PCIe) interface of the first circuit board is connected with the first end of the UBC connector; the second end of the power connector is used for being connected with the first PCIe device through the peripheral component interconnect express (PCI express) connector to supply power for the first PCIe device; the second end of the UBC connector is configured to connect to the first PCIe device through the PCIe connector to transmit PCIe signals to the first PCIe device.

2. The signal transmission circuit of claim 1, wherein the second end of the UBC connector is further configured to connect to a second PCIe device.

3. The signal transmission circuit of claim 1 or 2, further comprising a power module on the first circuit board for transmitting a first power to the power connector and a controller for transmitting a PCIe signal to the UBC connector; the power connector is used for outputting the first power supply to the PCIe connector, and the UBC connector is used for outputting the PCIe signal to the PCIe connector; the PCIe connector is configured to output the first power supply and the PCIe signal to the first PCIe device.

4. A signal transmission circuit according to any one of claims 1-3, wherein the UBC connector and the power connector are provided on the first circuit board and/or on a second circuit board; when the UBC connector and the power connector are arranged on the first circuit board, a power interface of the first circuit board is connected with a first end of the power connector through a cable or a Printed Circuit Board (PCB) wiring, and a PCIe interface of the first circuit board is connected with a first end of the UBC connector through a cable or a Printed Circuit Board (PCB) wiring; when the UBC connector and the power connector are arranged on the second circuit board, the power interface of the first circuit board is connected with the first end of the power connector, and the PCIe interface of the first circuit board is connected with the first end of the UBC connector through cables.

5. The signal transmission circuit of any of claims 1-4, wherein the second end of the UBC connector is connected to the first end of the PCIe connector through a second cable and the second end of the power connector is connected to the first end of the PCIe connector through a third cable.

6. The signal transmission circuit of claim 5, wherein the first end of the PCIe connector comprises at least one first pin and at least one second pin, the at least one first pin soldered to one end of the second cable, the other end of the second cable forming a first plug for mating with the second end of the UBC connector; the at least one second pin is welded with one end of the third cable, and the other end of the third cable forms a second plug which is used for being spliced with the second end of the power connector.

7. The signal transmission circuit of any one of claims 1-6, wherein the first end of the UBC connector and the first end of the power connector are soldered to the first circuit board.

8. The signal transmission circuit of any one of claims 1-7, wherein the PCIe connector is fixedly disposed on the first circuit board or the second circuit board.

9. The signal transmission circuit of any one of claims 1-8, wherein the first PCIe device is a network card, a redundant array of independent disks card, or a graphics card.

10. The signal transmission circuit of any of claims 2-9, wherein the second PCIe device is an open computing item card or a hard disk adapter board.

11. The computing device is characterized by comprising a first circuit board and a second circuit board, wherein a power module, a controller, a power connector and a joint bus (UBC) connector are arranged on the first circuit board, and a peripheral component interconnect (PCIe) connector and PCIe device are arranged on the second circuit board; the power module is connected with the first end of the power connector through a cable or a Printed Circuit Board (PCB) wiring, the controller is connected with the first end of the UBC connector through a cable or a PCB wiring, the second end of the UBC connector is connected with the first end of the PCIe connector through a second cable, the second end of the power connector is connected with the first end of the PCIe connector through a third cable, and the second end of the PCIe connector is connected with the PCIe device.