CN111563058A - Device for switching PCIE Gen4 in server - Google Patents

Device for switching PCIE Gen4 in server Download PDF

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Publication number
CN111563058A
CN111563058A CN202010402532.3A CN202010402532A CN111563058A CN 111563058 A CN111563058 A CN 111563058A CN 202010402532 A CN202010402532 A CN 202010402532A CN 111563058 A CN111563058 A CN 111563058A
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CN
China
Prior art keywords
pcie
connector
board
gen4
mainboard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010402532.3A
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Chinese (zh)
Inventor
义日贵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inspur Business Machines Co Ltd
Inspur Power Commercial Systems Co Ltd
Original Assignee
Inspur Business Machines Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inspur Business Machines Co Ltd filed Critical Inspur Business Machines Co Ltd
Priority to CN202010402532.3A priority Critical patent/CN111563058A/en
Publication of CN111563058A publication Critical patent/CN111563058A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/18Packaging or power distribution
    • G06F1/183Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/20Cooling means
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026PCI express

Abstract

The invention discloses a device for switching PCIE Gen4 in a server, which comprises a mainboard, a PCIE adapter plate and an IO plate, wherein a CPU arranged on the mainboard is connected with a mainboard connector arranged on the mainboard through a PCIE Gen4 bus, the mainboard connector is connected with the PCIE adapter plate, the PCIE adapter plate is connected with the IO plate, and the mainboard connector is connected with PCIE Gen4 equipment arranged in a PCIE Gen4 slot of the IO plate through the PCIE adapter plate. Through setting up the mainboard connector on the mainboard, through connecting the PCIE keysets, be connected PCIE keysets and IO board again, realize that CPU on the mainboard is connected with the PCIE Gen4 equipment in the PCIE Gen4 groove of IO board, when the server supports PCIE Gen4 equipment, saved high-speed backplate design, change high-speed cable interconnection design into and improved system heat-sinking capability, easy maintainability ability, high-speed signal link loss has been reduced, the operational reliability of server has been improved.

Description

Device for switching PCIE Gen4 in server
Technical Field
The invention relates to the technical field of PCIE switching in a server, in particular to a device for switching PCIE Gen4 in the server.
Background
The performance of an IO interface of a server is one of important performance indexes of the server, and a PCIE interface is the most important IO interface of the server. With the continuous upgrading of the technology, the PCIE interface standard is upgraded from 1.0 to 2.0 and then to 3.0.
Currently, server products supporting PCIE 4.0 interfaces already exist in the market. Newer interface standards imply higher transmission bandwidths and rates, placing higher demands on server hardware design. In the prior server technology, products supporting a PCIE 3.0 interface are very common, and the bit rate is 8 Gbps. With the gradual appearance of the PCIE 4.0 interface with a bit rate of 16Gbps in the server technology, the server system design faces more challenges, for example, the chip driving capability, the PCB board loss, the connector loss, the cable loss, etc. become more severe than the PCIE 3.0 interface. Therefore, the link condition in the existing system design can not meet the link loss requirement of the PCIE 4.0 interface.
In a common PCIE switching method in the prior art, as shown in fig. 1, a PCIE Gen3 signal of a CPU4 is first connected to a high-speed backplane 3 from a motherboard 1 through a high-speed backplane connector, and then connected to an IO board 2 from the high-speed backplane 3 through a high-speed backplane 3 connector, and connected to PCIE devices on the IO board 2 through a PCIE slot 5. The design is generally used for servers larger than 2U, such as 3U, 4U, 6U and the like, and has better expansion capability of PCIE equipment, such as a plurality of network equipment, storage equipment and the like. Therefore, it is necessary to support larger system power consumption and better high-speed interconnection capability.
However, such designs often face two risks:
the first vertical high-speed back plate is designed to keep out wind, and the heat dissipation capability of the system is limited when the power consumption of the system is large;
second, PCIE signal need pass through multistage PCB integrated circuit board such as mainboard, high-speed backplate, IO board, lead to the signal loss great, difficult in order to support higher signal rate.
Disclosure of Invention
The invention provides a device for switching PCIE Gen4 in a server, which improves the ventilation efficiency in a case so as to improve the heat dissipation capacity, reduces the loss of a PCIE Gen4 signal link, and can realize the speed of upgrading PCIE equipment in the server from PCIE Gen3 to PCIE Gen 4.
In order to solve the technical problem, the invention provides a device for switching a PCIE Gen4 in a server, which comprises a mainboard, a PCIE adapter board and an IO board, wherein a CPU arranged on the mainboard is connected with a mainboard connector arranged on the mainboard through a PCIE Gen4 bus, the mainboard connector is connected with the PCIE adapter board, the PCIE adapter board is connected with the IO board, and the mainboard connector is connected with PCIE Gen4 equipment arranged in a PCIE Gen4 slot of the IO board through the PCIE adapter board.
The board connector is connected with the PCIE adapter plate in such a way that the board connector is connected with an adapter board connector arranged on the PCIE adapter plate, and the adapter board connector is connected with an adapter card arranged on the PCIE adapter plate or connected with an adapter card arranged on the PCIE adapter plate.
The motherboard connector and the adapter board connector are Slimline connectors or Examax connectors.
The main board connector is connected with the adapter board connector of the PCIE adapter board through a Slimline cable or the main board connector is connected with the adapter card of the PCIE adapter board through a Slimline-to-Examax cable.
The number of the CPUs arranged on the mainboard is at least two.
The surfaces of the IO board and the PCIE adapter board are on the same plane, and are on different planes with the surface of the mainboard.
The PCIE adapter plate is connected with the IO plate through a backplane connector.
The plurality of the board connectors are connected with the plurality of adapter connectors arranged on the PCIE adapter board in a one-to-one correspondence manner, or the plurality of the board connectors are connected with the adapter cards arranged on the PCIE adapter board in a one-to-one correspondence manner.
The device of adversion PCIE Gen4 in server, through set up the mainboard connector on the mainboard, through connecting the PCIE keysets, be connected PCIE keysets and IO board again, realize that CPU on the mainboard is connected with the PCIE Gen4 equipment in the PCIE Gen4 groove of IO board, when the server supports PCIE Gen4 equipment, saved high-speed backplate design, change to high-speed cable interconnection design and improved system heat-sinking capability, easy maintainability, reduced high-speed signal link loss, the operational reliability of server has been improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a PCIE switch structure in a server in the prior art;
fig. 2 is a schematic structural diagram of an embodiment of an apparatus for switching PCIE Gen4 in a server provided in the present application;
fig. 3 is a schematic structural diagram of another embodiment of an apparatus for switching PCIE Gen4 in a server provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1-3, fig. 1 is a schematic diagram of a PCIE switch structure in a server in the prior art; fig. 2 is a schematic structural diagram of an embodiment of an apparatus for switching PCIE Gen4 in a server provided in the present application; fig. 3 is a schematic structural diagram of another embodiment of an apparatus for switching PCIE Gen4 in a server provided in the present application.
In a specific embodiment, the present invention provides a device for switching a PCIE Gen4 in a server, including a motherboard 10, a PCIE adapter board 20, and an IO board 30, where a CPU11 disposed on the motherboard 10 is connected to a motherboard connector 12 disposed on the motherboard 10 through a PCIE Gen4 bus, the motherboard connector 12 is connected to the PCIE adapter board 20, the PCIE adapter board 20 is connected to the IO board 30, and the motherboard connector 12 is connected to a PCIE Gen4 device disposed in a PCIE Gen4 slot 31 of the IO board 30 through the PCIE adapter board 20.
Through set up mainboard connector 12 on mainboard 10, through connecting PCIE keysets 20, be connected PCIE keysets 20 with IO board 30 again, realize CPU11 on mainboard 10 and the PCIE Gen4 equipment connection in PCIE Gen4 groove 31 of IO board 30, when the server supports PCIE Gen4 equipment, saved high-speed backplate design, change into high-speed cable interconnection design and improved the system heat-sinking capability, easy maintainability, high-speed signal link loss has been reduced, the operational reliability of server has been improved.
The device for switching the PCIE Gen4 in the server in the present invention does not limit the connection manner between the board connector 12 and the PCIE patch board 20, and may be a direct connection or an indirect connection. That is, the connection between the host board connector 12 and the PCIE adapter board 20 may be that the host board connector 12 is connected to an adapter board connector 21 disposed on the PCIE adapter board 20, and the adapter board connector 21 is connected to an adapter board disposed on the PCIE adapter board 20 and indirectly connected through the adapter board connector 21; or the board connector 12 is connected with a patch card arranged on the PCIE patch panel 20, and is directly connected.
The indirect connection mode is adopted, the connection equipment is simple, the type and the number of the corresponding connectors are not limited, and the mainboard connector 12 and the adapter plate connector 21 are Slimline connectors or Examax connectors or other types of connectors.
Correspondingly, the cables used in the connection process are not limited in the present invention, and the motherboard connector 12 is connected to the interposer connector 21 of the PCIE interposer 20 through a Slimline cable 13 or the motherboard connector 12 is connected to the riser card of the PCIE interposer 20 through a Slimline-to-Examax cable 14.
In the present invention, the number of the CPUs 11 on the motherboard 10 is not limited, and may be one or more, and in general, a plurality of CPUs 11 are used in order to improve the operating efficiency of the server, so that the number of the CPUs 11 provided on the motherboard 10 is at least two.
In the invention, the cable is adopted to connect the PCIE adapter plate 20 and the mainboard 10, instead of simultaneously connecting the IO plate 30, the mainboard 10 and the high-speed backboard by adopting a backboard connector in the prior art, a hard connection mode of the backboard connector is not adopted, but a soft connection mode of the cable is adopted, so that the PCIE adapter plate can be not in the same plane with the mainboard 10, the heat dissipation of the mainboard 10 is not influenced, and the cable can be adopted in a connection mode of the cable according to the requirement, so that the purpose of being far away from the mainboard 10 is realized, the mutual interference can be further reduced, and the equipment can be randomly arranged by a worker. Therefore, in an embodiment, the surfaces of the IO board 30 and the PCIE adapter board 20 are on the same plane, and are on different planes from the surface of the motherboard 10, it should be noted that the surfaces of the IO board 30 and the PCIE adapter board 10 are on different planes, or may be on parallel planes, that is, at different heights, and if the distance is relatively long, the surfaces of the IO board and the PCIE adapter board may also be on the same plane without affecting heat dissipation, but this situation is avoided as much as possible, and the design difficulty is reduced.
The connection mode of the PCIE adapter board 20 and the IO board 30 is not limited in the present invention, and a connection mode in the prior art may be adopted, or a new connection mode may be adopted. In one embodiment, the PCIE interposer 20 and the IO board 30 are connected by a backplane connector.
In the present invention, connection links from a plurality of CPUs 11 to PCIE Gen4 devices may be the same or different, for example, a connection link of one CPU11 is a direct connection mode, and another connection link is an indirect connection mode, but in order to simplify a process mode and reduce process difficulty, a plurality of links generally adopt the same structure, for example, a plurality of motherboard connectors 12 are connected to a plurality of interposer connectors 21 disposed on the PCIE interposer 20 in a one-to-one correspondence manner, or a plurality of motherboard connectors 12 are connected to the interposer cards disposed on the PCIE interposer 20 in a one-to-one correspondence manner.
In one embodiment, the PCIE Gen4 signal of the CPU11 on the motherboard 10 is connected to the PCIE adapter board 20 through the Slimline cable 13 capable of supporting 16G rate, and the PCIE Gen4 signal on the PCIE adapter board 20 is connected to the PCIE Gen4 slot 31 bit on the IO board 30 through the directly-inserted backplane connector. The mainboard 10 is on a horizontal plane, the IO board 30 and the PCIE adapter board 20 are on another horizontal plane, but the interconnection does not need to pass through a vertical high-speed backboard, thereby ensuring the expandable space of a server system, and simultaneously avoiding the adverse effect of the high-speed backboard on the heat dissipation of the system, and on the other hand, the link loss of high-speed cables such as slim line and the like is lower than that of a PCB (printed circuit board) high-speed backboard, so that the link loss when a PCIE Gen4 signal is taken is lower than that when a PCIE Gen4 signal is taken in the prior art, thereby being capable of supporting PCIE Gen4 equipment by a server, and compared with the interconnection design of the high-speed backboard, the high-speed interconnection design based on the cables has the advantages of lower.
On the basis of the above embodiment, in another embodiment, the PCIE signal sent by the CPU11 on the motherboard 10 is directly connected to the terminal of the Examax connector of the IO board 30 through a customized Slimline-to-Examax cable, that is, a direct connection manner is adopted. One end of the slim line to Examax cable 14 is installed on the slim line connector of the motherboard 10, and the other end is fixed to the PCIE adapter board 20, but there is no actual PCIE Gen4 signal trace on the PCIE adapter board 20, which only plays a role in fixing the structure, so that the IO board 30 can be plugged into the PCIE adapter card in a whole module. Therefore, the IO board 30 in the design still ensures the hot plug capability, the hot plug characteristic cannot be lost due to the interconnection with the cable, and the hot plug design difficulty cannot be improved. Meanwhile, because PCB routing of PCIE signals on the PCIE interposer 20 is reduced, link loss of PCIE Gen4 signals can be further reduced. The link loss of the PCIE Gen4 signal is further optimized in the embodiment, the cable customization degree is higher, and the server design can be selected at will according to the actual link length condition. For the requirement of PCIE Gen4 high-speed signal routing, the direct connection structure may also be used in combination with a scheme of direct connection and indirect connection in actual design, for example: signals larger than 16G adopt a direct connection structure, and signals smaller than 16G adopt an indirect connection structure.
In summary, in the apparatus for switching a PCIE Gen4 in a server provided in the embodiment of the present invention, by setting a motherboard connector on a motherboard, connecting a PCIE adapter board, and then connecting the PCIE adapter board to an IO board, a CPU on the motherboard is connected to a PCIE Gen4 device in a PCIE Gen4 slot of the IO board, and while the server supports PCIE Gen4 devices, the design of a high-speed backplane is omitted, and a high-speed cable interconnection design is changed to improve the heat dissipation capability of a system, the easy maintenance capability, the loss of a high-speed signal link is reduced, and the operation reliability of the server is improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. The device for switching PCIE Gen4 in the server is characterized by comprising a mainboard, a PCIE adapter board and an IO board, wherein the CPU and the mainboard connector of the mainboard are connected through a PCIE Gen4 bus, the mainboard connector is connected with the PCIE adapter board, the PCIE adapter board is connected with the IO board, and the mainboard connector is connected with PCIE Gen4 equipment in a PCIE Gen4 groove of the IO board through the PCIE adapter board.
2. The apparatus of claim 1, wherein the board connector is connected to the PCIE interposer such that the board connector is connected to an interposer connector disposed on the PCIE interposer, the interposer connector is connected to an interposer disposed on the PCIE interposer, or the board connector is connected to an interposer disposed on the PCIE interposer.
3. The apparatus of claim 2, wherein the motherboard connector, the patch panel connector is a slim line connector or an Examax connector.
4. The apparatus of claim 3, wherein the motherboard connector is connected to a patch panel connector of the PCIE patch panel via a Slimline cable or the motherboard connector is connected to a patch card of the PCIE patch panel via a Slimline to Examax cable.
5. The apparatus for switching PCIE Gen4 in a server of claim 4, wherein the number of the CPUs provided on the motherboard is at least two.
6. The apparatus of claim 5, wherein surfaces of the IO board and the PCIE interposer are in a same plane and are in a different plane than a surface of the motherboard.
7. The apparatus of claim 6, wherein the PCIE Gen4 switch board and the IO board are connected by a backplane connector.
8. The apparatus of claim 7, wherein a plurality of the motherboard connectors are connected to a plurality of the interposer connectors disposed on the PCIE interposer in a one-to-one correspondence, or a plurality of the motherboard connectors are connected to the interposer connectors disposed on the PCIE interposer in a one-to-one correspondence.
CN202010402532.3A 2020-05-13 2020-05-13 Device for switching PCIE Gen4 in server Pending CN111563058A (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203658929U (en) * 2013-11-11 2014-06-18 北海创新科存储技术有限公司 Server storage device of pseudo controllerframework
CN205229924U (en) * 2015-12-16 2016-05-11 山东海量信息技术研究院 PCIE expands integrated circuit board based on high -end server
CN107463522A (en) * 2017-08-17 2017-12-12 郑州云海信息技术有限公司 Oculink adapters and server based on the Oculink adapters, the method for connecting PCIE device
CN207367120U (en) * 2017-08-25 2018-05-15 郑州云海信息技术有限公司 A kind of CPU interacted systems of PCIE extension frameworks and two-way server based on AMD platforms
CN208766652U (en) * 2018-09-14 2019-04-19 贵州浪潮英信科技有限公司 It is a kind of to convert the U.2 adapter of hard disk connection and mounting means
US20190197005A1 (en) * 2017-12-25 2019-06-27 Giga-Byte Technology Co.,Ltd. Interface card module and adapter card thereof
CN210129223U (en) * 2019-09-06 2020-03-06 苏州浪潮智能科技有限公司 RAID adapter plate and system for realizing RAID

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203658929U (en) * 2013-11-11 2014-06-18 北海创新科存储技术有限公司 Server storage device of pseudo controllerframework
CN205229924U (en) * 2015-12-16 2016-05-11 山东海量信息技术研究院 PCIE expands integrated circuit board based on high -end server
CN107463522A (en) * 2017-08-17 2017-12-12 郑州云海信息技术有限公司 Oculink adapters and server based on the Oculink adapters, the method for connecting PCIE device
CN207367120U (en) * 2017-08-25 2018-05-15 郑州云海信息技术有限公司 A kind of CPU interacted systems of PCIE extension frameworks and two-way server based on AMD platforms
US20190197005A1 (en) * 2017-12-25 2019-06-27 Giga-Byte Technology Co.,Ltd. Interface card module and adapter card thereof
CN208766652U (en) * 2018-09-14 2019-04-19 贵州浪潮英信科技有限公司 It is a kind of to convert the U.2 adapter of hard disk connection and mounting means
CN210129223U (en) * 2019-09-06 2020-03-06 苏州浪潮智能科技有限公司 RAID adapter plate and system for realizing RAID

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