CN117407347B - PCIe switching chip, control method thereof and electronic equipment - Google Patents
PCIe switching chip, control method thereof and electronic equipment Download PDFInfo
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- CN117407347B CN117407347B CN202311725762.3A CN202311725762A CN117407347B CN 117407347 B CN117407347 B CN 117407347B CN 202311725762 A CN202311725762 A CN 202311725762A CN 117407347 B CN117407347 B CN 117407347B
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012545 processing Methods 0.000 claims abstract description 43
- 238000012546 transfer Methods 0.000 claims abstract description 14
- 238000004891 communication Methods 0.000 claims abstract description 10
- 230000008054 signal transmission Effects 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 238000013507 mapping Methods 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 2
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- 230000000694 effects Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a PCIe transfer chip, a control method thereof and electronic equipment, wherein the PCIe transfer chip comprises a processing unit, a PCIe signal interface module and at least one group of equipment interface modules, and the equipment interface modules comprise a protocol matching unit and equipment ports; the protocol matching unit is respectively connected with the PCIe signal interface module, the corresponding equipment port and the processing unit; the PCIe signal interface module is also used for connecting an upper computer; the equipment port is also used for connecting with lower equipment; after the PCIe transfer chip is electrified, the processing unit sends a configuration instruction to the protocol matching unit; and the protocol matching unit executes a target protocol corresponding to the configuration instruction according to the received configuration instruction. In the same PCIe transfer chip, the communication protocols of the device ports are configured through the configuration instructions, so that the PCIe transfer of the lower devices of different protocols is realized, the interface requirements of IT device diversification are met, and the area of the PCIe transfer chip is reduced.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a PCIe switching chip, a control method thereof and electronic equipment.
Background
Currently, a central processing unit (Central Processing Unit, abbreviated as CPU) is generally provided with a high-speed Serial computer expansion bus standard (Peripheral Component Interconnect express, abbreviated as PCIe) interface and a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, abbreviated as DDR) high-speed interface, and no Serial ATA (SATA) port and no universal Serial bus (Universal Serial Bus, abbreviated as USB) port are provided; information technology (Informtion Technology, abbreviated as IT) devices such as a general server, a storage device, a computer and the like need to connect a SATA port to a SATA solid state Disk (Solid State Drive, abbreviated as SSD) or to connect to a SATA mechanical Hard Disk (Hard Disk Drive, abbreviated as HDD); the USB port is connected with a mouse, a keyboard, a USB flash disk (U disk for short) and other devices.
In order to meet the requirements of IT equipment for connecting devices such as a hard disk, a mouse and a U disk, how to realize conversion from PCIe to SATA and vice versa becomes a problem focused by those skilled in the art.
Disclosure of Invention
The present invention is directed to a PCIe switching chip, a control method thereof and an electronic device, so as to at least partially improve the above-mentioned problems.
In order to achieve the above object, the technical scheme adopted by the embodiment of the invention is as follows:
in a first aspect, an embodiment of the present invention provides a PCIe switch chip, where the PCIe switch chip includes: the device comprises a processing unit, a PCIe signal interface module and at least one group of device interface modules, wherein the device interface modules comprise a protocol matching unit and a device port; the protocol matching unit is respectively connected with the PCIe signal interface module, the corresponding equipment port and the processing unit; the PCIe signal interface module is also used for connecting an upper computer; the equipment port is also used for connecting with lower equipment; the processing unit is used for sending a configuration instruction to the protocol matching unit; the protocol matching unit is used for executing a target protocol corresponding to the configuration instruction according to the received configuration instruction; the type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different.
In a second aspect, an embodiment of the present invention provides a PCIe switching chip control method, which is applied to the PCIe switching chip, where the method includes: after the PCIe transfer chip is powered on, the processing unit sends a configuration instruction to the protocol matching unit; the protocol matching unit executes a target protocol corresponding to the configuration instruction according to the received configuration instruction; the type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different.
In a third aspect, an embodiment of the present invention provides an electronic device, including: PCIe switching chip as described above.
Compared with the prior art, the PCIe transfer chip, the control method and the electronic equipment thereof provided by the embodiment of the invention comprise the following steps: the device comprises a processing unit, a PCIe signal interface module and at least one group of device interface modules, wherein the device interface modules comprise a protocol matching unit and a device port; the protocol matching unit is respectively connected with the PCIe signal interface module, the corresponding equipment port and the processing unit; the PCIe signal interface module is also used for connecting an upper computer; the equipment port is also used for connecting with lower equipment; the processing unit is used for sending a configuration instruction to the protocol matching unit; the protocol matching unit is used for executing a target protocol corresponding to the configuration instruction according to the received configuration instruction; the type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different. In the same PCIe transfer chip, the communication protocols of the device ports can be configured through configuration instructions, lower devices of different protocols can be transferred through PCIe, the interface requirements of IT device diversification are met, and the area of the PCIe transfer chip is reduced as much as possible.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a PCIe switching chip according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a PCIe adapter chip according to an embodiment of the present invention;
FIG. 3 is a third schematic diagram of a PCIe adapter chip according to an embodiment of the present invention;
fig. 4 is a flowchart of a PCIe switching chip control method according to an embodiment of the present invention.
In the figure: 10-a processing unit; 20-PCIe signal interface module; 30-a device interface module; 210-PCIe signal interface; 220-extensible host controller interface; 230-a USB hub unit; 231-USB3.0 hub; 232-USB2.0 hub; 240-a signal transmission unit; 241-first order selector; 242-second order selector; 310-a protocol matching unit; 311-serial ATA advanced host controller interface; 312-USB3.0 interface; 313-USB2.0 interface; 320-device port.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "upper", "lower", "inner", "outer", etc., are directions or positional relationships based on those shown in the drawings, or those that are conventionally put in use, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific direction, be constructed and operated in a specific direction, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed", "connected" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
At present, a CPU is usually provided with a PCIe interface and a memory DDR high-speed interface, and a SATA port and a USB port are not arranged; and IT devices such as a general server, a storage device, a computer and the like need SATA ports to connect with hard disks (SSD and HDD), USB ports to connect with mice, a USB disk and the like. Therefore, IT device motherboard needs to connect PCIe to SATA bridge and PCIe to USB bridge.
The current PCIe bridge chip has single function, and a single PCIe bridge chip can only realize the function of converting PCIe into SATA interface or converting PCIe into USB interface. In the PCIe to USB3.0/2.0 bridge, the same DownStream Port (also referred to as a device Port in the present invention, referred to as a DS Port for short) supports USB3.0 and USB2.0 rates, the USB3.0 interface (USB 3.0 PHY) is directly connected to the USB3.0 HUB (USB 3.0 HUB), the USB2.0 interface (USB 2.0 PHY) is directly connected to the USB2.0 HUB (USB 2.0 HUB), and the USB3.0 Gbps signal line and the USB2.0 480Mbps signal line are independently routed.
In the PCIe to SATA3.0 bridge chip, each serial ATA advanced host controller interface (Serial ATA Advanced Host Controller Interface, abbreviated as AHCI Ctrl) is connected to a PCIe signal interface module (PCIe interface) by using a direct connection signal.
Usually, IT devices such as a server, a storage device, a computer and the like need to output the SATA port and the USB port at the same time, so that the main board is provided with a PCIe to SATA chip and a PCIe to USB chip at the same time, which has higher cost and occupies a larger PCB area.
In order to overcome the above problems, the embodiment of the invention provides a PCIe switching chip, which integrates the function of PCIe to multiple other protocols including, but not limited to, SATA protocols and USB protocols, so that the same device port can support multiple devices (including SATA devices and USB devices), and the number of PCIe bridges is reduced, thereby reducing the chip area.
Specifically, referring to fig. 1, fig. 1 is a schematic structural diagram of a PCIe switching chip according to an embodiment of the present invention.
As shown in fig. 1, the PCIe switching chip includes: the device interface module 30 includes a protocol matching unit 310 and a device port 320.
The processing unit 10 may be, but not limited to, a micro control unit (Microcontroller Unit, abbreviated as MCU).
The protocol matching unit 310 is connected to the PCIe signal interface module 20, the corresponding device port 320, and the processing unit 10, respectively.
The PCIe signal interface module 20 is further configured to connect to a host computer (not shown in the figure), which may be, but is not limited to, a CPU, and the host computer is a PCIe-enabled device.
The device port 320 is also used to connect with a lower device (not shown in the figure), which may be, but not limited to, a hard disk, a usb disk, a mouse, and the like.
The processing unit 10 is configured to send a configuration instruction to the protocol matching unit 310.
The protocol matching unit 310 is configured to execute a target protocol corresponding to the configuration instruction according to the received configuration instruction.
The type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different.
Optionally, the target protocol is any protocol other than PCIe protocol, and may be any one of SATA protocol, USB3.0 protocol, and USB2.0 protocol. The protocol matching unit 310 may support a variety of communication protocols (e.g., SATA protocol or USB3.0 protocol, USB2.0 protocol), one of which matches the received configuration instruction, as a target protocol. When the configuration instruction changes, the target protocol executed by the configuration instruction correspondingly changes.
Optionally, the PCIe signal interface module 20 is configured to convert downstream data from a PCIe protocol to a target protocol, and convert upstream data from the target protocol to the PCIe protocol.
In the scheme of the invention, in the same PCIe switching chip, the communication protocol of the device port 320 can be configured through the configuration instruction, so that the PCIe switching of the lower devices with different protocols is realized, the diversified interface requirements of IT devices are met, and the area of the PCIe switching chip is reduced as much as possible.
The present embodiment also provides an alternative implementation as to how the processing unit 10 obtains the configuration instructions, please refer to the following.
The processing unit 10 is provided with a set of IO pins (for example, GPIOs), and a user can set the IO pins when the device (PCIe switching chip) is powered down, where the setting content includes pull-up and pull-down. At power up of the device, the processing unit 10 may receive a configuration signal through the IO pin, where the configuration signal is a combined signal of a plurality of IO pins. Taking 3 IO pins and 2 groups of device interface modules 30 as examples, when the configuration signal is 0000, the target protocols corresponding to the 2 groups of device interface modules 30 (i.e. there are 2 protocol matching units 310) are all SATA protocols, when the configuration signal is 0001, the target protocols corresponding to the 2 groups of device interface modules 30 are all USB3.0 protocols, when the configuration signal is 0010, the target protocols corresponding to the 2 groups of device interface modules 30 are all USB2.0 protocols, and so on, under different configuration signals, at least one group of target protocols of device interface modules 30 change.
In an alternative embodiment, the processing unit 10 is further configured to determine a configuration instruction corresponding to each protocol matching unit 310 according to the signal received by the IO pin.
In an alternative embodiment, the processing unit 10 may match the received configuration signal with a preset mapping relationship table, so as to determine a target protocol corresponding to each protocol matching unit 310, and further determine a configuration instruction corresponding to each protocol matching unit 310.
The mapping relation table may include a mapping relation between the configuration signal and the target protocol, or a mapping relation between the configuration signal and the configuration instruction.
The present embodiment also provides an alternative implementation as to how the processing unit 10 obtains the configuration instructions, please refer to the following.
The processing unit 10 is provided with a register, and when the device (PCIe switching chip) is powered down, a user may modify pre-configured protocol information stored in the register, where the pre-configured protocol information includes a target protocol or a configuration instruction corresponding to the protocol matching unit 310. After the device is powered up, the processing unit 10 may read and execute the pre-configured protocol information stored in the registers.
Optionally, the processing unit 10 is further configured to determine a configuration instruction corresponding to each protocol matching unit 310 according to the preconfigured protocol information.
The preconfigured protocol information includes a target protocol corresponding to the protocol matching unit 310.
It should be noted that, in the solution of the present invention, different configuration instructions may be sent to the protocol matching unit 310 by modifying the configuration signal or the pre-configuration protocol information, so that the protocol matching unit 310 executes different target protocols, thereby achieving the purpose of docking multiple devices by one port.
On the basis of fig. 1, regarding the specific structure of each module in the PCIe switching chip, an alternative implementation manner is further provided in the embodiment of the present invention, please refer to fig. 2, fig. 2 is a second schematic structural diagram of the PCIe switching chip provided in the embodiment of the present invention.
As shown in fig. 2, the PCIe signal interface module 20 includes: PCIe signal Interface 210 (e.g., PCIe Interface), extensible host controller Interface 220 (e.g., xHCI Ctrl), USB HUB unit 230 (including USB3.0 HUB and USB2.0 HUB), and signal transmission unit 240.
The PCIe signal Interface 210 is also called PCIe Interface, the scalable host controller Interface 220 is also called xHCI Ctrl, and the english is eXtensible Host Controller Interface For Universal Serial Bus, and the USB hub unit 230 includes a USB3.0 hub 231 and a USB2.0 hub 232.
The PCIe signal interface 210 is connected to the expandable host controller interface 220 and the signal transmission unit 240, respectively, and the PCIe signal interface 210 is also used to connect to an upper computer.
The expandable host controller interface 220 is connected to the USB hub unit 230, and the USB hub unit 230 is connected to the signal transmission unit 240.
The signal transmission unit 240 is also connected to each protocol matching unit 310.
Optionally, the USB hub unit 230 includes a USB3.0 hub 231 and a USB2.0 hub 232.
The protocol matching unit 310 includes a serial ATA advanced host controller interface 311 (also known as AHCI Ctrl), a USB3.0 interface 312 (also known as USB3.0 PHY), and a USB2.0 interface 313 (also known as USB2.0 PHY), and the number of the protocol matching units 310 is M.
The signal transmission unit 240 includes 3M direct-connected signal lines.
Optionally, the PCIe signal interface 210 and the signal transmission unit 240 are provided with M transmission channels, each corresponding to one protocol matching unit 310, where M is the number of protocol matching units 310. The USB3.0 hub 231 and the signal transmission unit 240 are provided with M transmission channels, each corresponding to one protocol matching unit 310, respectively, where M is the number of protocol matching units 310. The USB2.0 hub 232 and the signal transmission unit 240 are provided with M transmission channels, each corresponding to one protocol matching unit 310, where M is the number of protocol matching units 310. I.e. one direct signal line corresponds to 1 transmission channel.
One end of the serial ATA advanced host controller interface 311 is connected to the PCIe signal interface 210 through a direct connection signal line, and the other end of the serial ATA advanced host controller interface 311 is connected to the device port 320.
One end of the USB3.0 interface 312 is connected to the USB3.0 hub 231 through a direct signal line, and the other end of the USB3.0 interface 312 is connected to the device port 320.
One end of the USB2.0 interface 313 is connected to the USB2.0 hub 232 through a direct signal line, and the other end of the USB2.0 interface 313 is connected to the device port 320.
The configuration instruction sent by the processing unit 10 is used to instruct one of the serial ATA advanced host controller interface 311, the USB3.0 interface 312 and the USB2.0 interface 313 to work as a target interface, where a communication protocol corresponding to the target interface is a target protocol.
In the scheme of the invention, the connection between the M protocol matching units 310 and the PCIe signal interface module 20 is realized through 3M direct connection signal lines, so that all the equipment ports can be ensured to run simultaneously.
In the scheme shown in fig. 2, the signal transmission unit 240 needs to set 3M direct connection signal lines, which can cause the number of direct connection signal lines to be too large under the condition that the number of the protocol matching units 310 is large, so that the wiring difficulty is greatly increased. In order to solve the problem, an alternative implementation manner is further provided in the embodiment of the present invention, please refer to fig. 3, and fig. 3 is a third schematic structural diagram of the PCIe switching chip provided in the embodiment of the present invention.
As shown in fig. 3, the USB hub unit 230 includes a USB3.0 hub 231 and a USB2.0 hub 232.
The protocol matching unit 310 includes a serial ATA advanced host controller interface 311 (also known as AHCI Ctrl), a USB3.0 interface 312 (also known as USB3.0 PHY), and a USB2.0 interface 313 (also known as USB2.0 PHY), and the number of the protocol matching units 310 is M.
The signal transmission unit 240 includes M first-order selectors 241, M direct signal lines, and a second-order selector 242.
Optionally, each protocol matching unit 310 corresponds to one first-order selector 241.
One end of the serial ATA advanced host controller interface 311 is connected to the first port of the corresponding first-order selector 241, and the other end of the serial ATA advanced host controller interface 311 is connected to the device port 320.
One end of the USB3.0 interface 312 is connected to the second port of the corresponding first-order selector 241, and the other end of the USB3.0 interface 312 is connected to the device port 320.
One end of the USB2.0 interface 313 is connected to the third port of the corresponding first-order selector 241, and the other end of the USB2.0 interface 313 is connected to the device port 320.
The fourth port of the first-order selector 241 is connected to the corresponding first port of the second-order selector 242 through a corresponding direct signal line.
Optionally, the second-order selector 242 includes M first ports, M second ports, M third ports, and M fourth ports, where each first port is connected to a corresponding second port, third port, and fourth port, respectively.
The second port line of the second-order selector 242 is connected to the PCIe signal interface 210, the third port line of the second-order selector 242 is connected to the USB3.0 hub 231, and the fourth port line of the second-order selector 242 is connected to the USB2.0 hub 232.
The configuration instruction sent by the processing unit 10 is used to instruct one of the serial ATA advanced host controller interface 311, the USB3.0 interface 312 and the USB2.0 interface 313 to work as a target interface, where a communication protocol corresponding to the target interface is a target protocol.
The processing unit 10 is further configured to send a first switching instruction to the first-order selector 241 when a configuration instruction is issued.
The first-stage selector 241 is configured to switch the internal on state when receiving the first switching instruction, so that a port (any one of the first port, the second port, or the third port of the first-stage selector 241) corresponding to the target interface is turned on with the fourth port of the first-stage selector 241.
Optionally, the second order selector 242 includes M first ports, M second ports, M third ports, and M fourth ports.
The processing unit 10 is further configured to send a second switching instruction to the second order selector 242 when a configuration instruction is issued.
The second-order selector 242 is configured to switch the internal on state when receiving the second switching instruction, so that the first port (the first port on the second-order selector 242) corresponding to the second switching instruction is connected to the corresponding upper port.
Wherein, the upper port is any one of the second port, the third port and the fourth port.
In the scheme provided in fig. 3 according to the embodiment of the present invention, the signal transmission unit 240 adopts a MUX (selector) +io Bus (direct connection signal line) scheme instead of the full direct connection scheme of the high-speed signals, the number of direct connection high-speed signals is reduced by >50%, and Die area and mask layer number can be effectively reduced, thereby reducing the cost of the chip.
The PCIe switching chip control method provided by the embodiment of the present invention may be applied to, but not limited to, PCIe switching chips shown in fig. 1-3, and referring to fig. 4, the PCIe switching chip control method includes: s101 and S301 are specifically described below.
S101, after the PCIe transfer chip is powered on, the processing unit sends a configuration instruction to the protocol matching unit.
S301, the protocol matching unit executes a target protocol corresponding to the configuration instruction according to the received configuration instruction.
The type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different.
It should be noted that, the PCIe switching chip control method provided by the embodiment may perform the functional use shown in the PCIe switching chip embodiment, so as to achieve a corresponding technical effect. For a brief description, reference is made to the corresponding parts of the above embodiments, where this embodiment is not mentioned.
The embodiment of the invention also provides electronic equipment, which comprises the PCIe switching chip.
In summary, the PCIe switching chip, the control method thereof and the electronic device provided by the embodiment of the present invention include: the device comprises a processing unit, a PCIe signal interface module and at least one group of device interface modules, wherein the device interface modules comprise a protocol matching unit and a device port; the protocol matching unit is respectively connected with the PCIe signal interface module, the corresponding equipment port and the processing unit; the PCIe signal interface module is also used for connecting an upper computer; the equipment port is also used for connecting with lower equipment; the processing unit is used for sending a configuration instruction to the protocol matching unit; the protocol matching unit is used for executing a target protocol corresponding to the configuration instruction according to the received configuration instruction; the type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different. In the same PCIe transfer chip, the communication protocols of the device ports can be configured through configuration instructions, lower devices of different protocols can be transferred through PCIe, the interface requirements of IT device diversification are met, and the area of the PCIe transfer chip is reduced as much as possible.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (9)
1. PCIe transit chip, characterized in that the PCIe transit chip comprises: the device comprises a processing unit, a PCIe signal interface module and at least one group of device interface modules, wherein the device interface modules comprise a protocol matching unit and a device port;
the protocol matching unit is respectively connected with the PCIe signal interface module, the corresponding equipment port and the processing unit;
the PCIe signal interface module is also used for connecting an upper computer;
the equipment port is also used for connecting with lower equipment;
the processing unit is used for sending a configuration instruction to the protocol matching unit;
the protocol matching unit is used for executing a target protocol corresponding to the configuration instruction according to the received configuration instruction;
the type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different;
the PCIe signal interface module includes: PCIe signal interface, expandable host controller interface, USB hub unit and signal transmission unit;
the PCIe signal interface is respectively connected with the extensible host controller interface and the signal transmission unit, and is also used for connecting the upper computer;
the expandable host controller interface is connected with the USB hub unit, and the USB hub unit is connected with the signal transmission unit;
the signal transmission unit is also connected with each protocol matching unit.
2. The PCIe switch chip of claim 1, wherein,
the USB hub unit comprises a USB3.0 hub and a USB2.0 hub;
the protocol matching unit comprises a serial ATA advanced host controller interface, a USB3.0 interface and a USB2.0 interface, and the number of the protocol matching units is M;
the signal transmission unit comprises 3M direct-connection signal lines;
one end of the serial ATA advanced host controller interface is connected with the PCIe signal interface through the direct connection signal line, and the other end of the serial ATA advanced host controller interface is connected with the device port;
one end of the USB3.0 interface is connected with the USB3.0 concentrator through the direct connection signal line, and the other end of the USB3.0 interface is connected with the equipment port;
one end of the USB2.0 interface is connected with the USB2.0 hub through the direct connection signal line, and the other end of the USB2.0 interface is connected with the equipment port;
the configuration instruction sent by the processing unit is used for indicating one of the serial ATA advanced host controller interface, the USB3.0 interface and the USB2.0 interface to work as a target interface, and a communication protocol corresponding to the target interface is the target protocol.
3. The PCIe switch chip of claim 1 wherein the USB hub unit comprises a USB3.0 hub and a USB2.0 hub;
the protocol matching unit comprises a serial ATA advanced host controller interface, a USB3.0 interface and a USB2.0 interface, and the number of the protocol matching units is M;
the signal transmission unit comprises M first-order selectors, M direct connection signal lines and a second-order selector;
one end of the serial ATA advanced host controller interface is connected with the first port of the corresponding first-order selector, and the other end of the serial ATA advanced host controller interface is connected with the device port;
one end of the USB3.0 interface is connected with a second port of the corresponding first-order selector, and the other end of the USB3.0 interface is connected with the equipment port;
one end of the USB2.0 interface is connected with a third port of the corresponding first-order selector, and the other end of the USB2.0 interface is connected with the equipment port;
the fourth port of the first-order selector is connected with the corresponding first port on the second-order selector through the corresponding direct-connection signal line;
a second port line of the second-order selector is connected with the PCIe signal interface, a third port line of the second-order selector is connected with the USB3.0 concentrator, and a fourth port line of the second-order selector is connected with the USB2.0 concentrator;
the configuration instruction sent by the processing unit is used for indicating one of the serial ATA advanced host controller interface, the USB3.0 interface and the USB2.0 interface to work as a target interface, and a communication protocol corresponding to the target interface is the target protocol;
the processing unit is further used for sending a first switching instruction to the first-order selector when the configuration instruction is sent;
and the first-stage selector is used for switching the internal conduction state when receiving the first switching instruction so as to conduct the port corresponding to the target interface with the fourth port of the first-stage selector.
4. The PCIe switch-chip of claim 3 wherein the second order selector comprises M first ports, M second ports, M third ports and M fourth ports, wherein each first port is connected to a corresponding second port, third port and fourth port, respectively.
5. The PCIe switch chip of claim 3 wherein the second order selector comprises M first ports, M second ports, M third ports, and M fourth ports;
the processing unit is further used for sending a second switching instruction to the second-order selector when the configuration instruction is sent;
the second-order selector is used for switching the internal conducting state when receiving the second switching instruction so that a first port corresponding to the second switching instruction is connected with a corresponding upper port;
wherein, the upper port is any one of the second port, the third port and the fourth port.
6. The PCIe switch chip of claim 1, wherein,
the processing unit is further configured to determine the configuration instruction corresponding to each protocol matching unit according to the signal received by the IO pin.
7. The PCIe switch chip of claim 1, wherein,
the processing unit is further used for determining the configuration instruction corresponding to each protocol matching unit according to pre-configuration protocol information;
the pre-configured protocol information comprises a target protocol corresponding to the protocol matching unit.
8. A PCIe switch chip control method applied to the PCIe switch chip of any one of claims 1 to 7, the method comprising:
after the PCIe transfer chip is powered on, the processing unit sends a configuration instruction to the protocol matching unit;
the protocol matching unit executes a target protocol corresponding to the configuration instruction according to the received configuration instruction;
the type of the configuration instruction is more than or equal to 2, and the target protocol corresponding to each configuration instruction is different.
9. An electronic device, comprising: the PCIe transit chip of any one of claims 1-7.
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