CN116701267A

CN116701267A - Performance test method and interface conversion device of PCIE interface of main board

Info

Publication number: CN116701267A
Application number: CN202310721375.6A
Authority: CN
Inventors: 马晴; 张晓晖
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-06-16
Filing date: 2023-06-16
Publication date: 2023-09-05

Abstract

The embodiment of the invention provides a method for testing PCIE interface performance and an interface switching device, wherein the device comprises the following steps: the first PCIE interface comprises a first conductive contact, a first PCIE interface and a management module; the first conductive contact is used for being inserted into a second PCIE interface on a main board of the server to be tested, and the first conductive contact and the second PCIE interface are both in a first link specification; the first PCIE interface is used for bearing a second conductive contact of the external device, and the second conductive contact and the first PCIE interface are both in a second link specification; the management module is used for acquiring transmission performance parameters of the external equipment; the first conductive contact consists of a plurality of contacts, and the first PCIE interface comprises a plurality of pins; the single contact has transmission link mapping relation with at least one pin and is connected with at least one pin through a wire. The interface switching device switches the interfaces with different link specifications so as to solve the technical defect that the external equipment with the existing interface specifications cannot be connected into the PCIE interface of the main board to test the interface performance.

Description

Performance test method and interface conversion device of PCIE interface of main board

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a performance testing method and an interface conversion device for a PCIE interface of a motherboard, an electronic device, and a computer readable storage medium.

Background

The high-speed serial expansion bus standard (PCI-E, peripheral Component Interconnect Express) interface is a hardware expansion interface with mature application and is often applied to various consumer-level host computers and commercial server mainboards. By virtue of the technical advantage of high transmission rate, the system can be compatible with various hardware devices such as a sound acquisition card, a network card, a graphics processing card and the like according to the use requirement, and the transmission rate and the transmission standard are continuously improved along with the development of the technology.

To ensure the stability of hardware manufacturing, performance testing is required for the high-speed serial expansion bus standard interface on the computer motherboard. In the existing method, after the external equipment matched with the interface speed and bandwidth is selected for expansion connection, the transmission speed and bandwidth of the interface are read from the computer end and the external equipment end respectively and compared.

However, in the prior art, for the high-speed serial expansion bus standard interface, different transmission performances correspond to interface specifications (x 4/×8/×16) with various lengths. For interfaces supporting the GEN 5 transmission protocol and having the form specification of x 8, the implementation scheme of comparing and measuring the interface performance by lacking external equipment matched with the interface specification cannot detect the interface performance.

Disclosure of Invention

The embodiment of the invention provides a performance test method, an interface conversion device, electronic equipment and a computer readable storage medium of a main board PCIE interface, which are used for solving the problem that the main board interface aiming at a novel transmission protocol in the prior art cannot be subjected to compatibility test through the existing external equipment.

In a first aspect, an embodiment of the present invention provides an interface conversion apparatus, including: the first PCIE comprises a first conductive contact, a first PCIE interface and a management module;

the first conductive contact is used for being inserted into a second PCIE interface on a main board of the server to be tested, and the first conductive contact and the second PCIE interface are both in a first link specification;

the first PCIE interface is configured to carry a second conductive contact of an external device, where the second conductive contact and the first PCIE interface are both of a second link specification;

the management module is configured to obtain a transmission performance parameter of the external device when the second conductive contact is inserted into the first PCIE interface;

the first conductive contact consists of a plurality of contacts, and the first PCIE interface comprises a plurality of pins; a transmission link mapping relation exists between the single contact and at least one pin, and the single contact is connected with at least one pin through a wire.

In a second aspect, an embodiment of the present invention provides a method for detecting performance of a PCIE interface of a motherboard, where the method includes:

establishing hardware connection between external equipment and an interface conversion device through the first PCIE interface and the second conductive contact;

acquiring transmission performance parameters of the external equipment;

establishing hardware connection between a server mainboard to be tested and an interface conversion device through the first conductive contact and the second PCIE interface;

acquiring interface transmission parameters generated by the server to be tested in response to a preset detection instruction sent by test equipment;

comparing the interface transmission parameters with the transmission performance parameters to obtain a comparison result;

and sending a test report to the test equipment according to the comparison result.

In a third aspect, an embodiment of the present invention provides an electronic device, including: a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of the second aspect.

In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the method of the second aspect.

In the embodiment of the invention, a conversion device is provided, which comprises a first conductive contact, a first PCIE interface and a management module; the first conductive contact is used for being inserted into a second PCIE interface on a main board of the server to be tested, and the first conductive contact and the second PCIE interface are both in a first link specification; the first PCIE interface is used for bearing a second conductive contact of the external device, and the second conductive contact and the first PCIE interface are both in a second link specification; the management module is used for acquiring transmission performance parameters of the external equipment under the condition that the second conductive contact is inserted into the first PCIE interface; the first conductive contact consists of a plurality of contacts, and the first PCIE interface comprises a plurality of pins; the single contact has transmission link mapping relation with at least one pin and is connected with at least one pin through a wire. The interface switching device switches the interfaces with different link specifications so as to solve the technical defect that the external equipment with the existing interface specifications cannot be connected into the PCIE interface of the main board to test the interface performance.

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

fig. 1 is a schematic structural diagram of an interface conversion device according to an embodiment of the present invention;

fig. 2 is a hardware specification display diagram of an interface conversion device and a server motherboard according to an embodiment of the present invention;

fig. 3 is an interface-pin mapping relationship diagram of the interface conversion device according to the embodiment of the present invention;

fig. 4 is a flowchart of implementation steps of a method for detecting performance of a PCIE interface of a motherboard according to an embodiment of the present invention;

fig. 5 is a component connection relationship and execution logic diagram of a method for detecting performance of a PCIE interface of a motherboard according to an embodiment of the present invention;

FIG. 6 is a functional component relationship diagram of an electronic device according to an embodiment of the present invention;

fig. 7 is a functional component relationship diagram of another electronic device according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an interface conversion device according to an embodiment of the present invention. As shown in fig. 1, the interface conversion device includes a first PCIE interface for carrying an external device and a first conductive contact for accessing a slot of a motherboard, and the motherboard of the server to be tested includes a second PCIE interface for carrying the first conductive contact. The first conductive contact and the second PCIE interface are both of a first link specification, and the second conductive contact and the first PCIE interface are both of a second link specification. The interface expansion device further comprises an independent management module, and the independent management module is used for acquiring transmission performance parameters of the interface of the external equipment under the condition that the external equipment is inserted into the first PCIE interface through the second conductive contact.

PClE is full duplex communication, i.e. allowing transmission and reception of data at the same time and simultaneously. A link is driven by two low-voltage check signals, and a pair of transmitting and receiving signals exist at two sides of the link. In order to realize quick data transmission, a coding mode is used for realizing recovery and training of a data clock by a link contained in the PClE link. Once initialized, each transmission bandwidth is transmitted at that rate, and the PCle 5.0 protocol supports a single channel transmission rate of 32 GT/s. 32GT/s means that a single transmission bandwidth can transmit 32G bits per second, and not all data transmissions are valid because of the different coding schemes. One PClE link supports up to x32 bandwidth transmission, typically in the form of x1, x2, x4, x8, x12, x16, and x 32. Multiple lanes can increase the transmission rate of the link.

Devices with different specifications (physical dimensions) based on PCIE interfaces and PCIE conductive contacts can be downward compatible and externally connected, for example, external devices with the specification of PCIEX 8 conductive contacts can be connected into slots with the specification of PCIEX 8 or slots with the specification of PCIEX 16, but cannot be upward compatible. The number of channels actually connected to the interface slot may also be less than the number supported by the physical slot size. For example, a slot of specification x16 may run x1, ×2, ×4, ×8, ×16 cards, providing only 4 channels when running a x4 card. The specification can be read as "x 16" (x 4 mode) ", or" x16 @ x4 "(where the" size @ x speed "symbol is also a common system representation). The advantage is that such a slot can accommodate a wider range of PCIE cards without requiring motherboard hardware to support full transmission rates.

By means of the interface switching device provided by the embodiment of the invention, the external device of the high-specification conductive contact can be connected into the interface slot with the low specification to complete data exchange under the condition that the original interface device is kept unchanged. Because the external device supporting the PCIE 5.0 transmission protocol in the present stage has conductive contacts based on PCIE x 16 specification and cannot be connected into the mainboard slot based on PCIE x 8 specification, the problem of incompatibility is well solved by the conversion device of the embodiment of the invention.

Referring to fig. 2, fig. 2 is a connection relationship diagram between an interface conversion device and a server motherboard according to an embodiment of the present invention. As shown in fig. 2, the interface conversion device includes a gold finger (conductive contact) for inserting into a PCIE slot of a server motherboard, and a PCIE slot and an integrated management module for carrying an external device.

Specifically, in the embodiment of the present invention, the interface conversion device is configured to convert an interface slot with a specification of pcie×8 on a server motherboard into a slot with a specification of pcie×16, so as to access an external device with a golden finger with a specification of pcie×16. Referring to the server motherboard depicted in fig. 2, the baseboard includes a south bridge chipset (PCH, platform Controller Hub), a baseboard management controller (BMC, baseboard management controller), a universal serial bus interface (USB, universal Serial Bus), and two central processing units (CPU, central Processing Unit), CPU 0 and CPU 1.

Wherein, is based on one chip in the computer motherboard chipset architecture. Because the interactive band block designed by the CPU is limited, under the condition that the expansion hardware on the main board is more, all hardware cannot directly interact with the CPU, so that the south bridge is designed for processing low-speed signals and is connected with the central processing unit through the north bridge so as to share the data processing pressure of the CPU. The BMC is a basic management unit on a server main board, and can perform firmware upgrade, check machine equipment and other operations on the machine in a state that the machine is not started. The two CPUs in FIG. 2 are connected via a 24-channel hyper-path interconnect (UPI, ultra Path Interconnect) bus, the UPI being a low-latency coherent interconnect for scalable multiprocessor systems with shared address space. It uses a directory-based home snoop coherency protocol with transmission speeds up to 10.4GT/s, and typically supports processors with two or three UPI links.

The three PCIE lanes directly connected to the CPU0 exist in a physical form in a PCIE slot form, and include two pcie×16 slots with a link width of 16 and a pcie×8 slot with a link width of 8. The same direct connection with CPU1 includes two pcie×16 slots with a link width of 16, and one pcie×8 slot with a link width of 8, and one of them is an interface slot based on an open server architecture (OCP, open Compute Project). The OCP specifically provides an extensible server architecture, which can meet different server requirements. It supports a variety of network interfaces including ethernet, wireless bandwidth technology (InfiniBand), fibre channel (fibric channel), etc. In addition, the main board is connected with the interface conversion device through a USB interface wire so that the main board can send monitoring information to the management module on the conversion device. It should be noted that, the OCP interface of the server motherboard is not compatible with the devices carried by the PCIE interface.

Further, as shown in fig. 2, a slot with an interface specification of pcie×8, which is directly connected to the CPU0, is used to carry a golden finger plug-in unit of the interface conversion device provided by the embodiment of the present invention, so as to implement hardware connection. The PCIE slot of the server motherboard is specifically a transmission interface based on PCIE 5.0 transmission protocol standard (GEN 5). It should be noted that, with the development of computer technology, versions of PCIE transmission protocols are also being iteratively upgraded, and currently, data throughput that can be carried by an interface theory based on PCIE 5.0 transmission protocols and having 8 link channels may reach 32 gigabits per second (GT/s). The CPU0 and the south bridge chip group are connected through a direct media interface (DMI, direct Media Interface), the DMI is a bus developed by Intel corporation for connecting the south bridge and the north bridge of the main board, the previous Hub-Link bus is replaced, a point-to-point connection mode is adopted, and the bus is developed based on PCIE. The south bridge chipset is connected with the baseboard management controller through a system management BUS (SM BUS, system Management Bus) and realizes data interaction, and is particularly used for controlling external devices on a main board and collecting corresponding information through the baseboard management controller by the south bridge.

Referring to fig. 3, an interface-pin mapping relationship diagram of an interface conversion device according to an embodiment of the present invention is shown. As shown in fig. 3, the first conductive contact on the interface conversion device and the slot of the second PCIE interface of the motherboard have the same hardware specification, which is the pcie×8 specification.

Specifically, in fig. 3, 98 PIN PINs are shared by pcie×8 channel ends on the motherboard, and the physical form total length of the interface size is 56mm, and the interface is divided into two sides AB. The A surface is a link close to the PCIE bus and is used as an interaction end for carrying out data communication with external equipment, and the B surface is a link close to the CPU of the main board and is used as a data transmission end for carrying out data transmission with the main board. The 98 PIN PINs on the two sides are separated into 2 sections according to the slot notch key, and the specific form of the conductive contact and PCIE interface in fig. 1 can be referred to specifically. The front half end of the key is a power supply PIN, 22 PIN PINs from A1 to A11 and B1 to B11 are used as power supply links of PCIE slots, the rear half section of the key is a data transmission channel, and 76 PIN PINs from A12 to A49 and B12 to B49 are used as data transmission links. In addition, the first PCIE interface specification at the other end on the interface converter is pcie×16, the total length of the link channels in the slots is 89mm, the slot notch key is equally divided into a power supply link and a data transmission link, as with pcie×8 channels, 22 PIN are power supply PINs of pcie×16 slots, and the remaining 142 PIN are data transmission channels.

Furthermore, in the interface conversion device provided by the embodiment of the present invention, a connection link and a mapping relationship are provided between a contact point of the conductive contact sheet with pcie×8 specification and a pin of the socket with pcie×16 specification. Specifically, the contact and the pin are connected by a wire in an end-to-end direct connection mode. The PIN of the power supply link of the pci ex8 and the power supply link of the pci ex16 are kept unchanged, and a power supply mode of 1 to 1 is adopted. The data link of the PCIEx8 slot adopts a transmission mode of 1 to 2, and uses a data transmission cable of 1 to 2 to bind, for example: the data sources of the PCIEx16 channel B12 and B13 ports come from the PCIEx8 channel A12 port. By adopting the mode for data transmission and conversion, when 49 PIN PINs of the B surface of the PCIEx8 slot position are inserted into the PCIEx8 slot position on the mainboard for communication with the mainboard, after receiving signals from the CPU of the mainboard, the data are transmitted to A12 to A49 corresponding to the A surface through an internal link, the data of A12 in the PCIEx8 channel are transmitted to B12 and B13 in the PCIEx16 channel through A1-to-2 data transmission line, the data of A13 in the PCIEx8 channel are transmitted to B15 and B16 in the PCIEx16 channel, and the A14 is transmitted to B18 and B19, so that the data in the PCIEx8 channel are pushed until all the data are converted to the PCIEx16 channel.

It should be noted that, not all the contacts and pins used for data transmission at two ends have a connection relationship, at least part of the data transmission contacts are empty contacts, and at least part of the data transmission pins are empty pins. For example: the B14 pin in the PCIEx16 slot is suspended, so that a data string is prevented, and the effectiveness of data transmission is ensured.

In summary, the interface conversion device provided in the embodiment of the present invention includes a first conductive contact, a first PCIE interface, and a management module; the first conductive contact is used for being inserted into a second PCIE interface on a main board of the server to be tested, and the first conductive contact and the second PCIE interface are both in a first link specification; the first PCIE interface is used for bearing a second conductive contact of the external device, and the second conductive contact and the first PCIE interface are both in a second link specification; the management module is used for acquiring transmission performance parameters of the external equipment under the condition that the second conductive contact is inserted into the first PCIE interface; the first conductive contact consists of a plurality of contacts, and the first PCIE interface comprises a plurality of pins; the single contact has transmission link mapping relation with at least one pin and is connected with at least one pin through a wire. The interface switching device switches the interfaces with different link specifications so as to solve the technical defect that the external equipment with the existing interface specifications cannot be connected into the PCIE interface of the main board to test the interface performance.

Referring to fig. 4, a flowchart of implementation steps of a method for detecting performance of a PCIE interface of a motherboard according to an embodiment of the present invention is shown and applied to the interface conversion device and the server motherboard. As shown in fig. 4, the steps of the method include:

step 101: and establishing hardware connection between the external equipment and the interface conversion device through the first PCIE interface and the second conductive contact.

In the practical application process, the external equipment for detection is connected with the interface conversion device provided by the embodiment of the invention. The hardware connection can be completed by clamping a second wire contact (golden finger) on the external device with the PCIE slot on the interface conversion device. Here, it may be understood that the conductive contact is a "male" of the PCIE hardware connection device, and the slot of the PCIE interface is a "female". The types of external devices accessed here include: the link specification is pcie×16 network card, hard disk array card, host channel adapter card (HCA), etc., which is not limited herein.

The embodiment of the invention provides a performance detection method for a PCIE interface of a main board, which aims at testing the interface transmission rate and the transmission bandwidth of PCIE slots on the main board of a server. The method comprises the steps of selecting an external device matched with the PCIE interface speed and bandwidth of a main board, establishing hardware connection with a conductive contact through the interface, then respectively traversing and acquiring the transmission speeds and bandwidths of all PCIE slots on the main board and the data throughput speed and transmission bandwidths of the external device in a main board server system through a preset detection instruction, and comparing the results of the two to determine whether the PCIE slots on the current main board reach theoretical bandwidths and speeds.

Because the device integration level of the server main board is higher, the manufacturing cost is relatively high, and the PCIE slot is used as an important expansion interface on the main board at the present stage, so that various devices can be flexibly connected to the PCIE slot according to the use requirement. The method has important significance for reliable testing means of the interface performance of the slot of the server main board, and for hardware development, production and manufacture, sales management, post maintenance and the like of the server main board.

Step 102: and acquiring transmission performance parameters of the external equipment.

With continued reference to fig. 2, the interface conversion device provided by the embodiment of the invention further includes a group (visualization) management module, and the module can actively read the slot information of the interface where the device is located and store the slot information in the storage unit inside the interface when the device is not connected, and meanwhile, the acquired related information can be displayed through the display module attached to the interface conversion device, so that the interface conversion device is convenient for a tester to check.

It should be noted that, the interface conversion device is connected with the server motherboard through a USB interface and a data line, so as to realize the power supply support of the motherboard to the operation of the management module, and the subsequent server actively sends the acquired motherboard slot information to the management module.

Step 103: and establishing hardware connection between the server main board to be tested and the interface conversion device through the first conductive contact and the second PCIE interface.

Similarly, referring to step 101, the hardware connection between the server motherboard to be tested and the interface conversion device can be completed by inserting the first wire point contact (golden finger) of the interface conversion device into the second PCIE interface slot on the server motherboard.

In the embodiment of the invention, the PCIE slot on the mainboard to be tested and the golden finger of the interface conversion device are both in PCIE x 8 link specification, and can be completely inserted into the PCIE slot on the mainboard, the connector port has foolproof design, no structural interference, smooth assembly and repeated plugging and unplugging for a plurality of times, and the slot position of the adapter has no risks of loosening, deformation, collision and the like.

Step 104: and acquiring interface transmission parameters generated by the server to be tested in response to a preset detection instruction sent by test equipment.

Optionally, the prediction detection instruction includes: the method comprises the steps of presetting detection instructions based on a server operating system, presetting detection instructions based on a basic input output system and presetting detection instructions based on a mainboard management controller.

Referring to fig. 5, a component connection relationship and an execution logic diagram of a method for detecting performance of a PCIE interface of a motherboard according to an embodiment of the present invention are shown. As shown in fig. 5, the server to be tested establishes a physical connection relationship with the conductive contact on the interface conversion device through the PCIE interface slot on the motherboard, and in addition, the motherboard of the server to be tested and the interface conversion device realize data transmission and power transmission through the USB cable. The interface slot of the interface conversion device is physically connected with PCIE external equipment, and reads the related data of the external equipment and temporarily stores the related data into a storage module arranged in the management module. After the server to be tested responds to the detection instruction sent by the test equipment and sequentially generates detection results generated based on the BMC/BIOS/OS environment, the detection results are sent to the management module of the interface conversion device for data comparison. Based on the comparison result, uploading the passed test result to the test equipment side where the tester is located under the condition that the comparison result is consistent, and uploading the system log to the test equipment side where the tester is located under the condition that the comparison result is inconsistent.

Specifically, after the steps 101 to 103 are performed, all interfaces and components in the solution are connected, and relevant steps of testing the performance of the motherboard interface can be started after the slot position conversion adaptation of the external device for testing and the motherboard slot is completed.

In the embodiment of the invention, a tester sends a preset detection instruction to a server to be tested through independent test equipment (a computer), and then the server responds to the detection instruction to start actively reading the data transmission bandwidth and transmission rate of PCIE slot equipment accessed on a main board, and uploads the information to a management module of an interface conversion device through USB connection.

It is particularly emphasized that, in order to eliminate the fluctuation of the measurement result possibly caused by the individual difference among the elements as much as possible, the test link in the embodiment of the present invention reads the performance data of the external device of the motherboard through multiple modes under different operating systems, including: a Basic Input Output System (BIOS) based on a motherboard, a conventional Operating System (OS) based on a server running, and a mode based on a baseboard management controller BMC.

For the server operating system OS, in the embodiment of the present invention, a Linux system is taken as an example. Under the system, the lspci instruction is adopted to traverse and acquire the speed and the bandwidth of PCIE slots on all mainboards in the scheme, and currently, based on PCIE 5.0 transmission protocol, the bandwidth of data throughput which can be borne can reach 32 gigabits per second (GT/s), and the transmission speed is about 31.5GB/s under the condition that the link specification is a multiplied by 8 channel. After the acquisition is finished, the server can send the acquired interface performance parameters to a management module thereof through the USB connection of the server main board and the interface conversion device so as to enable the interface conversion device to perform next comparison operation.

Likewise, for the BIOS environment. The BIOS itself is a set of programs solidified on a Read-Only Memory (ROM) chip on the main board in the computer, which stores the most important basic input and output programs of the computer, the self-checking programs after starting up and the system self-starting programs, and can Read and write specific information set by the system from the CMOS. Its main function is to provide the lowest, most direct hardware setup and control for the computer. In addition, the BIOS provides some system parameters to the operating system. The system hardware changes are hidden by the BIOS and the program uses the BIOS functions rather than directly controlling the hardware. Modern operating systems ignore the abstraction layer provided by the BIOS and directly control the hardware components. Thus, rather than following upper level code commands like lspci, the BIOS itself is used to view various hardware specifications associated on the motherboard, and therefore is more bottom and direct for viewing specification information of the motherboard PCIE interface, than under the Linx operating system.

A Baseboard Management Controller (BMC) is a specialized server processor that uses sensors to monitor a computer. The sensors of the BMC are used to measure internal physical variables such as: temperature, humidity, supply voltage, fan speed, communication parameters and operating system functions, if any of these variables are outside the specified limits, they notify the administrator, who may take corrective action using remote control. The monitoring device may be power cycled or restarted when necessary, so that a single administrator may remotely control numerous servers and other devices simultaneously, saving the overall cost of the network, and ensuring reliability.

In the method provided by the embodiment of the invention, the performance parameters of the server main board interface are respectively acquired in 3 different modes aiming at the test link, and are compared with the acquired transmission performance parameters of the external equipment, so that the experimental errors caused by various unreliability can be eliminated, and the test result is more accurate.

Step 105: and comparing the interface transmission parameters with the transmission performance parameters to obtain a comparison result.

Because the PCIE slot of the current motherboard supports PCIE 5.0, the physical slot is an x 8 channel, and the external devices conforming to the transmission performance specification are all based on the interface specification of the x 16 channel, conversion adaptation is required by the interface conversion device provided by the embodiment of the present invention. After switching, the data transmission bandwidth and the transmission performance of the external device are respectively measured from two ends, and whether the data link specification of the physical slot of the main board meets the standard can be determined after comparison.

In an alternative embodiment, step 105 may further include:

sub-step 1051: and under the condition that the value of the transmission performance parameter is equal to the value of the interface transmission parameter, determining that the comparison result is passing.

And 104, aiming at the transmission performance parameters of the external equipment measured by the interface switching device end and the interface transmission parameters of the external equipment in the main board slot measured by the server main board end, after the server uploads the test parameters to the interface switching device, the device can call out the slot position information of the external equipment temporarily stored in the internal storage module and respectively compares the slot position information with the data under the BMC, BIOS, OS system. When the information of the external device temporarily stored in the internal storage module is consistent with the data under the BMC/BIOS/OS system, the comparison result can be considered to pass.

It should be noted that, even in the same test environment, the transmission performance parameters of the slot interface may not be completely consistent, and the transmission rate based on the PCIE 5.0 protocol is only a result based on the theoretical performance. In the actual test result, the transmission parameters and the transmission performance parameters of the interface will have some errors. For example, at a theoretical transmission rate of 31.5 GB/s= 32256MB/s, the unit is converted to megabytes per second, and then more resultant bits can be used as the error capacity. In this scheme, the comparison result can be considered to be passing when the difference between the actual measurement result and the theoretical transmission rate is smaller than the preset error threshold (for example, within 1000 MB/s). For example, according to a test result, the transmission rate of the interface of the main board is 31000MB/s, the transmission performance parameter rate of the external device is 32000MB/s, which is measured by the interface conversion device, and the comparison result can be considered to be passing. The specific allowable error threshold may be set by a tester according to actual situations, and the embodiment is not limited herein.

Optionally, the substep 1051 further includes:

sub-step 10511: and under the condition that the comparison result is passed, displaying a test passing prompt.

According to the above-mentioned sub-step 1051, in case the comparison result is passed, a prompt, for example, a "PASS" word, is displayed by the display unit in the interface conversion device, so as to prompt the tester that the current data comparison result has passed, and the transmission rate of the slot interface of the tested server motherboard meets the standard.

Under the condition that the comparison result is passed, the fact that the current server main board interface designed based on the PCIE 5.0 protocol accords with the data transmission rate standard is shown, the actual requirements of products manufactured by adopting the existing production flow are met for manufacturing the main board, and the fact that a large number of products are scrapped due to potential manufacturing flaws in the subsequent production process is effectively avoided, so that the method has positive significance in saving the material cost of the production and manufacturing links.

Substep 1052: and under the condition that the value of the transmission performance parameter is not equal to the value of the interface transmission parameter, determining that the comparison result is not passing.

Corresponding to the substep 1051, if the error between the interface transmission parameter and the transmission performance parameter in the measurement result is too large, for example, a test result is a test result, the measured interface transmission rate of the motherboard is 28000MB/s, and the measured transmission performance parameter rate of the external device by the interface conversion device is 32200MB/s. The comparison result is considered to be failed at this time.

Optionally, the substep 1052 further includes:

sub-step 10521: and displaying a test failure prompt under the condition that the comparison result is not passed.

According to the above-mentioned content in sub-step 1052, in case the comparison result is passed, a prompt such as "FAIL" is displayed by a display unit in the interface conversion device, so as to prompt the tester that the current data comparison result is not passed, and the transmission rate of the slot interface of the tested server motherboard does not meet the standard.

Under the condition that the comparison result is not passed, the fact that the current server main board interface designed based on the PCIE 5.0 protocol does not accord with the data transmission rate standard is indicated, so that the interface cannot bear the calibrated data volume in the subsequent use, the operation efficiency of the server can be seriously influenced, and under certain extreme high-load scenes, serious actual losses can be caused in succession due to information interaction delay caused by the fact that the transmission rate does not reach the standard.

Step 106: and sending a test report to the test equipment according to the comparison result.

With continued reference to fig. 5, after the comparison and judgment are completed, the interface conversion device will send a corresponding test report to the test equipment where the tester is located according to the comparison result, so as to inform the tester that the test is completed and the post-hoc data analysis can be performed.

In an alternative embodiment, step 106 may further include:

sub-step 1061: and if the comparison result is that the external equipment passes, sending the values of the equipment transmission bandwidth and the equipment transmission rate of the external equipment and the values of the data transmission bandwidth and the data transmission rate of the second PCIE interface to the test equipment.

And under the condition that the comparison result is passed, the management module of the conversion device can test the current test result, wherein the test result comprises the values of the device transmission bandwidth and the device transmission rate of the external device in the current test, and the values of the data transmission bandwidth and the data transmission rate of the second PCIE interface of the main board.

Sub-step 1062: if the comparison result is that the test result does not pass, a system test log is sent to the test equipment so as to enable a tester to conduct test failure analysis; the system test log is used for recording operation records when the server to be tested executes a preset detection instruction.

In contrast, if the test result is not passed, the management module of the conversion device uploads the log of the system execution log of the server running the detection instruction to the test equipment where the tester is located in the test process, and the tester can select to accept log according to the prompt to perform test failure analysis. The system execution log records the detailed operation record of the system in the process of running the preset detection instruction by the server, and the detailed operation record comprises an interface corresponding to which PCIE channel is detected in a polling mode and a detailed detection process. Through the system execution log, a tester can clearly know the whole process of executing the test by the system in response to the detection instruction so as to check against the failed result and determine the specific reason of the failure of the transmission.

In summary, in the method for detecting performance of the PCIE interface of the motherboard according to the embodiment of the present invention, by using the interface conversion device provided by the present invention, hardware connection between the external device and the interface conversion device is established through the first PCIE interface and the second conductive contact, and transmission performance parameters of the external device are obtained; then establishing hardware connection between the main board of the server to be tested and the interface conversion device through the first conductive contact and the second PCIE interface of the main board; after the interface transmission parameters generated by the server to be tested in response to the preset detection instruction sent by the test equipment are obtained, the transmission parameters of the mainboard interface are compared with the transmission performance parameters of the external equipment, a comparison result is obtained, and whether the PCIE interface slot transmission performance of the server mainboard meets the standard is determined according to the comparison result. The technical defect that the interface performance detection cannot be carried out due to the fact that an external device which is matched with the interface specification is lacked in the prior art to realize the implementation scheme of comparing and measuring the interface performance is overcome.

Fig. 6 is a block diagram of an electronic device 600, according to an example embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.

Referring to fig. 6, an electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power component 606, a multimedia component 608, an audio component 610, an input/output (I/O) interface 612, a sensor component 614, and a communication component 616.

The processing component 602 generally controls overall operation of the electronic device 600, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 602 can include one or more modules that facilitate interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate interaction between the multimedia component 608 and the processing component 602.

The memory 604 is used to store various types of data to support operations at the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phonebook data, messages, pictures, multimedia, and so forth. The memory 604 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 606 provides power to the various components of the electronic device 600. The power supply components 606 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 600.

The multimedia component 608 includes a screen between the electronic device 600 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense demarcations of touch or sliding actions, but also detect durations and pressures associated with the touch or sliding operations. In some embodiments, the multimedia component 608 includes a front camera and/or a rear camera. When the electronic device 600 is in an operational mode, such as a shooting mode or a multimedia mode, the front-facing camera and/or the rear-facing camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 610 is for outputting and/or inputting audio signals. For example, the audio component 610 includes a Microphone (MIC) for receiving external audio signals when the electronic device 600 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, audio component 610 further includes a speaker for outputting audio signals.

The I/O interface 612 provides an interface between the processing component 602 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 614 includes one or more sensors for providing status assessment of various aspects of the electronic device 600. For example, the sensor assembly 614 may detect an on/off state of the electronic device 600, a relative positioning of the components, such as a display and keypad of the electronic device 600, the sensor assembly 614 may also detect a change in position of the electronic device 600 or a component of the electronic device 600, the presence or absence of a user's contact with the electronic device 600, an orientation or acceleration/deceleration of the electronic device 600, and a change in temperature of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 616 is utilized to facilitate communication between the electronic device 600 and other devices, either in a wired or wireless manner. The electronic device 600 may access a wireless network based on a communication standard, such as WiFi, an operator network (e.g., 2G, 3G, 4G, or 5G), or a combination thereof. In one exemplary embodiment, the communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 600 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for implementing a method for detecting performance of a motherboard PCIE interface provided by an embodiment of the present invention.

In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 604, including instructions executable by processor 620 of electronic device 600 to perform the above-described method. For example, the non-transitory storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

Fig. 7 is a block diagram of an electronic device 700, according to an example embodiment. For example, the electronic device 700 may be provided as a server. Referring to fig. 7, electronic device 700 includes a processing component 722 that further includes one or more processors and memory resources represented by memory 732 for storing instructions, such as application programs, executable by processing component 722. The application programs stored in memory 732 may include one or more modules that each correspond to a set of instructions. In addition, the processing component 722 is configured to execute instructions to execute the performance detection method of the motherboard PCIE interface provided by the embodiment of the present invention.

The electronic device 700 may also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input output (I/O) interface 758. The electronic device 700 may operate based on an operating system stored in memory 732, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

It is to be understood that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the invention is limited only by the appended claims.

Claims

1. An interface conversion device, characterized in that the interface conversion device comprises: the first PCIE comprises a first conductive contact, a first PCIE interface and a management module;

2. The apparatus of claim 1, wherein the interface conversion apparatus further comprises: a universal serial bus interface, an internal memory unit;

the universal serial bus interface is used for the server to be tested to send interface transmission parameters to the management module; the interface transmission parameters are parameters which are generated by the server to be tested and used for representing the transmission performance of the second PCIE interface in response to a preset detection instruction sent by test equipment;

the internal storage unit is used for storing the acquired transmission performance parameters and interface transmission parameters.

3. The apparatus of claim 2, wherein the predictive detection instruction comprises: the method comprises the steps of presetting detection instructions based on a server operating system, presetting detection instructions based on a basic input output system and presetting detection instructions based on a mainboard management controller.

4. The apparatus of claim 1, wherein the first link specification comprises 8 link transmission lanes and the second link specification comprises 16 link transmission lanes;

the contact of the first conductive contact piece comprises: a first number of power supply contacts and a first number of data transfer contacts; pins in the first PCIE interface include: a first number of power pins and a second number of data transfer pins; the first number of data transmission contacts jointly form 8 link transmission channels, the second number of data transmission pins jointly form 16 link transmission channels, and the first number is smaller than half of the second number;

The single contact has transmission link mapping relation with at least one pin, and is connected with at least one pin through a wire, comprising:

the power supply contacts are connected with the power supply pins in a one-to-one correspondence manner;

the single data transmission contact is correspondingly connected with two adjacent data transmission pins; at least part of the data transmission contacts are empty contacts, and at least part of the data transmission pins are empty pins.

5. The apparatus of claim 1, wherein the management module is further configured to:

under the condition that the transmission performance parameter and the interface transmission parameter are obtained, comparing the value of the transmission performance parameter with the value of the interface transmission parameter to obtain a comparison result;

6. The apparatus of claim 5, wherein the means for comparing the value of the transmission performance parameter with the value of the interface transmission parameter to obtain a comparison result comprises:

determining that the comparison result is passing under the condition that the value of the transmission performance parameter is equal to the value of the interface transmission parameter;

And under the condition that the value of the transmission performance parameter is not equal to the value of the interface transmission parameter, determining that the comparison result is not passing.

7. The apparatus of claim 5, wherein the transmission performance parameters comprise: the device transmission bandwidth and the device transmission rate of the external device; the interface transmission parameters include: the data transmission bandwidth and the data transmission rate of the second PCIE interface;

the management module sends a test report to the test equipment according to the comparison result, and the test report comprises:

if the comparison result is that the external equipment passes, sending the values of the equipment transmission bandwidth and the equipment transmission rate of the external equipment and the values of the data transmission bandwidth and the data transmission rate of the second PCIE interface to the test equipment;

if the comparison result is that the test result does not pass, a system test log is sent to the test equipment so as to enable a tester to conduct test failure analysis; the system test log is used for recording operation records when the server to be tested executes a preset detection instruction.

8. The apparatus of claim 4, wherein the interface conversion apparatus further comprises: a display unit;

The display unit is used for displaying a test passing prompt when the comparison result is passing; displaying a test failure prompt when the comparison result is not passed;

the display unit is also used for displaying the transmission performance parameters of the external equipment under the condition that the external equipment is connected with the interface conversion device.

9. A method for detecting performance of a PCIE interface of a motherboard, which is applied to the apparatus of any one of claims 1 to 8, and is characterized in that the method includes:

acquiring transmission performance parameters of the external equipment;

10. An electronic device, comprising: a processor;

A memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of claim 9.

11. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of claim 9.