CN213581897U

CN213581897U - Novel display control calculation module

Info

Publication number: CN213581897U
Application number: CN202022203034.4U
Authority: CN
Inventors: 徐代阳; 裴芳; 闫青云; 姚海望
Original assignee: Changsha HCC Hiden Technology Co Ltd
Current assignee: Changsha HCC Hiden Technology Co Ltd
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2021-06-29
Anticipated expiration: 2030-09-30

Abstract

The utility model discloses a novel display control calculation module, wherein a memory particle chip, a display chip and a PCIE bus extension chip are all connected with a CPU; the system starting chip and the BMC chip are connected with the CPU through a complex programmable logic device; the display chip outputs 4 paths of HDMI digital signals to the CPEX connector; the CPU outputs 2 sets of PCIE x8 interfaces to the CPEX connector; the PCIE bus expansion chip converts 1 group of PCIE x8 interfaces of the CPU into 10 paths of PCIE x4 interfaces, wherein the PCIE x8 interfaces are respectively expanded to an Ethernet interface through a network chip, expanded to a USB interface through a USB chip and expanded to an SATA interface through an SATA chip, and are connected with a part of PCIE x4 interfaces to a CPEX connector, meanwhile, a part of USB interfaces are connected to a front panel interface and a BMC chip, and a part of SATA interfaces are connected to an MSATA connector and are used for an on-board electronic disk. The utility model discloses a novel display control calculation module integrated level is high, compact structure, and the extended capability is good.

Description

Novel display control calculation module

Technical Field

The utility model relates to a novel display control calculation module.

Background

The display control computing module is also called CPEX computing module and is a module applied to a display control computer system.

The existing display control computing module has a complex structure and a few expansion interfaces, is not beneficial to simplification and miniaturization of the module and has poor expansion performance.

In addition, the core computers used by key users are all embedded computers mainly based on applications such as high-performance computation and data storage. For a long time, most of embedded software and hardware are designed, produced and manufactured in the United states, and based on the requirement of national information security construction, the core technical monopoly of foreign manufacturers on high-end storage products is broken. The display control computing module faces the practical requirements of the high-performance computing field, and the developed high-performance display control computer product adopts a Feiteng processor chip with the independent intellectual property right of China, and has the advantages of high speed, high reliability, low power consumption and the like. Therefore, under the wave of the country which strongly promotes the localization, it is necessary to rapidly develop the embedded type based on the domestic software and hardware platform to ensure the security of the national data information system.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a novel display control calculation module is provided, this novel display control calculation module integrated level is high, compact structure, and the extended capability is good.

In order to achieve the technical purpose, the utility model adopts the following technical scheme:

a novel display control calculation module comprises a CPU, a memory particle chip, a display chip, a PCIE bus expansion chip, a complex programmable logic device, a system starting chip, a BMC chip, a network chip, an SATA chip, a USB chip, a front panel interface and a CPEX connector;

the memory particle chip, the display chip and the PCIE bus expansion chip are all connected with the CPU;

the system starting chip and the BMC chip are connected with the CPU through a complex programmable logic device;

the display chip outputs 4 paths of HDMI digital signals to the CPEX connector;

the CPU outputs 2 groups of PCIE x8 interfaces to be connected to the CPEX connector;

the BMC chip outputs 1 VGA and 1 gigabit network to the front panel interface and outputs 1 IPMB to the CPEX connector;

the input port of the PCIE bus expansion chip is connected to 1 set of PCIE x8 interfaces of the CPU, and outputs 10 paths of PCIE x4 as output interfaces, where:

the 2 PCIE x4 interfaces are expanded into 6 gigabit Ethernet interfaces through a network chip and connected to the CPEX connector;

the 3 PCIE x4 interfaces are degraded into 3 PCIE x1 interfaces, 12 USB2.0 interfaces are expanded through the USB chip, wherein 2 USB2.0 interfaces are connected to the front panel interface, 1 USB2.0 interface is connected with the BMC chip, 7 USB2.0 interfaces are directly connected to the CPEX connector, and 1 USB2.0 interface is connected with the audio conversion chip and then output to the CPEX connector;

the 1 path of PCIE x4 interface is degraded into 1 path of PCIE x1 interface, 4 paths of SATA interfaces are expanded through an SATA chip, wherein the 1 path of SATA interface is connected to an MSATA connector, the 1 path of SATA interface is used for an onboard electronic disk, and the 2 path of SATA interface is connected to a CPEX connector;

the 2-way PCIE x4 interface is directly connected to the CPEX connector;

the 2-way PCIE x4 interface is downgraded to a 2-way PCIE x2 interface, which connects to the CPEX connector.

Further, the PCIE bus expansion chip employs a PLX PEX8750 integrated device.

Further, the display chip is an JM7200 type integrated device, and the CPU is connected to the display chip through 1 set of PCIE x 8.

Furthermore, the CPU adopts a FT2000/4 type integrated device.

Furthermore, the BMC chip is connected with the complex programmable logic device through a UART interface, and further performs data transmission with the CPU.

Further, the complex programmable logic device, the output LPC interface and the GPIO interface are connected to the CPEX connector.

Further, the memory particle chip adopts an MT40A1G8SA-062EIT type integrated device.

Furthermore, the network chip adopts an Intel I350 type integrated device with the bandwidth of 1 Gb.

Further, the SATA chip adopts a Marvell 88SE9215 type integrated device.

Further, the system starting chip adopts an S25FS128 type integrated device, the BMC chip is AST2400 of ASPEED, and the USB chip adopts a UPD720201 type integrated device.

Advantageous effects

The utility model adopts a CPU to output a plurality of sets of PCIE x8 interfaces, wherein 1 set of PCIE x8 interfaces can convert and output HDMI digital signals through a display chip; another 1 set of PCIE x8 is used for the PCIE bus expansion chip to perform expansion to obtain a plurality of PCIE x4 interfaces, and then the plurality of PCIE x4 interfaces are used to perform conversion respectively to obtain a plurality of SATA interfaces, USB interfaces, audio interfaces, and network interfaces, and the plurality of SATA interfaces, USB interfaces, audio interfaces, and network interfaces are used to communicate with the local computer by connecting the CPEX connectors and the like; another 2 sets of PCIE x8 interfaces are directly connected to the CPEX connector for communication with other PCIE x8 interface type devices. Therefore, the utility model discloses a novel display control calculation module integrated level is high, compact structure, and the expansibility is good.

Drawings

Fig. 1 is a block diagram of an overall structure of a novel display control computing module according to an embodiment of the present invention.

Detailed Description

The following is a detailed description of the embodiments of the present invention, and the present embodiment uses the technical solution of the present invention as a basis for developing, and gives detailed implementation and specific operation process, and it is right to further explain the technical solution of the present invention.

The utility model provides a novel display control calculation module, which comprises a CPU, a memory particle chip, a display chip, a PCIE bus expansion chip, a complex programmable logic device, a system starting chip, a BMC chip, a network chip, a SATA chip, a USB chip, a front panel interface and a CPEX connector;

wherein, the CPU adopts a FT2000/4 type integrated device; the memory particle chip adopts an MT40A1G8SA-062EIT type integrated device; the display chip adopts a Jingjia micro JM7200 type integrated device; the PCIE bus expansion chip adopts a PLX PEX8750 type integrated device; the BIOS of the system starting chip adopts an S25FS128 type integrated device; the BMC chip is AST2400 of ASPEED; the network chip adopts an Intel I350 type integrated device with the bandwidth of 1 Gb; the SATA chip adopts a Marvell 88SE9215 type integrated device; the USB chip adopts a UPD720201 type integrated device.

The CPU is connected with the display chip through 1 group of PCIE x8, is connected with the PCIE bus expansion chip through 1 group of PCIE x8, and is connected with the CPEX connector through 2 groups of PCIE x8 directly and is also connected with the memory particle chip.

The system starting chip and the BMC chip are connected with the CPU through a complex programmable logic device; wherein, the communication interface between the complicated programmable logic device and the CPU comprises: any one or more of GPIO, I2C, UART, LPC, SPI, etc.; the complex programmable logic device is communicated with the BMC chip through a UART interface; in addition, the complex programmable logic device also comprises a GPIO interface, a TTL debugging interface and an RS232 interface, and is connected to the CPEX connector through the GPIO interface and connected to the front panel interface through the TTL debugging interface.

The BMC chip outputs 1 VGA and 1 gigabit network to the front panel interface, and outputs 1 IPMB (intelligent platform management bus) to the CPEX connector;

the display chip outputs 4 paths of 4K HDMI digital signals to the CPEX connector;

the 2-way PCIE x4 interface is directly connected to the CPEX connector;

The above embodiments are preferred embodiments of the present application, and those skilled in the art can make various changes or modifications without departing from the general concept of the present application, and such changes or modifications should fall within the scope of the claims of the present application.

Claims

1. A novel display control calculation module is characterized by comprising a CPU, a memory particle chip, a display chip, a PCIE bus expansion chip, a complex programmable logic device, a system starting chip, a BMC chip, a network chip, an SATA chip, a USB chip, a front panel interface and a CPEX connector;

the display chip outputs 4 paths of HDMI digital signals to the CPEX connector;

the 2-way PCIE x4 interface is directly connected to the CPEX connector;

2. The novel display control computing module of claim 1, wherein the PCIE bus expansion chip employs a PLX PEX8750 type integrated device.

3. The novel display control computing module of claim 1, wherein the display chip is an JM7200 integrated device, and the CPU is connected to the display chip via 1 PCIE x8 set.

4. The novel display control computing module of claim 1, wherein the CPU is implemented as a FT2000/4 integrated device.

5. The novel display control computation module of claim 1, wherein the BMC chip is connected to the complex programmable logic device through a UART interface, and further performs data transmission with the CPU.

6. The novel display control computation module of claim 1, wherein the complex programmable logic device, the output LPC interface and the GPIO interface are connected to a CPEX connector.

7. The novel display control computing module of claim 1, wherein the memory particle chip is implemented as an MT40A1G8SA-062EIT type integrated device.

8. The novel display control computing module of claim 1, wherein the network chip is an Intel I350 integrated device with a bandwidth of 1 Gb.

9. The novel display control computing module of claim 1, wherein the SATA chip is implemented as a Marvell 88SE9215 type integrated device.

10. The novel display control computing module of claim 1, wherein the system boot chip is an S25FS128 integrated device, the BMC chip is an asped 2400, and the USB chip is a UPD720201 integrated device.