CN211149356U

CN211149356U - Shenwei 1621CPU ICH-free 2 suite server mainboard

Info

Publication number: CN211149356U
Application number: CN201922368197.5U
Authority: CN
Inventors: 姚鸿
Original assignee: Avic Hongdian Beijing Information Technology Co ltd
Current assignee: Avic Hongdian Beijing Information Technology Co ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-07-31
Anticipated expiration: 2029-12-26

Abstract

The utility model discloses a Shenwei 1621CPU does not have ICH2 set chip server mainboard, including CPU, BIOS chip, memory slot, mainboard time sequence control chip, PCIE bus expansion chip, BMC management chip, network chip, SATA chip, SAS chip, USB chip, PCIE slot. The BIOS chip, the memory slot, the BMC management chip and the PCIE bus expansion chip are directly connected with the CPU. The CPU supports two sets of PCI-E X8 signals: one group of PCI-E X8 is used as the input of the SAS expansion chip and provides 2 groups of Mini-SAS X4 interfaces; the other set of PCI-E X8 signals is connected with the input end of the PCI-E bus expansion chip, and the PCIE bus expansion chip provides 1-path PCIE3.0X16, 3-path PCI-E3.0X8, 2-path PCI-EX4 and 4-path PCI-E X1 as output for expanding various low-speed and high-speed data ports. The utility model discloses an adopt domestic Shenwei SW1621CPU to carry on domestic deep operation system, have that the processing speed is fast, the interface extension is nimble, the sexual valence relative altitude, characteristics such as security level height.

Description

Shenwei 1621CPU ICH-free 2 suite server mainboard

Technical Field

The utility model relates to a server mainboard technical field, more specifically the utility model relates to a shen wei 1621CPU does not have ICH2 nest of plates server mainboard that says so.

Background

In China, after a Chinese-style event, the localization problem of the information industry is gradually brought to the schedule, and as the importance of the information industry, the autonomous controllability of the server industry is very important. In recent years, the country has increased the investment in the domestic autonomous controllable information industry, and each large server manufacturer has also successively introduced a batch of domestic autonomous controllable servers with the Shenwei SW1621CPU as the core, but most of these server manufacturers adopt the ICH2 suite design scheme, which not only has high price, but also has great performance constraints.

Therefore, how to provide a low-cost, excellent-performance and ICH-free 1621CPU server motherboard 2 set of cards that can meet the application requirements of key industries such as national defense, finance, telecommunication, energy and the like is a problem that needs to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model provides a shen wei 1621CPU does not have ICH2 nest plate server mainboard, it uses SW1621 treater to carry on PCIE SWITCH as the core and does not have ICH2 nest plate scheme, aims at replacing Intel well low-end server, realizes information security's autonomic controllable, provides powerful support for constructing national information security.

In order to achieve the above object, the utility model provides a following technical scheme:

a Shenwei 1621CPU ICH-free 2 set server mainboard comprises a CPU, a BIOS chip, a memory slot, a time sequence control chip, a PCIE bus expansion chip, a BMC management chip, an SAS chip, a network chip, an SATA chip, a USB chip and a PCIE slot;

the BIOS chip, the memory slot, the BMC management chip, the SAS chip and the PCIE bus expansion chip are directly connected with the CPU, and the BMC management chip is connected with the CPU through an I2C bus and used for monitoring the physical health state of the CPU and transmitting parameters;

1 group of X8 PCIE signals of the CPU are connected with the input end of the SAS expansion chip, 2 paths of Mini-SAS X4 signals are output to the outside through the SAS switching chip, and 8 paths of SATA3.0 interfaces can be provided to the outside through the SAS signal connector at most;

the 1 group of X8 PCIE signals of the CPU are connected with the input end of a PCI-E bus expansion chip, the PCI-E bus expansion chip takes 1 path of PCI-E X16, 3 paths of PCI-E X8, 2 paths of PCI-E X4 and 5 paths of PCI-E X1 as output and is used for the expansion of high and low speed bus interfaces, wherein:

1) the 1 path of X16 PCIE3.0 signal is connected to a PCIE X16 physical expansion slot, and the 3 paths of X8 PCIE3.0 signal are respectively connected to 3 PCIE X8 physical expansion slots, so as to expand an external high-performance expansion card;

2) the 1-path X4 PCIE3.0 signal is connected to the NVME slot and is used for expanding the high-performance data storage medium;

3) the 1 path of X4 PCIE3.0 signal is connected to the SATA expansion chip, and 3 paths of SATA3.0 interfaces and 1 path of msata3.0 interfaces are expanded and used for expanding and connecting a server operating system disk and a data disk;

4) the 1 path of X4 PCIE3.0 signal is connected to a network control chip, 4 paths of gigabit Ethernet interfaces are expanded, and a data exchange communication channel between a server and peripheral equipment is provided;

5) 2X 1 PCIE3.0 signals are respectively connected to the USB switching chip, and 6 USB3.0 and 2 USB2.0 interfaces are expanded for connecting peripheral equipment such as a keyboard, a mouse and a USB flash disk;

6) the 1-path X1 PCIE2.0 signal is connected to a BMC management chip, and provides a 1-path VGA display interface, a 1-path management interface and a 1-path management serial port for realizing remote health management and KVM-OVER-IP functions of the server;

7) and the 1 path of X1 PCIE2.0 signal is connected to the Mini-PCIE slot and is used for expanding the server trusted module.

Preferably, in the ICH-free 2 suite server motherboard of the shenwei 1621CPU, the BIOS memory chip is AT25F512B, the timing control chip is L CMX02, the PCIE expansion chip is PEX8780, the BMC management chip is AST2400, the SAS chip is SAS2008, the network chip is intel 350, the SATA chip is Marvell88SE9215, and the USB chip is UPD 720201.

Preferably, in the above-mentioned schwann 1621CPU ICH-free 2 deck server motherboard, the CPU adopts a schwann SW1621 integrated device.

Known through foretell technical scheme, compare with prior art, the beneficial effects of the utility model reside in that: the utility model discloses use SW1621 treater as the core to carry on PCIE SWITCH does not have ICH2 set of piece scheme and aim at replacing the middle and low-end server of Intel, realize the autonomic controllable of information security, provide powerful support for constructing national information security; the cable has the characteristics of low price, excellent performance and capability of meeting the application requirements of key industries such as national defense, finance, telecommunication, energy and the like.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a general structural frame diagram of the present invention.

Fig. 2 is a schematic structural diagram of the server motherboard according to the present invention.

Fig. 3 is an enlarged view of a portion a of the server motherboard according to the present invention.

Fig. 4 is an enlarged view of a B portion of the server motherboard according to the present invention.

Fig. 5 is an enlarged view of the C portion of the server motherboard according to the present invention.

The attached drawing of fig. 6 is the enlarged view of the D part of the server motherboard of the present invention.

Fig. 7 is an enlarged view of the E portion of the server motherboard according to the present invention.

Fig. 8 is an enlarged view of the F portion of the server motherboard according to the present invention.

Fig. 9 is an enlarged view of the H portion of the server motherboard according to the present invention.

Fig. 10 is an enlarged view of an I portion of a server motherboard according to the present invention.

Fig. 11 is an enlarged view of the G portion of the server motherboard according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Please refer to fig. 1-11, for the present invention discloses a novel Shenwei 1621CPU ICH-free 2 suite server motherboard, which includes a CPU, a BIOS chip, a memory slot, a power timing control chip, a PCIE bus expansion chip, a BMC management chip, an SAS chip, a network chip, an SATA chip, a USB chip, and a PCIE slot.

1. The mainboard takes Shenwei SW1621 as a core, completes power supply and time sequence control of the mainboard through a power supply time sequence control chip L CMX02, loads BIOS from a BIOS chip AT25F512B through an SPI data bus, and finally completes the starting of the mainboard, wherein the Shenwei SW1621CPU supports an eight-channel DDR3 memory controller, a single channel supports 32GB to the maximum extent, the memory accounts for 256GB, and the speed can reach 1600MHz AT most;

2. the Shenwei SW1621 supports 2 sets X8 PCIE 3.0: 1 set of X8 PCIE3.0 bus is expanded to 1 path of PCI-E X16, 3 paths of PCI-E X8, 2 paths of PCI-E X4 and 5 paths of PCI-E X1 as output through a PCIE bus expansion chip PEX8780 and is used for expansion of a low-speed bus interface; the 1 group of X8 PCIE3.0 outputs 2 paths of X4 Mini-SAS interfaces through the SAS switching chip, and 8 paths of SAS/SATA interfaces can be provided to the outside at most.

3. One PCIE bus expansion chip PEX8780 expands 1 lane of PCI-E X16, 3 lanes of PCI-E X8, 2 lanes of

PCIE3.0X

4, and 5 lanes of PCIE 2.0X 1 buses: wherein, the 1 path of X16 PCIE3.0 signal is connected to the PCIE X16 physical expansion slot, and the 3 paths of X8 PCIE3.0 signal are respectively connected to the 3 PCIE X8 physical expansion slots; the 1 path of PCI-E3.0X 4 signal is expanded into 4 paths of SATA3.0 signals through a SATA conversion chip Marvell88SE9215, and the 1 path of PCI-E3.0X 4 signal is externally led out through an NVME slot; 5-way PCI-E2.0X 1 signal: 1 path of PCIE 2.0X 1 signal is expanded out of 4 paths of gigabit Ethernet interfaces through a network control chip intel 35; 1 path of PCI-E2.0X 1 signal is expanded to the outside by a BMC management chip AST2400 to form a 1 path of VGA display interface, a 1 path of management interface and a 1 path of management serial port; 2 paths of PCIE 2.0X 1 signals are respectively expanded out of 6 paths of USB3.0 interfaces through 2 USB conversion chips UPD 720201; the 1-way PCI-E2.0X 1 signal is connected to the Mini-PCIE slot.

4. 1 path of X1 PCIE3.0 bus output by the PCIE bus expansion chip PEX8780 is expanded out of 4 paths of SATA3.0 interfaces through an SATA chip Marvell88SE9215, wherein the 1 path of SATA interface is connected with an MSATA connector, and the 3 paths of SATA are connected with the SATA connector;

5. 1 path of X1 PCIE2.0 signal output by the PCIE bus extension chip PEX8780 is extended out of 4 paths of gigabit Ethernet interfaces through 1 network chip intel 350 and is connected to a server mainboard RJ45 connector;

6. 1 path of X1 PCIE2.0 signal output by the PCIE bus extension chip PEX8780 expands 2 paths of USB2.0 and 2 paths of USB3.0 signals through 1 USB conversion chip UPD 720201: 1 path of the 2 paths of USB3.0 signals is connected to a Mini-PCIE slot for expanding a safe and credible module; the 1 path of USB2.0 is connected to the BMC chip and is used for realizing a KVM-OVER-IP function; the 2-channel USB3.0 is directly led out through the mainboard connector.

7. The SPI data bus of the SW1621CPU is connected to the BIOS chip through the level conversion chip for carrying the BIOS starting program.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A Shenwei 1621CPU ICH-free 2 set server mainboard comprises a CPU, a BIOS chip, a memory slot, a time sequence control chip, a PCIE bus expansion chip, a BMC management chip, an SAS chip, a network chip, an SATA chip, a USB chip and a PCIE slot;

5) 2X 1 PCIE3.0 signals are respectively connected to the USB switching chip, and 6 USB3.0 and 2 USB2.0 interfaces are expanded for connecting a keyboard, a mouse and a USB flash disk;

2. The ICH-free 2 suite server motherboard of claim 1621CPU, according to claim 1, wherein the BIOS memory chip is AT25F512B, the timing control chip is L CMX02, the PCIE expansion chip is PEX8780, the BMC management chip is 2400 AST, the SAS chip is SAS2008, the network chip is intel 350, the SATA chip is Marvell88SE9215, and the USB chip is UPD 720201.

3. The Shenwei 1621CPU ICH-free 2 chip set server motherboard as claimed in claim 1 or 2, wherein the CPU is integrated with Shenwei SW 1621.