CN211427336U

CN211427336U - Embedded VPX calculation module

Info

Publication number: CN211427336U
Application number: CN201922267932.3U
Authority: CN
Inventors: 王元圆; 卢山; 吴思璇; 杨山礼; 李俊
Original assignee: Changsha HCC Hiden Technology Co Ltd
Current assignee: Changsha HCC Hiden Technology Co Ltd
Priority date: 2019-12-17
Filing date: 2019-12-17
Publication date: 2020-09-04
Anticipated expiration: 2029-12-17

Abstract

The utility model discloses an embedded VPX calculation module, including CPU, memory granule chip, system start chip, PCIE bus extension chip, SRIO chip, display chip, BMC chip, 40Gb network chip, 1Gb network chip, SATA chip, USB chip and VPX connector; the memory particle chip, the display chip, the PCIE bus expansion chip, the 40Gb network chip, the 1Gb network chip and the system starting chip are all connected with the CPU; the SRIO chip, the BMC chip, the SATA chip and the USB chip are all connected with the PCIE bus expansion chip. The multi-interface high-speed data bus interface comprises multiple high-speed data buses such as a PCIE3.0 interface, a 40Gb network interface and an SRIO interface, and can realize the interface redundancy function; the system management system is provided with a BMC chip, can realize the system management of the computing module through the BMC chip, and can carry out remote control management on the computing module through a network; high density, multi-functional interface makes the calculation module can be applied to multiple occasion.

Description

Embedded VPX calculation module

Technical Field

The utility model relates to a computer technology field especially relates to an embedded VPX calculation module.

Background

The existing embedded computing module applied to the VPX system has a complex structure and a few expansion interfaces, is not beneficial to simplification and miniaturization of the module and has poor expansion performance.

In addition, the core computers used by key users are all embedded computers mainly based on applications such as high-performance computation and data storage. For a long time, most of embedded software and hardware are designed and manufactured in the United states, and the embedded software and hardware are mastered by other people, so that the embedded software and hardware based on the domestic software and hardware platform is rapidly developed vigorously to ensure the safety of a national data information system under the wave of the country greatly promoting the localization.

Therefore, it is necessary to design an embedded VPX calculation module for use in a VPX system.

SUMMERY OF THE UTILITY MODEL

The utility model provides an embedded VPX calculation module to solve among the prior art embedded calculation module integrated level not high and the poor problem of expansibility.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

an embedded VPX computing module comprises a CPU, a memory particle chip, a system starting chip, a PCIE bus expansion chip, an SRIO chip, a display chip, a BMC chip, a 40Gb network chip, a 1Gb network chip, an SATA chip, a USB chip and a VPX connector;

the memory particle chip, the display chip, the PCIE bus expansion chip, the 40Gb network chip, the 1Gb network chip and the system starting chip are all connected with the CPU;

the display chip outputs 1 path of VGA analog signal and 2 paths of DVI-D digital signals to the VPX connector;

the 40Gb network chip outputs 2 paths of 40Gb network signals to the VPX connector;

the 1Gb network chip outputs 4 paths of Seders network signals to the VPX connector;

the BMC chip outputs 1 path of VGA and 1 path of gigabit network to the front panel interface and outputs 2 paths of IPMB to the VPX connector;

1 group of 8 paths of PCIE3.0 signals of the CPU are connected with an input port of the PCIE bus expansion chip, and the PCIE bus expansion chip is provided with 10 paths of X4PCIE2.0 interfaces serving as an output port; wherein:

the 2-path X4PCIE2.0 interface is expanded out of a 2-path x4SRIO interface through the SRIO chip and is connected with the VPX connector;

the 2-path X4PCIE2.0 interface is expanded into 8-path USB2.0 interface through the USB chip, wherein the 2-path USB2.0 interface is placed on the front panel of the board card; the 1 path of USB2.0 interface is connected with a BMC chip, the 1 path of USB2.0 interface is connected with a serial port chip, and an RS232 signal output by the serial port chip is connected with the VPX connector; the 4-path USB2.0 interface is connected with the VPX connector;

the 1 path of X4PCIE2.0 interface is expanded to 4 paths of SATA interfaces through the SATA chip, wherein the 1 path of SATA interface is connected with an MSATA connector, and the 3 path of SATA interface is connected with the VPX connector;

the 1-path X4PCIE2.0 interface is accessed to the BMC chip and is used for data transmission between the BMC chip and the CPU;

the 4-way X4PCIE2.0 interface accesses the VPX connector.

Further, the 4-way X4PCIE2.0 interface is accessed into the VPX connector, and the 4-way X4PCIE2.0 interface can be combined into 2-way X8PCIE2.0 or 1-way X16PCIE2.0. Different data transmission bandwidths, the wider the bandwidth, the more data is transmitted, and the faster the speed is.

Furthermore, the TTL debugging interface of the CPU is connected to the front panel through the CPLD, and the UART serial port of the CPU outputs an RS422 signal to the VPX connector through the CPLD.

Further, the memory particle chip is an SCB13H8G802BF-13KI type integrated device, the PCIE bus expansion chip is a PLX PEX8750 type integrated device, the display chip is an AMD E8860 type integrated device, the 1Gb network chip is an Intel I350 type integrated device, the 40Gb network chip is an Intel XL710 type integrated device, the SRIO chip is an IDT TSI721 type integrated device, the SATA chip is a Marvell 88SE9215 type integrated device, the system start chip is an S25FS128 type integrated device, the USB chip is an UPD720201 type integrated device, the serial port chip is a PL2303 type integrated device, and the BMC chip is an ASPEED 2400 type integrated device.

Further, the CPU is a Feiteng 1500A-16 type integrated device.

Advantageous effects

The utility model provides an embedded VPX computing module, which is provided with a plurality of high-speed data buses, such as a PCIE3.0 interface, a 40Gb network interface and an SRIO interface; the multiple high-speed data interfaces are all multi-path, and the interface redundancy function can be realized; the system management system is provided with a BMC chip, can realize the system management of the computing module through the BMC chip, and can carry out remote control management on the computing module through a network; high density, multi-functional interface, standardization for the calculation module can be applied to multiple occasion.

Drawings

Fig. 1 is a block diagram illustrating an overall structure of an embedded VPX computing module according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments.

As shown in fig. 1, an embodiment of the present invention provides an embedded VPX computing module, which includes a CPU, a memory particle chip, a system start chip, a PCIE bus expansion chip, an SRIO chip, a display chip, a BMC chip, a 40Gb network chip, a 1Gb network chip, an SATA chip, a USB chip, and a VPX connector;

the display chip outputs 1 path of VGA analog signal and 2 paths of DVI-D digital signals to the VPX connector, is used for outputting a system display interface and is externally connected with a VGA or DVI-D display;

the 40Gb network chip is used for high-speed transmission of system data, the 1Gb network chip is used for transmission of system control signals, and the two networks are separated, so that the efficiency of system control and data transmission can be increased.

the 4-way X4PCIE2.0 interface accesses the VPX connector, wherein the 4-way X4PCIE2.0 interface can be combined into 2-way X8PCIE2.0 or 1-way X16PCIE2.0. Different data transmission bandwidths, the wider the bandwidth, the more data is transmitted, and the faster the speed is.

It should be understood that, because of the compatibility of the X4PCIE2.0 interface, the X4PCIE2.0 interface can also be used as the X1PCIE2.0 interface, so as to better accommodate chips that only accept pcie x1 signals.

The TTL debugging interface of the CPU is connected to the front panel through the CPLD, and the UART serial port of the CPU outputs an RS422 signal to the VPX connector through the CPLD.

In specific implementation, the CPU is preferably a soar 1500A-16 type integrated device, the memory particle chip is an SCB13H8G802BF-13KI type integrated device, the PCIE bus expansion chip is a PLX PEX8750 type integrated device, the display chip is an AMD E8860 type integrated device, the 1Gb network chip is an Intel I350 type integrated device, the 40Gb network chip is an Intel XL710 type integrated device, the SRIO chip is an IDT TSI721 type integrated device, the SATA chip is a Marvell 88SE9215 type integrated device, the system start chip is an S25FS128 type integrated device, the USB chip is a UPD720201 type integrated device, the serial port chip is a PL2303 type integrated device, and the BMC chip is a peased AST 2400.

The system starts the work of the Feiteng 1500A-16CPU by a system starting chip S25FS 128; the Feiteng 1500A-16CPU has a four-channel DDR3 memory controller and 32GB memory with board-mounted board, and the speed can reach 1600MHz at most.

1 group of X8PCIE3.0 buses from the Feiteng 1500A-16CPU is expanded out of a 10-way X4PCIE2.0 bus through a PCIE bus expansion chip PEX 8750; 1 group X8PCIE3.0 expanded by the Feiteng 1500A-16CPU outputs 1 path VGA analog signal and 2 paths DVI-D digital signal through the display chip E8860; 1 group X4PCIE3.0 from the Feiteng 1500A-16CPU expands 4 routes of Serdes signals through a 1Gb network chip; the 1 group X8PCIE3.0 from the Feiteng 1500A-16CPU extends 2 paths of 40Gb network signals through a 40Gb network chip. The Feiteng 1500A-16CPU UART serial port and TTL debug interface are changed from special 1.8V level to universal 3.3V level through level conversion, the TTL debug interface is connected to the front panel, the UART serial port is output to the VPX connector,

the core of the embedded VPX computing module provided by the embodiment is a Feiteng 1500A-16CPU, the Feiteng 1500A-16CPU is a high-performance universal 64-bit CPU independently developed by the national defense science and technology university, is designed for a latest series of processors Cortex-A57 based on an ARMv8 architecture, and is a sixteen-core sixteen-thread; the system is mainly oriented to the application fields of notebooks, servers, high-end embedded systems and the like, and is provided with various high-speed data buses, such as a PCIE3.0 interface, a 40Gb network interface and an SRIO interface; the multiple high-speed data interfaces are all multi-path, and the interface redundancy function can be realized; the system management system is provided with a BMC chip, can realize the system management of the computing module through the BMC chip, and can carry out remote control management on the computing module through a network; high density, multi-functional interface, standardization for the calculation module can be applied to multiple occasion.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An embedded VPX computing module is characterized by comprising a CPU, a memory particle chip, a system starting chip, a PCIE bus expansion chip, an SRIO chip, a display chip, a BMC chip, a 40Gb network chip, a 1Gb network chip, an SATA chip, a USB chip and a VPX connector;

1 group of 8PCIE3.0 signals of the CPU are connected with an input port of the PCIE bus expansion chip, and the PCIE bus expansion chip is provided with 10X 4PCIE2.0 interfaces as an output port; wherein:

a 2-path X4PCIE2.0 interface is expanded out of a 2-path X4SRIO interface through the SRIO chip and is connected with the VPX connector;

the 2-path X4PCIE2.0 interface expands 8-path USB2.0 interfaces through the USB chip, wherein the 2-path USB2.0 interface is arranged on the front panel of the board card; the 1 path of USB2.0 interface is connected with a BMC chip, the 1 path of USB2.0 interface is connected with a serial port chip, and an RS232 signal output by the serial port chip is connected with the VPX connector; the 4-path USB2.0 interface is connected with the VPX connector;

the 1 path of X4PCIE2.0 interface expands 4 paths of SATA interfaces through the SATA chip, wherein the 1 path of SATA interface is connected with an MSATA connector, and the 3 paths of SATA interfaces are connected with the VPX connector;

the 1-path X4PCIE2.0 interface is accessed to the BMC chip;

and a 4-path X4PCIE2.0 interface is accessed to the VPX connector.

2. The embedded VPX computation module of claim 1, wherein the 4 way X4PCIE2.0 interface is accessed into the VPX connector, and the 4 way X4PCIE2.0 interface can be combined into 2 way X8PCIE2.0 or 1 way X16PCIE 2.0.

3. The embedded VPX computation module of claim 1, wherein the TTL debug interface of the CPU is connected to the front panel via a CPLD, and the UART serial port of the CPU outputs an RS422 signal to the VPX connector via the CPLD.

4. The embedded VPX computing module of claim 1, wherein the memory granule chip is an SCB13H8G802BF-13KI type integrated device, the PCIE bus expansion chip is a PLX PEX8750 type integrated device, the display chip is an AMD E8860 type integrated device, the 1Gb network chip is an Intel I350 type integrated device, the 40Gb network chip is an Intel XL710 type integrated device, the SRIO chip is an IDT TSI721 type integrated device, the SATA chip is a Marvell 88SE9215 type integrated device, the system start-up chip is an S25FS128 type integrated device, the USB chip is a UPD720201 type integrated device, the serial port chip is a PL2303 type integrated device, and the BMC chip is an ASPEED 2400 type integrated device.

5. The embedded VPX computation module of any of claims 1 to 4, wherein the CPU is a FT 1500A-16 type integrated device.