CN105068955B - A kind of local bus architecture and data interactive method - Google Patents
A kind of local bus architecture and data interactive method Download PDFInfo
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- CN105068955B CN105068955B CN201510427270.5A CN201510427270A CN105068955B CN 105068955 B CN105068955 B CN 105068955B CN 201510427270 A CN201510427270 A CN 201510427270A CN 105068955 B CN105068955 B CN 105068955B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
Abstract
The present invention provides a kind of local bus architecture of data reliable communicating between more FPGA for nuclear power I＆C system, including main FPGA, two and two or more are from FPGA, the main FPGA and from passing through full duplex parallel bus transfers data between FPGA, characterized in that, the main FPGA and FPGA from FPGA for embedded black box IP kernel；The main FPGA includes the data processing module provided with CRC (CRC), bus data transceiver controller, I/O modules, includes the data processing module provided with CRC from FPGA, receives data dual port RAM, send data dual port RAM, I/O modules.Using the bus structures and method of the present invention, solve the problems, such as the data reliable communication between more FPGA, also customized bus mode, bus control unit is voluntarily write, and black box IP particular requirement can not be used by meeting nuclear power industry.
Description
Technical field
The invention belongs to industrial DCS (distributed AC servo system) system information processing technology field, it is related to for nuclear power instrument control system
The local bus architecture and data interactive method of data reliable communicating between more FPGA of system.
Background technology
Design based on now more popular digitlization I＆C system DCS is all based on microprocessor realization, in order to more
Good reaches the diverse designs for being different from above DCS, solves the problems such as common cause fault, some DCS start to adopt in the world at present
Designed with the DCS that FPGA is processor is based entirely on；
But in order to reach the independence of board internal module function, generally we are flat in DCS master control board card
Platform part and algorithm part use different FPGA to realize, and due to the diversity of configuration algorithm, in order to realize inhomogeneity algorithm
Parallel quick operation, and isolation between all kinds of algorithms it is special for variety classes algorithm using multiple FPGA realization.
Due to using the communication mode of one master and multiple slaves between platform FPGA and algorithm FPGA, therefore it is integrated with pci bus IP
The FPGA of (Inte llectual Property) core can also realize this function, but embedded IP is black box, its functional module
Specific verilog implementation methods, be user not to be opened, but require to carry out functional module in nuclear power station application detailed
Complete V＆V (Verification＆Validation software verifications are with confirming) work, to ensure that functional block is safe and reliable, by
In the source code that can not take IP kernel therefore V＆V can not be carried out and completely worked, this does not meet the special applications of nuclear power I＆C system.
And there is problems with traditional pci bus mode applied to microprocessor：Pci bus controller is write tired
Difficulty, signal definition is complicated, and difficulty is write again with logical code；The port level of pci bus is fixed, and not all FPGA
All support the particular level standard；Pci bus is not carried out communication isolation, sprawling of easily breaking down.
The content of the invention
The present invention provides a kind of local bus architecture of data reliable communicating between more FPGA for nuclear power I＆C system,
Including main FPGA, two and two or more are from FPGA, the main FPGA and from passing through full duplex parallel bus transfers between FPGA
Data, it is characterised in that the main FPGA and FPGA from FPGA for embedded black box IP kernel；The main FPGA includes being provided with CRC
The data processing module of (CRC), bus data transceiver controller, I/O modules, include the number provided with CRC from FPGA
According to processing module, data dual port RAM is received, sends data dual port RAM, I/O modules.
The present invention also provides a kind of local bus of data reliable communicating between more FPGA for nuclear power I＆C system
Methods of the main FPGA with carrying out data interaction from FPGA in structure, it is characterised in that specifically include following steps：
Step 1, main FPGA carries out write operation, writes data into successively from the corresponding address of FPGA memory spaces 1；
Step 2, after the completion of main FPGA write-ins, write-in complement mark is sent to from FPGA；
Step 3, judge whether to detect write-in complement mark from FPGA, be then to enter step 4, otherwise return to step 3；
Step 4, the data in memory space 1 are read since FPGA；
Step 5, CRC check is carried out from FPGA reading process, judges whether that verification is correct, is then to enter step 6, otherwise
Return to step 3；
Step 6, sent from FPGA and read complement mark；
Step 7, main FPGA regularly judges whether to receive the reading complement mark from FPGA after the completion of write-in, is to enter
Step 8, otherwise return to step 1；
Step 8, after FPGA is handled data, it is written in the corresponding address of memory space 2；
Step 9, ready is sent from FPGA, notifies main FPGA to read, and start the reading completion that timing detects main FPGA
Mark；
Step 10, main FPGA carries out read operation after detecting the ready signals sent from FPGA, reads from FPGA and stores sky
Between 2 data；
Step 11, CRC check is carried out in main FPGA reading process, judges whether that verification is correct, be then to enter step 13, it is no
Then enter step 12；
Step 12, main FPGA does not send reading complement mark to from FPGA；
Step 13, main FPGA sends reading complement mark to from FPGA；
Step 14, judge whether detect within the set time reading complement mark that main FPGA sends from FPGA, be
Then enter step 15, otherwise return to step 9；
Step 15, this end cycle.
Using the bus structures and method of the present invention, solves the problems, such as the data reliable communication between more FPGA, also certainly
The bus mode of definition, bus control unit are voluntarily write, and black box IP particular requirement can not be used by meeting nuclear power industry.
Figure of description
The detailed bus structures figure of Fig. 1 present invention
Fig. 2 clock signals and read control signal network connection topology
Fig. 3 address signals, data-signal, write control signal connect topology with data completion signal network is read
Fig. 4 reads DSR signal network connection topology
The main FPGA of Fig. 5 and the data access interaction diagrams from FPGA
Specific embodiment
In order that goal of the invention, technical scheme and its technique effect of the present invention become apparent from, below in conjunction with accompanying drawing and tool
Body embodiment, the present invention will be described in further detail.It should be appreciated that the specific embodiment party described in this specification
Formula is not intended to limit the present invention just for the sake of explaining the present invention.
As shown in figure 1, the local bus to communicate with one another between the more FPGA of the present invention with lower part by being formed：
(1) the bus master data write by verilog, which are sent, receives controller；
(2) the bus slave data write by verilog, which are sent, receives controller；
(3) Hardware I/O Interface circuit for meeting plurality of level standard of bus signals transmitting-receiving is realized；
(4) data transfer path of master-slave equipment is connected.
The signal definition of bus is as shown in table 1,
The signal definition of the bus of table 1
The communication interface of this local bus can uniformly be arranged to following several level in FPGA：
3.3V LVTTL level standards；
3.3V LVCMOS level standards；
PCI level standards；
PCI-X level standards.
As shown in Fig. 2 the clock signal and read control signal (RD_EN1-4) of this bus are point-to-point using master-slave equipment
Connected mode, to ensure the signal integrity of clock.R1-R4 in figure is used for doing impedance termination matching use, according to actual design
Pcb board card chooses resistance.
As shown in figure 3, the address signal of this bus, data-signal, write control signal and RD_FINISH signals are using identical
Topological structure, the advantages of combining T row topological sum daisy-chained topologies, topological mode of the two mixing is employed, to ensure
The integrality of signal.R in figure is used for doing impedance termination matching use, and resistance is chosen according to actual design pcb board card.
As shown in figure 4, the reading ready for data signal (RD_READY1-4) of this bus uses the point-to-point company of master-slave equipment
Connect mode, the R1-R4 in figure, which is used for doing impedance termination matching, to be used, and resistance is chosen according to actual design pcb board card, to ensure clock
Signal integrity.
Main FPGA is with the data access interaction diagrams from FPGA as shown in figure 5, specifically including following steps：
Step 501, main FPGA carries out write operation, writes data into successively from the corresponding address of FPGA memory spaces 1；
Step 502, after the completion of main FPGA write-ins, write-in complement mark is sent to from FPGA；
Step 503, judge whether to detect write-in complement mark from FPGA, be then to enter step 504, otherwise return to step
503；
Step 504, the data in memory space 1 are read since FPGA；
Step 505, CRC check is carried out from FPGA reading process, judges whether that verification is correct, is then to enter step 506,
Otherwise return to step 503；
Step 506, sent from FPGA and read complement mark；
Step 507, main FPGA regularly judges whether to receive the reading complement mark from FPGA after the completion of write-in, is to enter
Enter step 508, otherwise return to step 501；
Step 508, after FPGA is handled data, it is written in the corresponding address of memory space 2；
Step 509, ready is sent from FPGA, notifies main FPGA to read, and the reading for starting regularly to detect main FPGA is complete
Into mark；
Step 510, main FPGA carries out read operation after detecting the ready signals sent from FPGA, reads from FPGA and stores
The data in space 2；
Step 511, CRC check is carried out in main FPGA reading process, judges whether that verification is correct, be then to enter step 513,
Otherwise step 512 is entered；
Step 512, main FPGA does not send reading complement mark to from FPGA；
Step 513, main FPGA sends reading complement mark to from FPGA；
Step 514, judge whether detect within the set time reading complement mark that main FPGA sends from FPGA, be
Then enter step 515, otherwise return to step 509；
Step 515, this end cycle.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (4)
1. the local bus architecture of data reliable communicating between a kind of more FPGA for nuclear power I＆C system, including main FPGA,
Two and two or more are from FPGA, the main FPGA and from passing through full duplex parallel bus transfers data, its feature between FPGA
It is, the main FPGA and the FPGA from FPGA for embedded black box IP kernel；The main FPGA includes the data processing mould provided with CRC
Block, bus data transceiver controller, I/O modules, include the data processing module provided with CRC from FPGA, receive data twoport
RAM, data dual port RAM, I/O modules are sent, the data by full duplex parallel bus transfers include, clock signal, number
It is believed that number, address signal, write control signal, write data complete signal, read control signal, read data complete signal, to read data accurate
Get signal ready, the clock signal and read control signal use the point-to-point connected mode of master-slave equipment；The address signal, number
It is believed that number, write control signal and read data complete signal use identical topological structure, using T row topological sum daisy-chained topologies
The topological mode of mixing；The reading ready for data signal uses the point-to-point connected mode of master-slave equipment, to ensure clock
Signal integrity.
2. local bus architecture as claimed in claim 1, it is characterised in that the bus data transceiver controller of the main FPGA
With the reception data dual port RAM from FPGA, sending data dual port RAM is write by verilog.
3. local bus architecture as claimed in claim 1, it is characterised in that the communication interface of the bus is unified in FPGA
It is arranged to 3.3V LVTTL level standards, 3.3V LVCMOS level standards, PCI level standards or PCI-X level standards.
4. sides of the main FPGA with carrying out data interaction from FPGA in any described local bus architecture in claim 1-3
Method, it is characterised in that specifically include following steps：
Step 1, main FPGA carries out write operation, writes data into successively from the corresponding address of FPGA memory spaces 1；
Step 2, after the completion of main FPGA write-ins, write-in complement mark is sent to from FPGA；
Step 3, judge whether to detect write-in complement mark from FPGA, be then to enter step 4, otherwise return to step 3；
Step 4, the data in memory space 1 are read since FPGA；
Step 5, CRC check is carried out from FPGA reading process, judges whether that verification is correct, is then to enter step 6, otherwise returns
Step 3；
Step 6, sent from FPGA and read complement mark；
Step 7, main FPGA regularly judges whether to receive the reading complement mark from FPGA after the completion of write-in, is then to enter step
8, otherwise return to step 1；
Step 8, after FPGA is handled data, it is written in the corresponding address of memory space 2；
Step 9, ready is sent from FPGA, notifies main FPGA to read, and start the reading completion mark that timing detects main FPGA
Will；
Step 10, main FPGA carries out read operation after detecting the ready signals sent from FPGA, reads from FPGA memory spaces 2
Data；
Step 11, CRC check is carried out in main FPGA reading process, judges whether that verification is correct, be then to enter step 13, otherwise enter
Enter step 12；
Step 12, main FPGA does not send reading complement mark to from FPGA；
Step 13, main FPGA sends reading complement mark to from FPGA；
Step 14, judge whether detect within the set time reading complement mark that main FPGA sends from FPGA, be to enter
Enter step 15, otherwise return to step 9；
Step 15, this end cycle.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106168933B (en) * | 2016-06-30 | 2019-08-09 | 国电南瑞科技股份有限公司 | A method of virtual dual-port shared drive is realized based on high-speed serial communication |
| CN106201629A (en) * | 2016-07-22 | 2016-12-07 | 北京广利核系统工程有限公司 | A kind of method and apparatus to the programming of multi-disc target FPGA |
| CN106815046A (en) * | 2016-12-20 | 2017-06-09 | 中核控制系统工程有限公司 | Algorithm performs method based on domain storage |
| CN109491290B (en) * | 2018-11-16 | 2020-08-14 | 西安空间无线电技术研究所 | Cold backup bus multiplexing circuit suitable for digital processing system |
| CN112506900A (en) * | 2020-11-27 | 2021-03-16 | 中广核工程有限公司 | Method, device and equipment for checking three-dimensional data of ventilation pipe of nuclear power plant and storage medium |
| CN113157637B (en) * | 2021-04-27 | 2023-03-07 | 电子科技大学 | High-capacity reconfigurable FFT operation IP core based on FPGA |
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