CN109491290B - Cold backup bus multiplexing circuit suitable for digital processing system - Google Patents
Cold backup bus multiplexing circuit suitable for digital processing system Download PDFInfo
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- CN109491290B CN109491290B CN201811369372.6A CN201811369372A CN109491290B CN 109491290 B CN109491290 B CN 109491290B CN 201811369372 A CN201811369372 A CN 201811369372A CN 109491290 B CN109491290 B CN 109491290B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21063—Bus, I-O connected to a bus
Abstract
A cold backup bus multiplexing circuit suitable for a digital processing system firstly multiplexes data signals for data transmission of a main control board and a plurality of controlled boards, a plurality of controlled FPAGs in each controlled board are interconnected in a daisy chain mode, secondly, an interface impedance isolation circuit is added on a signal path of the main control board and the controlled boards, so that impedance isolation of signals received by the controlled boards and signals sent by the controlled boards is realized, impedance matching of the main control board and the plurality of controlled boards is realized, and finally, the interface impedance matching circuit and the corresponding controlled boards are respectively and independently powered, so that the controlled boards are matched with impedance of the main control board in two states of on-off and are multiplexed with data after the controlled boards are turned on.
Description
Technical Field
The invention relates to a responder system of a multi-band and multi-mode working system in the communication field, in particular to a cold backup bus multiplexing circuit suitable for a digital processing system.
Background
In a traditional transponder communication measurement and control system, a system generally works in a single mode with fixed frequency bands and fixed frequency points. In a new generation of transponder communication measurement and control system, a complex system with multiple working frequency bands and multiple working modes is often adopted, multiple sets of FPGA are needed for core functions and main technical indexes in the system, and different software is loaded and refreshed through a system main control panel so as to realize the random switching of different systems and functions. At present, the traditional hardware design mode of multi-board data transmission is mainly realized by direct interconnection or two types of methods of data bus protocols through a low-frequency connector and a backplane connector under the working system. In a system adopting direct interconnection communication, limited node resources of a connector restrict a data transmission path required by a multi-mode system, and based on the design trend of light and small products, the system is difficult to continuously enlarge the design scale to complete mass data transmission. The data bus protocol method needs to adopt a transmission protocol of a corresponding standard, but part of FPGA interfaces do not necessarily support the mode protocol, so that the application of the interconnection mode is greatly limited. Therefore, the existing system design has various problems such as large design scale, frequent switching of multiple boards, large system power consumption and the like.
Disclosure of Invention
The technical problem solved by the invention is as follows: the circuit comprises three circuits of data multiplexing, interface impedance isolation and partition power supply management, realizes reliable transmission of high data volume multiplexing under the condition of cold backup of time-sharing startup of a plurality of board cards in the system, greatly reduces the number of data channels, improves the resource utilization rate and reduces the system power consumption compared with the traditional method.
The technical solution of the invention is as follows: a cold backup bus multiplexing circuit suitable for a digital processing system comprises a data multiplexing circuit, an interface impedance isolation circuit and a subarea power supply management circuit, wherein:
the data multiplexing circuit is used for multiplexing data signals for data transmission of the main control board and the plurality of controlled boards, data interconnection of the main control board and the plurality of controlled boards is completed by the same group of data access, data signals sent by the main control board are sent to the plurality of controlled boards through the connectors between boards, and a main control FPGA of the main control board sends the data signals to the interface impedance isolation circuit of the controlled boards through the connectors between boards;
the interface impedance isolation circuit comprises an interface chip circuit, a controlled terminal matching resistor R1 and a filter capacitor C1; the input end of the interface chip circuit receives a data signal sent by the main control FPGA, the output end of the interface chip circuit is connected with one end of the controlled terminal matching resistor R1, the other end of the controlled terminal matching resistor R1 is connected with an input pin of the controlled FPGA in the controlled board, one end of the filter capacitor C1 is connected with the controlled terminal matching resistor R1 and the input pin of the controlled FPGA in the controlled board, and the other end of the filter capacitor C1 is grounded;
the interface impedance matching circuit can ensure impedance matching and data isolation between the main control board and the controlled boards and data multiplexing after the controlled boards are started up when the controlled boards are shut down; the power supply circuit comprises a power supply chip D1, output voltage matching resistors R2 and R3, an enable state resistor R4, polarity filter capacitors C2, C3, C4 and C5, and ceramic filter capacitors C6 and C7; an input voltage VIN of a power chip D1 is connected with an anode end of a polarity filter capacitor C2, the other end of a polarity filter capacitor C2 is connected with an anode end of a polarity filter capacitor C3, the other end of the polarity filter capacitor C3 is grounded, an output voltage VOUT of D1 is connected with an anode end of a polarity filter capacitor C4, the other end of the polarity filter capacitor C5 is connected with an anode end of C5 in series, the other end of the polarity filter capacitor C5 is grounded, an output voltage VOUT end of D1 is simultaneously connected with one ends of ceramic filter capacitors C6 and C7, the other ends of C6 and C7 are grounded, an ADJ end of D1 is simultaneously connected with one ends of output voltage matching resistors R2 and R3, the other end of R2 is grounded, the other end of R3 is connected with a VOUT end of D1.
The controlled board is connected with the main control board after multiplexing and interconnecting by adopting data channels, and the data interconnection of a plurality of controlled FPGAs in the controlled board adopts a daisy chain mode.
The controlled terminal matching resistor R1 is between 200 omega and 1K omega, and the capacitance value of the filter capacitor C1 is between 0.01uF and 0.1 uF.
The interface chip circuit comprises an interface chip N1, a power supply filter capacitor C8, a power supply filter capacitor C9, a current limiting resistor R5, a current limiting resistor R6, a resistor R7 and a resistor R8; two enable ports OE1 and OE2 of the interface chip N1 are connected with a resistor R7, the other end of the resistor R7 is grounded, a power supply port VCCA1 and VCCA2 of the interface chip N1 are connected with a filter capacitor C8 and a current-limiting resistor R5, the other end of the filter capacitor C8 is grounded, the other end of the current-limiting resistor R5 is connected with a power supply VOUT, a power supply port VCCB1 and a power supply port VCCB1 of the interface chip N1 are connected with the filter capacitor C1 and the current-limiting resistor R1, the other end of the filter capacitor C1 is grounded, the other end of the current-limiting resistor R1 is connected with the power supply VOUT, data direction ports DIR1 and DIR1 of the interface chip N1 are connected with the resistor R1, the other end VOUT of the resistor R1 is connected, 8 GND ports of the interface chip N1 are grounded, a data input port 1B 1 of the N1 receives a data.
Compared with the prior art, the invention has the advantages that:
(1) the invention saves hardware resources, port resources of the main control FPGA and the number of data transmission channels by multiplexing data transmission, and has certain expandability in similar complex systems;
(2) the invention ensures that a plurality of boards of the system are clamped under a low-power-consumption working mechanism of cold backup of time-sharing startup through impedance isolation matching, and realizes the reliable multiplexing transmission of data;
(3) the independent power supply system and the board card power supply independent regional power supply system realize data multiplexing and simultaneously well reduce the power consumption of the system.
Drawings
FIG. 1 is a functional block diagram of a data multiplexing system;
FIG. 2 is a block diagram of a port equivalent model;
FIG. 3 is a functional block diagram of a partitioned power supply circuit;
FIG. 4 is a schematic block diagram of an interface chip circuit.
Detailed Description
A cold backup bus multiplexing circuit suitable for a digital processing system is realized by three circuits of data multiplexing, interface impedance isolation and partition power supply management, a data multiplexing transmission channel is combined with interface impedance isolation circuits of all controlled boards to realize that a main control board is transmitted to a plurality of controlled boards by a single-group data channel in a time-sharing multiplexing mode, the impedance of a source end port of the main control board is independent of the working state of the controlled boards, the real-time matching of signal transmission impedance is ensured under the working state that a terminal board card is started in a time-sharing mode, and the impedance mismatching of a main control FPGA port is avoided. The interface impedance isolation circuit of each controlled board adopts an independent power supply mechanism of an in-board area power supply module, when the controlled board is in a cold backup shutdown state, the interface isolation circuit still plays the role of signal isolation and impedance matching, and the multiplexing of cold backup data signals under the condition of low power consumption of the system is ensured.
The data multiplexing circuit is used for multiplexing data signals for data transmission between the main control board and the plurality of controlled boards, the number of transmission channels is equal to that of the plurality of controlled boards, and the controlled FPGAs in the boards are interconnected in a daisy chain mode;
the interface impedance isolation circuit is a first-stage receiving circuit for transmitting signals to a controlled board through an inter-board connector for the main control FPGA, and comprises an interface chip circuit, a controlled terminal matching resistor R1, a filter capacitor C1 and a controlled FPGA. After the multiplexed data signal is transmitted to the controlled board, the interface impedance isolation circuit isolates the received data signal from the source end and matches the impedance of the terminal.
On a multiplex data transmission link, the board card of the terminal in the cold backup shutdown state can cause impedance mismatch of a main control FPGA port of the source terminal board card, an anti-static diode (Vcc end) in an input port of a controlled FPGA in the shutdown state is conducted in the forward direction, an equivalent small resistor is generated in I/O, the resistance value of the resistor is similar to the output I/O impedance magnitude of the main control FPGA of the source terminal, and the impedance of the port of the source terminal is influenced. Therefore, the interface chip on the transmission link can isolate signals between boards, and the output end of the interface chip is adjacent to the I/O port of the controlled FPGA and is connected with the impedance matching resistor in series, and the signal filtering capacitor is added; the resistance value of the series resistor is far larger than the resistance value of an equivalent resistor in the source end main control FPGA logic device, so that the impedance mismatch between the controlled terminal and the source end in a cold backup state is avoided, and data multiplexing under the cold backup is realized;
the resistance value of a matching resistor R1 in the interface impedance isolation circuit is between 200 omega and 1K omega, and the capacitance value of a filter capacitor C1 is between 0.01uF and 0.1 uF;
the partition power supply management circuit strips the power supply of the part of circuits from the power supply of the controlled board card through the independent power supply design of the interface impedance matching circuit, the partition power supply of each controlled board supplies power for the interface impedance isolation circuit for a long time, and the power supply supplies power for the controlled board in a time-sharing mode according to the system requirements, so that when the board card is in a shutdown state, the interface still ensures impedance matching on a data path, and the data multiplexing of low-power time-sharing startup is ensured;
the model specification of a power supply chip in the subarea power supply management circuit is MSK5101-00, and a peripheral circuit of the subarea power supply management circuit comprises output voltage matching resistors R2 and R3, an enabling state resistor R4, polarity filter capacitors C2, C3, C4 and C5, and ceramic filter capacitors C6 and C7;
the following describes the present invention in further detail with reference to the accompanying drawings.
Considering the on-orbit operation of a satellite and a complex space radiation environment, an anti-fuse device A54SX72A-1CQ208M insensitive to single particles of ACTEL company is selected as a core processor of a main control board, and the multi-band and multi-mode program refreshing loading control of the control board is realized. The core FPGA of the controlled board adopts a chip of XQ5VFX130T-1EF1738I model number of XILINX company.
In order to save the port resources of the main control FPGA and the data transmission channel, reduce the power consumption of the system at the same time, and realize the cold backup state data multiplexing that a plurality of boards in the system can be started up in a time-sharing manner, the invention provides a bus multiplexing circuit suitable for a cold backup system, which comprises a bus multiplexing circuit, an interface impedance isolation circuit and a partition power supply management circuit, as shown in fig. 1, wherein:
(1) the data multiplexing circuit is used for multiplexing design of four groups of refreshing loading data transmission of the main control board and the two controlled boards, the main control FPGA is interconnected with the two controlled boards by four controlled FPGAs through the connectors between the boards, and the FPGAs in the controlled boards are interconnected in a daisy chain mode, so that time-sharing multiplexing transmission of multiple groups of interconnected data in the same group of data paths is realized;
(2) the interface impedance isolation circuit comprises an interface chip circuit (shown in figure 4), a terminal matching resistor R1 and a terminal filter capacitor C1, which are shown in figure 2. 54ACS164245SF is used as a core interface device, a terminal matching resistor R1 is connected between an interface chip and a controlled FPGA in series, one end of a filter capacitor C1 is connected with a signal input end of the controlled FPGA, and the other end of the filter capacitor C1 is pulled down to the ground. The interface chip circuit comprises an interface chip N1, a power supply filter capacitor C8, a power supply filter capacitor C9, a current limiting resistor R5, a current limiting resistor R6, a resistor R7 and a resistor R8; two enabling ports OE1 and OE2 of the interface chip N1 are connected in series with the resistor R7 at the same time, and the other port of the resistor R7 is grounded; the power supply power ports VCCA1 and VCCA2 of the interface chip N1 are connected in series with a filter capacitor C8 and a current-limiting resistor R5 at the same time, the other end of the filter capacitor C8 is grounded, and the other end of the current-limiting resistor R5 is connected with a power supply VOUT; the power supply ports VCCB1 and VCCB2 of the interface chip N1 are connected with the filter capacitor C9 and the current-limiting resistor R6 in series at the same time, the other end of the filter capacitor C9 is grounded, and the other end of the current-limiting resistor R6 is connected with the power supply VOUT; the data direction ports DIR1 and DIR2 of the interface chip N1 are connected with the resistor R8 in series at the same time, and the other end of the resistor R8 is connected with VOUT; 8 GND ports of the interface chip N1 are all grounded; the data input port 1B0 of N1 receives a data input signal and the data output port 1A0 of N1 sends a data output signal;
after the multiplexed data is transmitted to a controlled board, an interface impedance isolation circuit carries out isolation and filtering on a received signal and a source end port and impedance matching with a terminal;
(3) the subarea power supply management circuit adopts MSK5101-00H as a core power supply chip D1, the output rated current is 1.5A, and the use requirement of the interface impedance isolation circuit can be met. As shown in fig. 3, the peripheral circuit includes output voltage matching resistors R2 and R3, an enable state resistor R4, polarity filter capacitors C2, C3, C4 and C5, and ceramic filter capacitors C6 and C7; the input voltage VIN end of the power chip D1 is connected in series with the positive end of a polarity filter capacitor C2, the other end of the polarity filter capacitor C2 is connected in series with the positive end of a capacitor C3, and the other end of the polarity filter capacitor C3 is grounded; the output voltage VOUT of the D1 is connected with the positive terminal of the polarity filter capacitor C4, the other end of the output voltage VOUT is connected with the positive terminal of the C5 in series, and the other end of the polarity filter capacitor C5 is grounded; the output voltage VOUT end of the D1 is connected with one ends of the ceramic filter capacitors C6 and C7 at the same time, and the other ends of the ceramic filter capacitors C6 and C7 are grounded; the ADJ end of the D1 is simultaneously connected with one ends of output voltage matching resistors R2 and R3, the other end of the R2 is grounded, the other end of the R3 is simultaneously connected with the VOUT end of the D1, and the enabling state resistor R4 is connected between the ENABLE port of the D1 and VIN in series;
wherein the polar capacitors C4, C5 are placed near the output voltage port to avoid output voltage oscillation; r4 is connected in series between the ENABLE port of the power chip and VIN to set the power chip to be in an enabling working state. Through the independent power supply design of the interface impedance matching circuit, the power supply of the partial circuit is separated from the power supply of the board card, so that when the board card is in a power-off state, the interface still ensures the impedance matching on a data path, and the data multiplexing of low-power-consumption time-sharing power-on is ensured;
the invention adopts a method for reusing cold backup data, which comprises the following steps: the power supply circuit of the power supply circuit is converted into 3.3V _ J to supply power to the interface isolation circuit of each controlled board, so that the long working state of the partial circuit is ensured;
according to instruction control, the controlled board 2 is in a cold backup shutdown state, the power supply +5VIN _1 of the controlled board 1 in the system is started, the power supply +5VIN _1 is converted into voltages such as 1.0V, 2.5V, 3.3V, 3.3V _ AVDD, 3.0V _ AVDD and 1.8V needed by the board card through a plurality of DC/DC and LDO in the board respectively, and the voltages are output to various digital and analog devices in the board;
data are output by the main control FPGA by adopting a data multiplexing transmission channel, are transmitted to the controlled panel 1 through the connectors between the panels, are transmitted to the controlled FPGA1 after being isolated and matched by the interface isolation circuit in the panel, and are loaded and refreshed in the S frequency band program; after the loading and refreshing of the FPGA1 program is completed, the program is transmitted to the FPGA1 of the controlled board 1 through the same group of data transmission channels according to the command control, and the loading and refreshing of the program loaded with the C frequency band is refreshed in a daisy chain signal interconnection mode of directly transmitting the program to the FPGA2 through the FPGA1, so that the time-division multiplexing transmission of the data of the two frequency bands in the controlled board 1 is realized;
according to instruction control, the controlled board 1 is placed in a cold backup shutdown state, the power supply +5VIN _2 of the controlled board 2 in the system is started, the power supply +5VIN _2 is transmitted to the FPGA1 of the controlled board 2 through the same group of data transmission channels, and loading and refreshing of an X frequency band program are carried out; when the loading and refreshing of the programs of the FPGA1 are completed, the programs are transmitted to the FPGA1 of the controlled board 2 through the same group of data transmission channels according to the command control, and the loading and refreshing of the loaded KA band programs are refreshed in a daisy chain interconnection mode of transmitting the programs from the FPGA1 to the FPGA 2.
The invention has the advantages that the time-sharing startup under the cold backup of the system is realized by adopting a data multiplexing transmission mode and combining the circuit which is provided with interface impedance isolation and partition power supply management on each controlled board, and the power consumption of the system is reduced while the occupation of the port resources of the FPGA and the transmission channel is reduced.
The invention has been applied to a certain transponder satellite system, has realized a single machine finishes the system four working frequency bands, the switchable type work of nine working modes, the invention is simple to realize, debug flexibly, the batch is put into production many products, the uniform success. The invention is also suitable for data multiplexing transmission of the multi-board multi-chip controlled FPGA and has certain expandability.
In summary, the present invention provides a cold backup data multiplexing circuit with low hardware resources, which combines a multiplexing data transmission path with an interface impedance isolation circuit and a power supply circuit thereof, so that the impedance of the source port of the main control board does not depend on the working state of the controlled board, and realizes reliable transmission of cold backup data multiplexing of multi-board time-sharing startup in a multi-mode system with low hardware resources, and effectively reduces the system power consumption.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Claims (3)
1. A cold backup bus multiplexing circuit suitable for a digital processing system is characterized by comprising a data multiplexing circuit, an interface impedance isolation circuit and a subarea power supply management circuit, wherein:
the data multiplexing circuit is used for multiplexing data signals for data transmission of the main control board and the plurality of controlled boards, data interconnection of the main control board and the plurality of controlled boards is completed by the same group of data access, data signals sent by the main control board are sent to the plurality of controlled boards through the connectors between boards, and a main control FPGA of the main control board sends the data signals to the interface impedance isolation circuit of the controlled boards through the connectors between boards;
the interface impedance isolation circuit comprises an interface chip circuit, a controlled terminal matching resistor R1 and a filter capacitor C1; the input end of the interface chip circuit receives a data signal sent by the main control FPGA, the output end of the interface chip circuit is connected with one end of the controlled terminal matching resistor R1, the other end of the controlled terminal matching resistor R1 is connected with an input pin of the controlled FPGA in the controlled board, one end of the filter capacitor C1 is connected with the controlled terminal matching resistor R1 and the input pin of the controlled FPGA in the controlled board, and the other end of the filter capacitor C1 is grounded;
the subarea power supply management circuit is used for independently supplying power to the interface impedance matching circuit and the corresponding controlled board respectively, the subarea power supply management circuit of each controlled board supplies power to the interface impedance isolation circuit, and the power supply supplies power to the controlled board in a time-sharing manner according to the system requirements; the power supply circuit comprises a power supply chip D1, output voltage matching resistors R2 and R3, an enable state resistor R4, polarity filter capacitors C2, C3, C4 and C5, and ceramic filter capacitors C6 and C7; an input voltage VIN of a power chip D1 is connected with an anode end of a polarity filter capacitor C2, the other end of a polarity filter capacitor C2 is connected with an anode end of a polarity filter capacitor C3, the other end of the polarity filter capacitor C3 is grounded, an output voltage VOUT of D1 is connected with an anode end of a polarity filter capacitor C4, the other end of the polarity filter capacitor C5 is connected with an anode end of C5 in series, the other end of the polarity filter capacitor C5 is grounded, an output voltage VOUT end of D1 is simultaneously connected with one ends of ceramic filter capacitors C6 and C7, the other ends of C6 and C7 are grounded, an ADJ end of D1 is simultaneously connected with one ends of output voltage matching resistors R2 and R3, the other end of R2 is grounded, the other end of R3 is connected with a VOUT end of D1;
the interface chip circuit comprises an interface chip N1, a power supply filter capacitor C8, a power supply filter capacitor C9, a current limiting resistor R5, a current limiting resistor R6, a resistor R7 and a resistor R8; two enable ports OE1 and OE2 of the interface chip N1 are connected with a resistor R7, the other end of the resistor R7 is grounded, a power supply port VCCA1 and VCCA2 of the interface chip N1 are connected with a filter capacitor C8 and a current-limiting resistor R5, the other end of the filter capacitor C8 is grounded, the other end of the current-limiting resistor R5 is connected with a power supply VOUT, a power supply port VCCB1 and a power supply port VCCB1 of the interface chip N1 are connected with the filter capacitor C1 and the current-limiting resistor R1, the other end of the filter capacitor C1 is grounded, the other end of the current-limiting resistor R1 is connected with the power supply VOUT, data direction ports DIR1 and DIR1 of the interface chip N1 are connected with the resistor R1, the other end VOUT of the resistor R1 is connected, 8 GND ports of the interface chip N1 are grounded, a data input port 1B 1 of the N1 receives a data.
2. A cold-standby bus multiplexing circuit suitable for use in a digital processing system according to claim 1, wherein: the controlled board is connected with the main control board after multiplexing and interconnecting by adopting data channels, and the data interconnection of a plurality of controlled FPGAs in the controlled board adopts a daisy chain mode.
3. A cold-standby bus multiplexing circuit suitable for use in a digital processing system according to claim 1, wherein: the controlled terminal matching resistor R1 is between 200 omega and 1K omega, and the capacitance value of the filter capacitor C1 is between 0.01uF and 0.1 uF.
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| CN102880088A (en) * | 2012-10-26 | 2013-01-16 | 中联重科股份有限公司 | Expander circuit of switching value input interface |
| CN103971571A (en) * | 2014-03-26 | 2014-08-06 | 电子科技大学中山学院 | Experiment board for multi-machine system of single-chip microcomputer |
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Inventor after: Li Wenchen Inventor after: Liu Jie Inventor after: Zhao Hui Inventor after: Xing Jianli Inventor after: Liu Junfeng Inventor before: Li Wenchen Inventor before: Liu Jie Inventor before: Zhao Hui Inventor before: Xing Jianli Inventor before: Liu Junfeng |