CN114020669A - I2C link system and server based on CPLD - Google Patents

I2C link system and server based on CPLD Download PDF

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Publication number
CN114020669A
CN114020669A CN202111176950.6A CN202111176950A CN114020669A CN 114020669 A CN114020669 A CN 114020669A CN 202111176950 A CN202111176950 A CN 202111176950A CN 114020669 A CN114020669 A CN 114020669A
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cpld
signal
cpld chip
chip
motherboard
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CN114020669B (en
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白含冰
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Programmable Controllers (AREA)
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Abstract

The invention discloses an I2C link system and a server based on a CPLD, wherein the system comprises a first mainboard, downstream equipment and a CPLD chip; the first I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip performs level shift on the received first I2C signal, and transmits the corresponding first I2C signal to the corresponding downstream device through a multiplexer inside the CPLD chip after logic processing. The server configures the system. The I2C signal of the mainboard is transmitted to the CPLD chip, the CPLD chip performs logic processing, and the corresponding I2C signal is transmitted to corresponding downstream equipment through the multiplexer of the CPLD chip, so that the CPLD chip replaces a plurality of voltage level conversion chips and IO expansion chips, a large amount of board card space is saved, the board card design is facilitated, and the design cost is saved.

Description

I2C link system and server based on CPLD
Technical Field
The invention relates to an I2C link system, in particular to an I2C link system and a server based on a CPLD.
Background
With the development of cloud computing applications, informatization gradually covers various fields of society. The application proportion of the server in various industries is getting bigger and bigger. The server can maintain continuous and stable operation, and all parts are needed to cooperate to provide strong and powerful guarantee. The realization of each module mostly needs a hardware basic circuit and a software programming program for cooperative support, if the establishment of the hardware circuit is more comprehensive and complete, the realization of the software program is simpler, otherwise, if the hardware circuit completes the basic connection, the software program needs more code quantity to perfect the normal operation of the whole system.
At present, the I2C link of the server is usually a daisy chain type of independent circuit to connect with respective downstream devices, a voltage level conversion chip and an IO expansion chip are arranged on the link, and when the number of I2C links is large, the space occupation ratio of the whole I2C system circuit on the board is high.
Disclosure of Invention
In order to solve the above problems, the invention provides an I2C link system and a server based on a CPLD, which adds a CPLD chip to complete the functions of a voltage level conversion chip and an IO expansion chip in a motherboard, reduces the design of the voltage level conversion chip and the IO expansion chip, and greatly reduces the space occupation ratio of a circuit in the motherboard.
In a first aspect, the technical solution of the present invention provides an I2C link system based on a CPLD, including a first motherboard, a downstream device, and a CPLD chip;
the first I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip performs level shift on the received first I2C signal, and transmits the corresponding first I2C signal to the corresponding downstream device through a multiplexer inside the CPLD chip after logic processing.
Further, the system also comprises a second main board;
the second I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip transmits the received second I2C signal to a downstream device through level shifting, and the other signal is transmitted to the second motherboard.
Further, the second I2C signal of the first motherboard is connected to the first voltage bank interface of the CPLD chip, and the corresponding I2C signal of the second motherboard is connected to the second voltage bank interface of the CPLD chip.
Further, the first mainboard is BMC, and the second mainboard is CPU.
Further, a first voltage bank interface of the BMC connected to the CPLD chip is a P3V3 bank interface, and a second voltage bank interface of the CPU connected to the CPLD chip is a P1V8 bank interface.
Further, the first I2C signals of the first motherboard include I2C0 signals, I2C2 signals, I2C3 signals, and I2C4 signals, and the downstream devices include first, second, third, fourth, fifth, sixth, seventh, and eighth downstream devices;
the I2C0 signal is transmitted to the first downstream equipment through the CPLD chip;
the I2C2 signal is transmitted to the second downstream equipment and the third downstream equipment through the CPLD chip;
the I2C3 signal is transmitted to the fourth downstream equipment and the fifth downstream equipment through the CPLD chip;
the I2C4 signal is transmitted to the sixth, seventh, and eighth downstream devices via the CPLD chip.
Further, the early warning signal of the downstream equipment is transmitted to the first mainboard through the CPLD chip.
Furthermore, the early warning signal of the single-path downstream equipment is directly transmitted to the first mainboard through the CPLD chip, and the early warning signal of the multi-path downstream equipment is subjected to OR operation through the OR gate and then transmitted to the first mainboard through the CPLD chip.
In a second aspect, the present invention provides a server configured with any one of the above I2C link systems based on CPLD.
Compared with the prior art, the I2C link system and the server based on the CPLD have the following beneficial effects: the I2C signal of the mainboard is transmitted to the CPLD chip, the CPLD chip performs logic processing, and the corresponding I2C signal is transmitted to corresponding downstream equipment through a multiplexer of the CPLD chip, so that the CPLD chip replaces a plurality of voltage level conversion chips and IO expansion chips, a large amount of board card space is saved, board card design is facilitated, and design cost is saved.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a conventional I2C link topology.
Fig. 2 is a schematic block diagram of a topology structure of an I2C link system based on a CPLD according to an embodiment of the present invention.
Fig. 3 is a schematic block diagram of a topology structure of an I2C link system based on a CPLD according to the second embodiment.
Fig. 4 is a schematic block diagram of the voltage shift between two main boards.
Fig. 5 is a schematic block diagram of a voltage shift structure between the first main board and the second main board.
Fig. 6 is a block diagram illustrating a CPLD-based I2C link system topology according to an embodiment.
FIG. 7 is a schematic block diagram of the voltage shift principle between BMC and CPU.
Fig. 8 is a schematic diagram of transmission of a warning signal of a conventional I2C link.
Fig. 9 is a schematic diagram of transmission of an early warning signal of an I2C link system based on CPLD according to the third embodiment.
Detailed Description
The following explains some of the english terms related to the present invention.
CPLD: complex Programmable logic device;
I2C: Inter-Integrated Circuit, two-wire serial bus;
BMC: a Basebard Management Controller, a substrate Management Controller;
a Translator: the voltage level conversion chip, for example, inputs a voltage of 1.8V, and can convert the voltage into 3.3V;
IO expander: IO EXP for short and IO expansion chip;
level shift: level shifting;
device: downstream equipment;
bank: in order to facilitate management and adaptation to various electrical standards, the IO interfaces of the CPLD are divided into a plurality of banks (banks), the interface standard of each bank is determined by its interface voltage VCCO, and one bank only has one VCCO, but VCCOs of different banks may be different. Only ports of the same electrical standard can be connected together.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
With the development of cloud computing applications, informatization gradually covers various fields of society. The application proportion of the server in various industries is getting bigger and bigger. The server can maintain continuous and stable operation, and all parts are needed to cooperate to provide strong and powerful guarantee. The realization of each module mostly needs a hardware basic circuit and a software programming program for cooperative support, if the establishment of the hardware circuit is more comprehensive and complete, the realization of the software program is simpler, otherwise, if the hardware circuit completes the basic connection, the software program needs more code quantity to perfect the normal operation of the whole system. At present, the I2C link of the server is usually a daisy chain type of independent circuit to connect with respective downstream devices, a voltage level conversion chip and an IO expansion chip are arranged on the link, and when the number of I2C links is large, the space occupation ratio of the whole I2C system circuit on the board is high.
Fig. 1 is a schematic diagram of a conventional I2C link topology, in which several more common I2C connection manners are listed, for example, I2C0 of a motherboard 1 is that a motherboard and a downstream device are connected through a voltage level conversion chip; I2C1 is two motherboards and one downstream device, an I2C link in multi-master form; I2C2 is a motherboard and two downstream devices, an I2C link in the form of a multiple slave; I2C3 is formed by connecting a main board and two downstream devices through a voltage level conversion chip and an IO expansion chip; I2C4 has one more downstream device than I2C 3. In this simple topology, 5 voltage level conversion chips and 2 IO expansion chips are used, in practical application, the number of downstream devices is determined by design requirements, and may be more than 4, and a large number of voltage level conversion chips and IO expansion chips are correspondingly used, thereby greatly occupying board card space.
Therefore, the I2C link system based on the CPLD uses the CPLD chip to replace a voltage level conversion chip and an IO expansion chip, and the CPLD chip realizes the functions of the voltage level conversion chip and the IO expansion chip, so that the I2C signal of the mainboard is transmitted to downstream equipment through the CPLD chip.
Example one
Fig. 2 is a schematic block diagram of a topology structure of an I2C link system based on a CPLD according to this embodiment, which includes a first motherboard, a downstream device, and a CPLD chip.
The first I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip performs level shift on the received first I2C signal, and transmits the corresponding first I2C signal to the corresponding downstream device through a multiplexer inside the CPLD chip after logic processing.
The CPLD chip carries out level shift on the received first I2C signal, and the function of a voltage level conversion chip is realized. Because the voltage amplitude of the IO port of the CPLD chip depends on the bank reference voltage, the I2C signal of the first mainboard is accessed to a voltage bank interface at the input end of the CPLD chip, the other voltage bank interface at the output end of the CPLD chip is connected to downstream equipment, and the voltages of the input end voltage bank interface and the output end voltage bank interface are different, so that level shift is realized.
It should be noted that there is generally more than one downstream device, so that the CPLD chip transmits the received first I2C signal to the corresponding downstream device through the multiplexer inside the CPLD chip after the logic processing, so as to implement the function of the IO expansion chip. The CPLD chip is used for simple path bridging and signal transparent transmission, can be realized by using some simple logic controls, and has simple code development work.
In the I2C link system based on the CPLD provided in this embodiment, the I2C signal of the motherboard is transmitted to the CPLD chip, the CPLD chip performs logic processing, and the multiplexer of the CPLD chip transmits the corresponding I2C signal to the corresponding downstream device, so that the CPLD chip replaces a plurality of voltage level conversion chips and IO expansion chips, a large amount of board space is saved, board design is facilitated, and design cost is saved.
Example two
Considering that the motherboard can be connected to not only the downstream device but also another motherboard through the I2C link, on the basis of the first embodiment, the second embodiment provides a CPLD-based I2C link system, which connects the downstream device and another motherboard through the CPLD chip.
Fig. 3 is a schematic block diagram of a topology structure of an I2C link system based on a CPLD according to a second embodiment, which includes a first motherboard, a second motherboard, a downstream device, and a CPLD chip.
The first I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip performs level shift on the received first I2C signal, and transmits the corresponding first I2C signal to the corresponding downstream device through a multiplexer inside the CPLD chip after logic processing.
The second I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip transmits the received second I2C signal to a downstream device through level shifting, and the other signal is transmitted to the second motherboard.
In the I2C link system based on CPLD provided in the second embodiment, the I2C signal of the motherboard is transmitted to the CPLD chip, the CPLD chip performs logic processing, the multiplexer of the CPLD chip transmits the corresponding I2C signal to the corresponding downstream device, and the I2C signal of the motherboard is also connected to another motherboard via the CPLD chip, so that the CPLD chip replaces a plurality of voltage level conversion chips and IO expansion chips, thereby saving a large amount of board space, facilitating board design, and saving design cost.
Generally, the amplitudes of voltages at two sides of I2C interconnected by two motherboards are different, and voltage shift is needed in the middle for voltage conversion, as shown in fig. 4, a schematic block diagram of a principle of voltage shift between two motherboards is shown.
In this embodiment, the voltage shift between the two motherboards is also realized through a voltage bank interface, specifically, as shown in fig. 5, a schematic block diagram of a voltage shift structure between the first motherboard and the second motherboard is shown, a second I2C signal of the first motherboard is connected to a first voltage bank interface of the CPLD chip, a corresponding I2C signal of the second motherboard is connected to a second voltage bank interface of the CPLD chip, and the two interfaces are connected through the inside of the CPLD chip. The first voltage bank interface and the second voltage bank interface have different reference voltages.
To further explain the present invention, a specific embodiment is provided below, and fig. 6 is a schematic block diagram of a topology of a CPLD-based I2C link system.
The first I2C signals of the first motherboard include I2C0 signals, I2C2 signals, I2C3 signals, and I2C4 signals, and the downstream DEVICEs include a first downstream DEVICE (DEVICE 0), a second downstream DEVICE (DEVICE 2), a third downstream DEVICE (DEVICE 3), a fourth downstream DEVICE (DEVICE 4), a fifth downstream DEVICE (DEVICE 5), a sixth downstream DEVICE (DEVICE 6), a seventh downstream DEVICE (DEVICE 7), and an eighth downstream DEVICE (DEVICE 8).
The I2C0 signal is transmitted to the first downstream equipment through the CPLD chip; the I2C2 signal is transmitted to the second downstream equipment and the third downstream equipment through the CPLD chip; the I2C3 signal is transmitted to the fourth downstream equipment and the fifth downstream equipment through the CPLD chip; the I2C4 signal is transmitted to the sixth, seventh, and eighth downstream devices via the CPLD chip.
Of course, the second I2C signal (i.e., I2C1 signal) of the first motherboard is also transmitted to the second motherboard and the ninth downstream DEVICE (DEVICE 1) via the CPLD chip.
When the first motherboard is a BMC and the second motherboard is a CPU, voltage shift from 3.3V to 1.8V needs to be performed between the BMC and the CPU, as shown in fig. 7, which is a schematic block diagram of a voltage shift principle structure between the BMC and the CPU, the BMC is connected to a P3V3 bank interface of the CPLD chip, the CPU is connected to a P1V8 bank interface of the CPLD chip, and the two bank interfaces are communicated inside the CPLD chip.
EXAMPLE III
I2C has warning signals (alert signals) in addition to SCL and SDA signals, which also differ for different I2C links. Fig. 8 is a schematic diagram of transmission of an existing I2C link early warning signal, which is mainly divided into an early warning signal of a single-channel downstream device, an early warning signal of a multi-channel downstream device, and an early warning signal with an IO extension chip. The early warning signal with the IO expansion chip is transmitted to the mainboard 1 by the IO expansion chip.
Fig. 9 is a schematic diagram of transmission of an early warning signal of an I2C link system based on CPLD according to the third embodiment.
The early warning signal of the downstream equipment is transmitted to the first mainboard through the CPLD chip. Specifically, the early warning signal to the single-channel downstream equipment is directly transmitted to the first mainboard through the CPLD chip, and the early warning signal to the multi-channel downstream equipment is subjected to OR operation through the OR gate and then transmitted to the second mainboard through the CPLD chip.
For example, the early warning signals of the first downstream device and the ninth downstream device are directly transmitted to the first mainboard through the CPLD chip, the early warning signals of the second downstream device and the third downstream device are subjected to or operation through the or gate and then transmitted to the first mainboard through the CPLD chip, the early warning signals of the fourth downstream device and the fifth downstream device are subjected to or operation through the or gate and then transmitted to the first mainboard through the CPLD chip, and the early warning signals of the sixth downstream device, the seventh downstream device and the eighth downstream device are subjected to or operation through the or gate and then transmitted to the first mainboard through the CPLD chip.
Example four
The fourth embodiment provides a server, which can configure the CPLD-based I2C link system in any of the above embodiments.
The server of the present embodiment is implemented based on the aforementioned CPLD-based I2C link system, so that the specific implementation of the server can be seen in the foregoing part of the embodiment of the CPLD-based I2C link system, and therefore, the specific implementation thereof can refer to the description of the corresponding respective partial embodiments, and will not be further described herein.
In addition, since the server of this embodiment is implemented based on the aforementioned I2C link system based on CPLD, its role corresponds to that of the above method, and is not described here again.
The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.

Claims (9)

1. The I2C link system based on the CPLD is characterized by comprising a first mainboard, downstream equipment and a CPLD chip;
the first I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip performs level shift on the received first I2C signal, and transmits the corresponding first I2C signal to the corresponding downstream device through a multiplexer inside the CPLD chip after logic processing.
2. The CPLD based I2C link system of claim 1, further comprising a second motherboard;
the second I2C signal of the first motherboard is transmitted to the CPLD chip, the CPLD chip transmits the received second I2C signal to a downstream device through level shifting, and the other signal is transmitted to the second motherboard.
3. The CPLD-based I2C link system according to claim 2, wherein the second I2C signal of the first motherboard is connected to the first voltage bank interface of the CPLD chip, and the corresponding I2C signal of the second motherboard is connected to the second voltage bank interface of the CPLD chip.
4. The CPLD-based I2C link system according to claim 3, wherein the first motherboard is a BMC and the second motherboard is a CPU.
5. The CPLD-based I2C link system according to claim 4, wherein the first voltage bank interface of the BMC connected to the CPLD chip is P3V3 bank interface, and the second voltage bank interface of the CPU connected to the CPLD chip is P1V8 bank interface.
6. The CPLD-based I2C link system of claim 3, 4 or 5, wherein the first I2C signal of the first motherboard includes an I2C0 signal, an I2C2 signal, an I2C3 signal and an I2C4 signal, and the downstream devices include a first downstream device, a second downstream device, a third downstream device, a fourth downstream device, a fifth downstream device, a sixth downstream device, a seventh downstream device and an eighth downstream device;
the I2C0 signal is transmitted to the first downstream equipment through the CPLD chip;
the I2C2 signal is transmitted to the second downstream equipment and the third downstream equipment through the CPLD chip;
the I2C3 signal is transmitted to the fourth downstream equipment and the fifth downstream equipment through the CPLD chip;
the I2C4 signal is transmitted to the sixth, seventh, and eighth downstream devices via the CPLD chip.
7. The CPLD-based I2C link system according to claim 6, wherein the early warning signal of the downstream device is transmitted to the first motherboard via the CPLD chip.
8. The I2C link system based on CPLD according to claim 7, wherein the early warning signal of the single-channel downstream device is directly transmitted to the first motherboard via the CPLD chip, and the early warning signal of the multi-channel downstream device is OR-operated via the OR gate and then transmitted to the first motherboard via the CPLD chip.
9. A server, characterized by configuring a CPLD based I2C link system of any one of claims 1-8.
CN202111176950.6A 2021-10-09 2021-10-09 CPLD-based I2C link system and server Active CN114020669B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115982086A (en) * 2023-02-14 2023-04-18 井芯微电子技术(天津)有限公司 Chip prototype verification board

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