CN114020669B - CPLD-based I2C link system and server - Google Patents

CPLD-based I2C link system and server Download PDF

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CN114020669B
CN114020669B CN202111176950.6A CN202111176950A CN114020669B CN 114020669 B CN114020669 B CN 114020669B CN 202111176950 A CN202111176950 A CN 202111176950A CN 114020669 B CN114020669 B CN 114020669B
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signal
cpld
cpld chip
transmitted
chip
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CN114020669A (en
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白含冰
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses an I2C link system and a server based on CPLD, wherein the system comprises a first main board, downstream equipment and a CPLD chip; the first I2C signal of the first main board is transmitted to the CPLD chip, the CPLD chip carries out level shift on the received first I2C signal, and the corresponding first I2C signal is transmitted to corresponding downstream equipment through a multiplexer in the CPLD chip after logic processing. The server configures the system. The I2C signals of the main board are transmitted to the CPLD chip, the CPLD chip performs logic processing, and the corresponding I2C signals are transmitted to corresponding downstream equipment through the multiplexer of the CPLD chip, so that the CPLD chip replaces a plurality of voltage level conversion chips and IO expansion chips, a large amount of board card space is saved, the board card design is facilitated, and the design cost is saved.

Description

CPLD-based I2C link system and server
Technical Field
The invention relates to an I2C link system, in particular to an I2C link system based on CPLD and a server.
Background
With the development of cloud computing applications, informatization is gradually covered to various fields of society. Servers are increasingly being used in a wide variety of industries. The server can maintain continuous and stable operation, and the cooperation of all parts is required to provide powerful guarantee. The implementation of each module is mostly supported by cooperation of a hardware basic circuit and a software programming program, if the hardware circuit is built more comprehensively and completely, the implementation of the software programming is simpler, otherwise, if the hardware circuit is connected with the basic circuit, the software programming needs more code quantity to perfect the normal operation of the whole system.
At present, the server I2C links are usually independent circuits and are connected with respective downstream devices in a daisy chain mode, a voltage level conversion chip and an IO expansion chip are arranged on the links, and when the number of the I2C links is large, the space occupation of the whole I2C system circuit on a board card is relatively high.
Disclosure of Invention
In order to solve the problems, the invention provides an I2C link system and a server based on a CPLD, which are characterized in that the functions of a voltage level conversion chip and an IO expansion chip in a main board are increased by adding a CPLD chip, the designs of the middle voltage level conversion chip and the IO expansion chip are reduced, and the space occupation ratio of a circuit in the main board is greatly reduced.
In a first aspect, the present invention provides a CPLD-based I2C link system, including a first motherboard, a downstream device, and a CPLD chip;
the first I2C signal of the first main board is transmitted to the CPLD chip, the CPLD chip carries out level shift on the received first I2C signal, and the corresponding first I2C signal is transmitted to corresponding downstream equipment through a multiplexer in the CPLD chip after logic processing.
Further, the system also comprises a second main board;
and the CPLD chip transmits the received second I2C signal to downstream equipment through level shift, and the other path of the received second I2C signal is transmitted to the second main board.
Further, a second I2C signal of the first motherboard is connected to a first voltage bank interface of the CPLD chip, and a corresponding I2C signal of the second motherboard is connected to a second voltage bank interface of the CPLD chip.
Further, the first main board is a BMC, and the second main board is a CPU.
Further, the first voltage bank interface of the BMC connected to the CPLD chip is a P3V3 bank interface, and the second voltage bank interface of the CPU connected to the CPLD chip is a P1V8 bank interface.
Further, the first I2C signal of the first motherboard includes an I2C0 signal, an I2C2 signal, an I2C3 signal, and an I2C4 signal, and the downstream devices include a first downstream device, a second downstream device, a third downstream device, a fourth downstream device, a fifth downstream device, a sixth downstream device, a seventh downstream device, and an eighth downstream device;
the I2C0 signal is transmitted to a first downstream device through the CPLD chip;
the I2C2 signal is transmitted to the second downstream equipment and the third downstream equipment through the CPLD chip;
the I2C3 signal is transmitted to a fourth downstream device and a fifth downstream device through the CPLD chip;
the I2C4 signal is transmitted to the sixth downstream device, the seventh downstream device and the eighth downstream device through the CPLD chip.
Further, the early warning signal of the downstream device is transmitted to the first main board through the CPLD chip.
Further, the early warning signals of the single-path downstream equipment are directly transmitted to the first main board through the CPLD chip, and the early warning signals of the multi-path downstream equipment are transmitted to the first main board through the CPLD chip after OR operation is carried out on the early warning signals of the multi-path downstream equipment.
In a second aspect, the present invention provides a server configured with any one of the CPLD-based I2C link systems described above.
Compared with the prior art, the I2C link system and the server based on the CPLD have the following beneficial effects: the I2C signals of the main board are transmitted to the CPLD chip, the CPLD chip performs logic processing, and the corresponding I2C signals are transmitted to corresponding downstream equipment through a multiplexer of the CPLD chip, so that the CPLD chip replaces a plurality of voltage level conversion chips and IO expansion chips, a large amount of board card space is saved, the board card design is facilitated, and the design cost is saved.
Drawings
For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.
Fig. 1 is a schematic diagram of a conventional I2C link topology.
Fig. 2 is a schematic block diagram of a CPLD-based I2C link system topology according to an embodiment of the present invention.
Fig. 3 is a schematic block diagram of a CPLD-based I2C link system topology structure according to the second embodiment.
Fig. 4 is a schematic block diagram of the voltage shift principle between two main boards.
Fig. 5 is a schematic block diagram of a voltage shift structure between a first motherboard and a second motherboard.
Fig. 6 is a schematic block diagram of a CPLD-based I2C link system topology of a specific embodiment.
Fig. 7 is a schematic block diagram of the voltage shift principle between the BMC and the CPU.
Fig. 8 is a schematic diagram of transmission of an early warning signal of a conventional I2C link.
Fig. 9 is a schematic diagram of early warning signal transmission of an I2C link system based on a CPLD according to the third embodiment.
Detailed Description
The following explains some of the english terms related to the present invention.
CPLD: complex Programmable logic device, complex programmable logic devices;
I2C: inter-Integrated Circuit, two-wire serial bus;
BMC: baseboard Management Controller, baseboard management controller;
translabor: a voltage level conversion chip, for example, input at 1.8V voltage, can convert it to 3.3V;
IO expander: IO EXP for short, IO expansion chip;
level shift: level shifting;
device: a downstream device;
bank: in order to facilitate management and adapting to various electrical appliance standards, the IO interfaces of the CPLD are divided into several groups (banks), and the interface standard of each bank is determined by the interface voltage VCCO thereof, and one bank can only have one VCCO, but the VCCO of different banks can be different. Only ports of the same electrical standard can be connected together.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
With the development of cloud computing applications, informatization is gradually covered to various fields of society. Servers are increasingly being used in a wide variety of industries. The server can maintain continuous and stable operation, and the cooperation of all parts is required to provide powerful guarantee. The implementation of each module is mostly supported by cooperation of a hardware basic circuit and a software programming program, if the hardware circuit is built more comprehensively and completely, the implementation of the software programming is simpler, otherwise, if the hardware circuit is connected with the basic circuit, the software programming needs more code quantity to perfect the normal operation of the whole system. At present, the server I2C links are usually independent circuits and are connected with respective downstream devices in a daisy chain mode, a voltage level conversion chip and an IO expansion chip are arranged on the links, and when the number of the I2C links is large, the space occupation of the whole I2C system circuit on a board card is relatively high.
Fig. 1 is a schematic diagram of an existing I2C link topology, in which several common I2C connection manners are listed, for example, I2C0 of a motherboard 1 is a motherboard and a downstream device are connected through a voltage level conversion chip; I2C1 is an I2C link of two main boards and one downstream device, a multi-master form; I2C2 is a motherboard and two downstream devices, an I2C link in the form of multiple slaves; the I2C3 is that a main board and two downstream devices are connected through a voltage level conversion chip and an IO expansion chip; I2C4 has one more downstream device than I2C 3. In this simple topology, 5 voltage level conversion chips and 2 IO expansion chips are used, and in practical application, the number of downstream devices is determined by design requirements, possibly more than 4, and a large number of voltage level conversion chips and IO expansion chips are correspondingly used, so that the board space is greatly occupied.
Therefore, the invention provides an I2C link system based on CPLD, which uses CPLD chip to replace voltage level conversion chip and IO expansion chip, and the CPLD chip realizes the functions of the voltage level conversion chip and the IO expansion chip, so that the I2C signal of the main board is transmitted to downstream equipment through the CPLD chip.
Example 1
Fig. 2 is a schematic block diagram of a CPLD-based I2C link system topology according to the first embodiment, which includes a first motherboard, a downstream device, and a CPLD chip.
The first I2C signal of the first main board is transmitted to the CPLD chip, the CPLD chip carries out level shift on the received first I2C signal, and the corresponding first I2C signal is transmitted to corresponding downstream equipment through a multiplexer in the CPLD chip after logic processing.
The CPLD chip performs level shift on the received first I2C signal to realize the function of a voltage level conversion chip. Because the IO port voltage amplitude of the CPLD chip depends on the bank reference voltage, the I2C signal of the first main board is connected into a voltage bank interface of the input end of the CPLD chip, the other voltage bank interface of the output end of the CPLD chip is connected to downstream equipment, and the voltages of the input end voltage bank interface and the output end voltage bank interface are different, so that level shift is realized.
It should be noted that, the downstream devices are generally more than one, so the CPLD chip transmits the received first I2C signal to the corresponding downstream device through the multiplexer inside the CPLD chip after logic processing, so as to implement the function of the IO expansion chip. The CPLD chip is used for simple path bridging and signal transmission, can be realized by using some simple logic control, and has simple code development work.
In the I2C link system based on the CPLD provided in the first embodiment, the I2C signal of the motherboard is transmitted to the CPLD chip, the CPLD chip performs logic processing, and the corresponding I2C signal is transmitted to the corresponding downstream device through the multiplexer of the CPLD chip, so that the CPLD chip replaces numerous voltage level conversion chips and IO expansion chips, a large amount of board space is saved, board design is facilitated, and design cost is saved.
Example two
Considering that the main board is connected to not only the downstream device but also another main board through the I2C link, based on the first embodiment, the second embodiment provides a CPLD-based I2C link system, where the downstream device and the another main board are connected simultaneously through the CPLD chip.
Fig. 3 is a schematic block diagram of a CPLD-based I2C link system topology structure according to a second embodiment, which includes a first motherboard, a second motherboard, a downstream device, and a CPLD chip.
The first I2C signal of the first main board is transmitted to the CPLD chip, the CPLD chip carries out level shift on the received first I2C signal, and the corresponding first I2C signal is transmitted to corresponding downstream equipment through a multiplexer in the CPLD chip after logic processing.
And the CPLD chip transmits the received second I2C signal to downstream equipment through level shift, and the other path of the received second I2C signal is transmitted to the second main board.
In the I2C link system based on the CPLD provided in the second embodiment, the I2C signal of the motherboard is transmitted to the CPLD chip, the CPLD chip performs logic processing, the corresponding I2C signal is transmitted to the corresponding downstream device through the multiplexer of the CPLD chip, and meanwhile, the I2C signal of the motherboard can be connected to another motherboard through the CPLD chip, so that the CPLD chip replaces a plurality of voltage level conversion chips and IO expansion chips, a large amount of board space is saved, board design is facilitated, and design cost is saved.
In general, two voltage amplitudes at two sides of an I2C interconnect two main boards are different, and voltage shift is needed in the middle to perform voltage conversion, as shown in fig. 4, which is a schematic block diagram of voltage shift between two main boards.
The voltage shift between the two mainboards in this embodiment is also implemented through a voltage bank interface, specifically, as shown in fig. 5, which is a schematic block diagram of a voltage shift structure between the first and second mainboards, where the second I2C signal of the first mainboard is connected to the first voltage bank interface of the CPLD chip, and the corresponding I2C signal of the second mainboard is connected to the second voltage bank interface of the CPLD chip, and then the two signals are communicated by the interior of the CPLD chip. The reference voltages of the first voltage bank interface and the second voltage bank interface are different.
For further explanation of the present invention, a specific embodiment is provided below, and a schematic block diagram of the CPLD-based I2C link system topology of this specific embodiment is shown in fig. 6.
The first I2C signal of the first main board includes an I2C0 signal, an I2C2 signal, an I2C3 signal, and an I2C4 signal, and the downstream DEVICEs include a first downstream DEVICE (DEVICE 0), a second downstream DEVICE (DEVICE 2), a third downstream DEVICE (DEVICE 3), a fourth downstream DEVICE (DEVICE 4), a fifth downstream DEVICE (DEVICE 5), a sixth downstream DEVICE (DEVICE 6), a seventh downstream DEVICE (DEVICE 7), and an eighth downstream DEVICE (DEVICE 8).
The I2C0 signal is transmitted to a first downstream device through the CPLD chip; the I2C2 signal is transmitted to the second downstream equipment and the third downstream equipment through the CPLD chip; the I2C3 signal is transmitted to a fourth downstream device and a fifth downstream device through the CPLD chip; the I2C4 signal is transmitted to the sixth downstream device, the seventh downstream device and the eighth downstream device through the CPLD chip.
Of course, the second I2C signal (i.e., the I2C1 signal) of the first motherboard is also transmitted to the second motherboard and the ninth downstream DEVICE (DEVICE 1) via the CPLD chip.
When the first main board is a BMC and the second main board is a CPU, voltage shift between 3.3V and 1.8V is required between the BMC and the CPU, as shown in FIG. 7, which is a schematic block diagram of the principle of voltage shift between the BMC and the CPU, the BMC is connected to a P3V3 bank interface of the CPLD chip, the CPU is connected to a P1V8 bank interface of the CPLD chip, and the two bank interfaces are communicated inside the CPLD chip.
Example III
The I2C has an early warning signal (alert signal) in addition to the SCL and SDA signals, which also varies for different I2C links. Fig. 8 is a schematic diagram of transmission of an early warning signal of an existing I2C link, which is mainly divided into an early warning signal of a single downstream device, an early warning signal of a plurality of downstream devices, and an early warning signal with an IO expansion chip. The early warning signal of the IO expansion chip is transmitted to a GPIO signal of the main board 1 by the IO expansion chip.
Fig. 9 is a schematic diagram of early warning signal transmission of an I2C link system based on a CPLD according to the third embodiment.
And the early warning signal of the downstream equipment is transmitted to the first main board through the CPLD chip. Specifically, the early warning signals of the single-path downstream equipment are directly transmitted to the first main board through the CPLD chip, and the early warning signals of the multi-path downstream equipment are OR-operated and then transmitted to the second main board through the CPLD chip.
For example, early warning signals of the first downstream device and the ninth downstream device are directly transmitted to the first main board through the CPLD chip, early warning signals of the second downstream device and the third downstream device are transmitted to the first main board through the CPLD chip after being subjected to OR operation through an OR gate, early warning signals of the fourth downstream device and the fifth downstream device are transmitted to the first main board through the CPLD chip after being subjected to OR operation through an OR gate, and early warning signals of the sixth downstream device, the seventh downstream device and the eighth downstream device are transmitted to the first main board through the CPLD chip after being subjected to OR operation through an OR gate.
Example IV
The fourth embodiment provides a server, which can configure the CPLD-based I2C link system of any one of the above embodiments.
The server of this embodiment is implemented based on the CPLD-based I2C link system described above, and thus, the detailed description of the server can be found in the example section of the CPLD-based I2C link system described above, so, the detailed description of the server can refer to the description of the examples of the respective sections, and will not be described herein.
In addition, since the server of the present embodiment is implemented based on the CPLD-based I2C link system, the function thereof corresponds to the function of the method described above, and the description thereof will not be repeated here.
The foregoing disclosure is merely illustrative of the preferred embodiments of the invention and the invention is not limited thereto, since modifications and variations may be made by those skilled in the art without departing from the principles of the invention.

Claims (7)

1. The CPLD-based I2C link system is characterized by comprising a first main board, downstream equipment and a CPLD chip;
the method comprises the steps that a first I2C signal of a first main board is transmitted to a CPLD chip, the CPLD chip carries out level shift on the received first I2C signal, and after logic processing, the corresponding first I2C signal is transmitted to corresponding downstream equipment through a multiplexer in the CPLD chip;
the system also includes a second motherboard;
the second I2C signal of the first main board is transmitted to the CPLD chip, the CPLD chip transmits the received second I2C signal to downstream equipment through level shift by one path, and the second I2C signal is transmitted to the second main board by the other path;
the first I2C signal of the first motherboard includes an I2C0 signal, an I2C2 signal, an I2C3 signal, and an I2C4 signal, and the downstream devices include a first downstream device, a second downstream device, a third downstream device, a fourth downstream device, a fifth downstream device, a sixth downstream device, a seventh downstream device, and an eighth downstream device;
the I2C0 signal is transmitted to a first downstream device through the CPLD chip;
the I2C2 signal is transmitted to the second downstream equipment and the third downstream equipment through the CPLD chip;
the I2C3 signal is transmitted to a fourth downstream device and a fifth downstream device through the CPLD chip;
the I2C4 signal is transmitted to the sixth downstream device, the seventh downstream device and the eighth downstream device through the CPLD chip.
2. The CPLD-based I2C link system according to claim 1, wherein a second I2C signal of the first motherboard is connected to a first voltage bank interface of the CPLD chip, and a corresponding I2C signal of the second motherboard is connected to a second voltage bank interface of the CPLD chip.
3. The CPLD-based I2C link system according to claim 2, wherein the first motherboard is a BMC and the second motherboard is a CPU.
4. The CPLD-based I2C link system according to claim 3, wherein the first voltage bank interface to which the BMC is connected to the CPLD chip is a P3V3 bank interface, and the second voltage bank interface to which the CPU is connected to the CPLD chip is a P1V8 bank interface.
5. The CPLD-based I2C link system of any one of claims 1-4, wherein the pre-warning signal of the downstream device is transmitted to the first motherboard via the CPLD chip.
6. The CPLD-based I2C link system according to claim 5, wherein the early warning signals of the downstream devices in a single path are directly transmitted to the first motherboard via the CPLD chip, and the early warning signals of the downstream devices in multiple paths are ored by the or gate and then transmitted to the first motherboard via the CPLD chip.
7. A server, characterized in that it is configured with the CPLD-based I2C link system as claimed in any one of claims 1-6.
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