CN104424154A - Universal Spi (serial Peripheral Interface) - Google Patents
Universal Spi (serial Peripheral Interface) Download PDFInfo
- Publication number
- CN104424154A CN104424154A CN201410404682.2A CN201410404682A CN104424154A CN 104424154 A CN104424154 A CN 104424154A CN 201410404682 A CN201410404682 A CN 201410404682A CN 104424154 A CN104424154 A CN 104424154A
- Authority
- CN
- China
- Prior art keywords
- data
- latch
- input
- electrically coupled
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Information Transfer Systems (AREA)
Abstract
A Universal SPI (10) is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI includes multiple latches (12, 14, 20), buffers (22, 24), and in an alternative embodiment, a multiplexer (50)is configured together, such that the universal SPI is provided that can be readily reconfigured by using only input signals to provide compatibility across multiple bus interfaces.
Description
Technical field
Relate generally to bus interface devices of the present invention and the method for electronic system.More particularly, the present invention relates to and also can connect except the system and method for reconfigurable SPI (serial peripheral interface) bus of the various interfaces of SPI by interface for providing.
Background technology
Serial data bus is widely used in electronic application, such as automotive electronics, computer, hand-held device, inertial navigation system, household electrical appliance, consumption electronic product, protection system and other industry much, science, engineering and portable system.This serial data bus can be used to allow between the various electronic circuits in setter, at various peripheral unit and intrasystem main device and communicate and shared data between compared with the multiple systems in Iarge-scale system.SPI (serial peripheral interface) is a kind of serial data bus system communicated and the agreement that are developed to contribute to carrying out data and information with a kind of serial mode of particular type.SPI provides synchronous four-wire interface to simple peripheral unit, and is adopted by many companies with the connection allowing such as peripheral unit.
Accompanying drawing explanation
(not necessarily draw in proportion) by reference to the accompanying drawings and consult detail specifications and claim, can have than more complete understanding the present invention.Wherein in the accompanying drawings, similar reference symbol represents identical element, and:
Fig. 1 show according to an embodiment the block scheme of the general SPI device of content configuration of teaching;
Fig. 2 A shows the block scheme of the general SPI device of the Fig. 1 configured in SPI pattern;
Fig. 2 B shows the representative sequential chart of the general SPI device of Fig. 2 A;
Fig. 3 A shows the block scheme of the general SPI device of the Fig. 1 configured in DSA pattern;
Fig. 3 B shows the representative sequential chart of the general SPI device of Fig. 3 A;
Fig. 4 A shows at the block scheme with the general SPI device improving the Fig. 1 configured in the DSA pattern of immunity to interference;
Fig. 4 B shows the representative sequential chart of the general SPI device of Fig. 4 A;
Fig. 5 A shows the block scheme of the general SPI device of the Fig. 1 configured in shift register mode;
Fig. 5 B shows the representative sequential chart of the general SPI device of Fig. 5 A;
Fig. 6 A shows at the block scheme with the general SPI device improving the Fig. 1 configured in the shift register mode of immunity to interference;
Fig. 6 B shows the representative sequential chart of the general SPI device of Fig. 6 A;
Fig. 7 show according to alternate embodiment the block scheme of the general SPI device of content configuration of teaching.
Embodiment
Spi bus can be connected to and the SPI peripheral unit run has four SPI signal pins usually: SDI, SDO, SSB and SCLK thereon.SDI, is abbreviated as " serial date transfer ", is the serial date transfer to peripheral unit, and it is usually from its signal of SPI master controller reception be present in spi bus.SDO, being abbreviated as " serial data output ", is the output from SPI peripheral unit.(that is, it does not provide any output and source or remittance (leakage) (sink) any electric current) of its normally tri-state, unless SSB signal (discussing below) is for low.In this case (SSB is low), SDO provides data to export to spi bus.By operating by this way, multiple SPI periphery exports and can be connected to spi bus at one time, and can not cause signal disturbing.SSB, is abbreviated as " subordinate selection bus-bar ", when master controller wishes to communicate with SPI periphery, is moved to low by SPI master controller.When SSB is high, peripheral SPI device ignores all signals on SDI and SCLK line (SCLK is discussed below), and as mentioned above, SDO is tri-state.SCLK, is abbreviated as " serial clock " and is supplied to SPI peripheral unit on spi bus by SPI master controller.When SPI periphery (or subordinate) device is activated by its SSB input being dragged down, it will input chronometric data by SDI on SCLK signal rising edge, and on SCLK signal negative edge, export data by SDO pin subsequently.In this case, the data that SDI input provides must be stablized before SCLK signal rising edge, and must remain unchanged in the specific retention time section afterwards of rising clock edge (but suppose that this retention time reaches, these data are allowed to change before decline clock edge).By at SCLK signal rising clock along chronometric data, and in SCLK signal negative edge chronometric data, when multiple SPI peripheral unit connected place time, can sequence problem be avoided.
Some electronic installation can be configured to shared data and use directly not compatible with SPI universal serial bus serial or parallel bus to communicate.Such as, digital step attenuator (DSA) device often needs to comprise RF device with other device and carries out interface, and comprises serial or parallel bus interface.Some DSA product utilization universal serial bus on market, although itself and SPI universal serial bus have certain similarity, incompatible with SPI universal serial bus.In other words, these products can not work when not having additional interface circuit in SPI serial bus system, and this is expensive in cost and circuit board space.Such as, some the DSA product requirement SDI data-signal on market is stable before SCLK signal (being similar to SPI protocol) rising edge, but also needs SDI data
remain unchanged, until SCLK signal negative edge
afterwards(being different from SPI protocol to require).Typical DSA interface is called as " shift register ", and is similar to SPI, except SDO is in SCLK rising edge instead of negative edge in the near future just change.Most of microcontroller SPI interfaces on market can not meet stricter DSA timing requirements when not adding discrete logic components to system.
As mentioned above, some DSA device comprises parallel bus interface to carry out interface with other assembly or device, wherein parallel interface signal is from general purpose I/O pin (GPIO) or use serial-parallel shift register setting, such as, for the 74xx164 type device of interface object.Most of microcontroller interfaces on market are not easy and these devices when not having additional external shift register or software to force GPIO pin to serve as such shift register, comprise DSA device compatible.
Although the company of design DSA shift register and the other products of RF and be used to build such as power amplifier palette other market theory on can make to work together with device with circuit by adding additional logic, this solution is not best.Ideally, the built-in and various microcontroller of these DSA and other products and relevant parallel and serial line interface, comprise the compatibility of SPI, and do not need the space increasing cost, complicacy and additional interface logical requirements.There is provided the existing shift register that both may have with consumer to design compatibility, also may be used for needing the single device of the design based on microcontroller of standard SPI to be highly profitable.In addition, there is built-in DSA with multibus protocol-compliant and other products provides and like a cork these new products can be dropped into the advantage in existing design, and no matter existing bus protocol how, and without the need to redesigning or changing main circuit plate.
On the one hand, general SPI device is provided, without the need to additional interface logical OR software, this general SPI device and spi bus, existing DSA, utilize the other products that has and be similar to the interface of (but incompatible) SPI and the universal serial bus of agreement and to require and 74xx164 type signal sends compatible parallel bus compatibility.On the other hand, provide the general SPI device having and reduce number of pins, it provide identical general-purpose interface, but use less outside output pin.This general SPI device can be configured to work together with agreement with dissimilar bus, interface, and this depends on how the input of general SPI device is configured, and which signal input is connected to.Therefore, provide the design object realizing keeping low cost and the dirigibility used in raising existing system design simultaneously, and realize the device with the interface compatibility of existing apparatus.
Fig. 1 show according to an embodiment the block scheme of the general SPI device of content configuration of teaching.General SPI device 10 is shown to have general SPI logic 8, have provide in general SPI logic 8 outside and by multiple electric contact (being described below) from the received multiple input and output signals of the device of general SPI logic 8 outside.General SPI logic 8 comprises and has two latchs be connected in series, the shift register portion of latch 12 and latch 14.Each latch 12 and latch 14 comprise data input (being appointed as " D "), latch enable input (is appointed as
), clock input (being appointed as " > ") and data output (being appointed as " Q ").Latch 12 and latch 14 are electrically coupled together, so that the data of latch 12 export the data input D that Q (being appointed as signal 11) is provided as latch 14.Each latch 12 and latch 14
be connected in together and be appointed as the input signal of signal 3 from the external reception of latch 12 and latch 14.When signal 3 is low, latch 12 and latch 14 are activated, and by response to be applied to > input clock signal and be applied to its separately data input D data-signal.When signal 3 is high, latch 12 and latch 14 non-response in > input and the data-signal being applied to respective data input D, and can not change its separately data export the state of Q.Together with each latch 12 is connected in the > signal of latch 14, and link the clock source being appointed as signal 5 of latch 12 and latch 14 outside.When signal 3 is when clock signal 5 rising edge is low, latch 12 and latch 14 are enabled, and each latch 12 and latch 14 clock signal 5 rising edge by be present at signal 5 rising edge its value that data export D separately count (clock into) himself, and export Q at it this value be provided.When signal 3 is when clock signal 5 rising edge is high, each latch 12 and latch 14 can not change the value provided in its Q output.Should be appreciated that, because the output Q of latch 12 is provided as the input D of latch 14, each latch 12 and latch 14 are enabled and timing, the input value that the output valve of latch 12 will be latch 14.In fact, had each clock, the data be stored in latch 12 are passed to latch 14, and new data (the data input D from latch 12 outside at latch 12 is provided, and is also referred to as signal 1) is stored in latch 12.By this way, latch 12 and latch 14 serve as shift register, from the outside shifted data position of latch 12 to latch 12, then arrive latch 14.Should be appreciated that, although in the present embodiment, only have 2 latchs, latch 12 and latch 14, therefore, only have 2 be stored and be shifted, added latch be added to serially the centre of latch 12 and latch 14 or its on, to be stored by shift register portion more than 2 and to be shifted.
General SPI logic 8 also comprises and has two latchs, reflection (shadow) the register portion of latch 16 and latch 18.Each latch 16 and latch 18 comprise data input (being appointed as " D "), clock input (being appointed as " > ") and data and export (being appointed as " Q ").The clock source being appointed as signal 7 of latch 16 and latch 18 outside is linked together with each latch 16 is connected in the > signal of latch 18.The value being present in its data input D separately during signal 7 rising edge is counted himself at the rising edge of clock signal 7 by each latch 16 and latch 18, and exports Q at it and provide this value.As shown in the figure, the data input D of latch 16 is electrically coupled to data output Q (being appointed as signal 11) of latch 12.Also as shown in the figure, the data input D of latch 18 is electrically coupled to data output Q (being appointed as signal 13) of latch 14.Should be appreciated that, each clock signal 7 has rising edge, the data value be stored in latch 12 will be latched to latch 16 and as its export QN (being appointed as signal 17) be provided, and the data be stored in latch 14 will be latched to latch 18 and as its output Q0 (being appointed as signal 19) be provided.Should also be clear that the data being present in output terminal QN and Q0 respectively will maintain (not changing), until the rising edge of clock signal 7 next time.By this way, be not received at signal 7 at supposition rising edge, after the value of latch 12 and latch 14 has changed for a long time, provided by latch 12 and latch 14 and the data counting latch 14 and latch 18 can be maintained at and export QN and Q0.Latch 12 just described above and latch 14, should be appreciated that, although in the present embodiment, only have 2 latchs, latch 16 and latch 18 serve as image register, therefore, only have 2 to be stored as output and are shifted, added latch can be added to shift register portion as the added latch beyond latch 12 and latch 14, can be stored more than 2 and be provided as output.
General SPI logic 8 also comprises and has latch, the delay time register portion of latch 20.Latch 20 comprises data input (being appointed as " D "), clock input (being appointed as " > ") and data and exports (being appointed as " Q ").The > signal of each latch 20 is connected in together and links the clock source of latch 20 outside, and is connected to and is supplied to latch 12 with latch 14 and is designated as the identical clock signal of signal 5.Latch 20 clock signal 5 negative edge by be present in during signal 5 negative edge its separately data input D value count himself, and its export Q this value is provided.As shown in the figure, the data input D of latch 20 is electrically coupled to data output Q (being appointed as signal 13) of latch 14.Should be appreciated that, each clock signal 5 has negative edge, and the data value be stored in latch 14 will be latched to latch 20 and export Q (being appointed as signal 15) as it and be provided.Should also be clear that because, latch 20 is in the negative edge timing data of clock signal 5, and the data of latch 14 in rising edge timing.Latch 20 has and keeps and provide the effect of the identical output data of latch 14 as exporting, but is delayed half clock period from the output at latch 14 is provided.
General SPI logic 8 also comprises three-state buffer, three-state buffer 22 and three-state buffer 24.The input of three-state buffer 22 is electrically coupled to data output D (signal 13) of latch 14.Three-state buffer 22 also comprises output, and it is configured in high impedance status, or exports at it and be provided in its input (signal 13) identical signal of providing as output signal 21.Three-state buffer 22 is also configured to reception control signal (specification signal 9) to determine that whether three-state buffer 22 exports at it identical signal providing and receive as its input (signal 13), or whether its output enters high impedance status.The input of three-state buffer 24 is electrically coupled to data output D (signal 15) of latch 20.Three-state buffer 24 also comprises the output being configured in high impedance status, or exports at it and be provided in its input (signal 15) identical signal of providing as output signal 23.Three-state buffer 24 is also configured to reception control signal (specification signal 9) to determine that whether three-state buffer 24 exports at it identical signal providing and receive in its input (signal 15), or whether its output enters high impedance status.Should be appreciated that, when control signal 9 is low, three-state buffer 22 exports D as its output signal 21 (signals 13) using providing these data of latch 14, and three-state buffer 24 exports D (signal 15) as its output signal 21 using providing these data of latch 20, it is identical with signal 13, but is delayed half clock period.
As mentioned above, general SPI device 10 is shown to have multiple electric contact being electrically coupled to the circuit of general SPI logic 8.More particularly, general SPI device 10 comprise the data input D that is electrically coupled to latch 12 electric contact 30 (being also referred to as SDI), be electrically coupled to latch 12 and latch 14
electric contact 32 (being also referred to as SSB) and be electrically coupled to the > input of latch 12, latch 12 and latch 14 electric contact 34 (being also referred to as SCLK), be electrically coupled to the electric contact 36 (being also referred to as RCLK) of the > input of latch 16 and latch 18 and be electrically coupled to the electric contact 38 (being also referred to as SDOEB-serial data output enable impact damper) of control inputs of three-state buffer 22 and three-state buffer 24.Should be appreciated that, signal 1, signal 3, signal 5, signal 7 and signal 9 are supplied to general SPI device 10 respectively by electric contact 30, electric contact 32, electric contact 34, electric contact 36 and electric contact 38 from external source.The electric contact 42 (being also referred to as Q0) that general SPI device 10 also comprises electric contact 40 (being also referred to as QN) that the data being electrically coupled to latch 16 export Q, the data that are electrically coupled to latch 18 export Q, be electrically coupled to the electric contact 44 (being also referred to as SDO) of the output of three-state buffer 22 and be electrically coupled to the electric contact 46 (being also referred to as the serial data that SDOD-postpones to export) of output of three-state buffer 24.Should be appreciated that, signal 17, signal 19, signal 21 and signal 23 are provided in general SPI device 10 outside respectively by electric contact 40, electric contact 42, electric contact 44 and electric contact 46.
In general operation, in response to SSB signal (this makes shift register portion in response to clock signal shifted data) and SCLK clock signal, input at the SDI of general SPI device 10 data provided and moved into general SPI device 10 by turn.The data moving into shift register export based on RCLK signal can obtain at the QN to Q0 of general SPI device 10, and are kept in these outputs in response to RCLK signal.Along with new data is moved into general SPI device 10, legacy data (in order) is moved out of general SPI device 10 (unless these outputs are placed in high impedance state by SDOEB signal) in SDO and SDOD output based on FIFO, wherein SDOD exports and exports identical with SDO, but is delayed half SCLK cycle.
Fig. 2 A shows the block scheme of the general SPI device of the Fig. 1 configured in spi modes.For the purpose of clear, the interior details of general SPI logic 8 omits from this figure, and it is identical to be considered to Fig. 1 general remark.In fig. 2, general SPI device 10 is coupled in standard spi bus, RCLK, SSB, and SDOEB input is all connected in together and is coupled in SSB (subordinate selector bar) signal provided by spi bus main frame.SCLK and SDI is also provided by spi bus main frame.Finally, spi bus SDO line is electrically coupled to the SDOD output of general SPI device 10.Fig. 2 B shows the representative sequential chart of the general SPI device of Fig. 2 A.Together with reference to Fig. 2 A and Fig. 2 B, the operation of general SPI device 10 will be described.When SSB is high, general SPI device 10 have ignored SDI (data) signal and SCLK (clock) signal (occurring without data clock), and SDO with SDOD output is tri-state (high impedance-device is not put into communicating in bus).As long as SSB step-down, SDO output becomes active, and exports the value (although this value is not positioned on spi bus, because SDO line is not connected to spi bus in this configuration) in last shift register.And when SSB is low, is timed at SCLK rising edge new data and passes through shift register from SDI to SDO.This new data was delayed by the clock period before being provided to spi bus, provided because the SDOD that it is SDO by being electrically coupled to spi bus exports (serial data of delay exports).At the rising edge of SSB, the content of shift register is counted into image register, and appears at Q output (not being connected in this configuration).Should be appreciated that, in this configuration, (general SPI device 10 RCLK, SSB and SDOEB line is connected together and links spi bus SSB as shown in Figure 2 A and 2B, general SPI device 10 SDI line is linked spi bus SDI line, and general SPI device 10 SDOD line is linked spi bus SDO line), general SPI device 10 operates with the pattern completely compatible with SPI, and does not need accessory logic circuit.Should also be clear that because the SSB input of general SPI device 10 is coupled in the SSB signal of spi bus, this system improves immunity to interference.This is because when SSB is high, any pulse on SCLK will be left in the basket, and not change the content of shift register.Any pulse on SSB line can cause the content of shift register to be latched to image register, but during owing to being high as SSB, the content of shift register does not change, and the Q of image register exports does not have actual change.In addition, should be appreciated that, serial data exports in the system of the larger timing margin of (SDO and/or SDOD) device needs that will connect wherein, and this system board designer Selection utilization SDO output instead of SDOD pin may provide larger timing margin.
Fig. 3 A shows with the block scheme of the general SPI device of Fig. 1 of DSA pattern configurations.For the purpose of clear, the interior details of general SPI logic 8 omits from this figure, and it is identical to be considered to Fig. 1 general remark.In figure 3 a, general SPI device 10 is similar to SPI by use but the DSA and traditional that the universal serial bus incompatible with SPI is arranged in system operates, latch enable (LE) signal of DSA universal serial bus is electrically coupled to the RCLK input of general SPI device 10, and SSB and SDOEB pin is connected to ground.The SDI input of general SPI device 10 is electrically coupled to the sdi signal of DSA universal serial bus.Fig. 3 B shows the representative sequential chart of the general SPI device of Fig. 3 A.Together with reference to Fig. 1 and Fig. 3 A and Fig. 3 B, the operation of general SPI device 10 will be described.Due to SSB be connected to (low), the latch in shift register is always enabled, and new data will by SDI input be counted into latch at each SCLK rising edge.As long as LE is low, is counted into general SPI device 10 and can not image register be counted into from SDI input by the new data of shift register on the rising edge of each SCLK, and can not occur as output QN and Q0.When rising edge occurs on LE, the content of shift register contributes to image register from shift register, and is provided as output Q0 and QN, and is accessible by electric contact 40 and electric contact 42 in general SPI device 10 outside.By this way, when general SPI device 10 is configured to shown in Fig. 3 A, general SPI device 10 is compatible with non-SPI DSA universal serial bus.
It should be noted that many DSA devices do not provide SDO pin in its bus interface portion, this makes the content of the impossible read shift register of designer.Should be appreciated that, by using the embodiment being configured to the Fig. 1 shown in 3, board design personnel may be provided to the connection of SDO and/or SDOD pin with the value and/or the scan chain connecting test that allow application program to read internal shift register.
The block scheme of the general SPI device of Fig. 1 that the DSA pattern (being similar to Fig. 3 A) that Fig. 4 A shows to have improvement immunity to interference configures.For the purpose of clear, the interior details of general SPI logic 8 omits from this figure, and be considered to usually to illustrate with Fig. 1 identical.In the configuration of Fig. 4 A, general SPI device 10 is similar to SPI but the universal serial bus incompatible with SPI is arranged to the DSA and traditional that having in system improve immunity to interference operates by using.Fig. 4 A to be configured in everyway identical with the configuration of Fig. 3 A, the RCLK input that latch enable (LE) signal except DSA universal serial bus is electrically coupled to general SPI device 10 inputs with the SSB of general SPI device 10 (instead of SSB as in Fig. 3 A with being connected to).Fig. 4 B shows the representative sequential chart of the general SPI device of Fig. 4 A.Together with reference to Fig. 1 and Fig. 4 A and Fig. 4 B, the operation of general SPI device 10 is identical with the operation in Fig. 3 A, except in this configuration, SSB is connected to latch enable (LE) signal, when latch enable (LE) is for time low, new data is only counted latch at each SCLK rising edge by the latch in shift register.When device not accessed (determine as LE signal, only access this device when LE is low), improve immunity to interference by preventing shift register from moving into new data.In order to provide this additional immunity to interference, LE signal always must remain on height by universal serial bus main device, except when bus main device is attempted new data to be loaded into general SPI device 10 (and LE is low clearly certainly).
Fig. 5 A shows with the block scheme of the general SPI device of Fig. 1 of shift register mode configuration.For the purpose of clear, the interior details of general SPI logic 8 omits from this figure, and it is identical to be considered to Fig. 1 general remark.In fig. 5, latch enable (LE) signal of bus is electrically coupled to the RCLK input of general SPI device 10, and SSB and SDOEB pin is connected to ground.The SDI input of general SPI device 10 is electrically coupled to the sdi signal of bus.Fig. 5 B shows the representative sequential chart of the general SPI device of Fig. 5 A.Together with reference to Fig. 1 and Fig. 5 A and Fig. 5 B, the operation of general SPI device 10 will be described.Due to SSB be connected to (low), the latch in shift register is always enabled, and new data will each SCLK rising edge by SDI input be counted into latch.As long as LE is low, is counted into general SPI device 10 and can not image register be counted into from SDI input by the new data of shift register at the rising edge of each SCLK, and can not occur as output QN and Q0.When rising edge occurs on LE, the content of shift register contributes to image register from shift register, and be provided as output Q0 and QN, and be accessible by electric contact 40 and electric contact 42 (being SDO and SDOD respectively) in general SPI device 10 outside.If application program is the application program that SDO signal is updated on bus SCLK signal rising edge, the SDO signal of general SPI device 10 can be utilized.Needing to improve in the application program of timing, SDOD (the SDO signal of delay) also may be utilized.
Fig. 6 A shows the block scheme of the general SPI device of the Fig. 1 with the shift register mode configuration improving immunity to interference.For the purpose of clear, the interior details of general SPI logic 8 omits from this figure, and it is identical to be considered to Fig. 1 general remark.Fig. 6 A to be configured in everyway identical with the configuration of Fig. 5 A, the RCLK input that latch enable (LE) signal except bus is electrically coupled to general SPI device 10 inputs with the SSB of general SPI device 10 (instead of SSB as in Fig. 5 A with being connected to).Fig. 6 B shows the representative sequential chart of the general SPI device of Fig. 6 A.Together with reference to Fig. 1 and Fig. 6 A and Fig. 6 B, the operation of general SPI device 10 is identical with the operation in Fig. 5 A, except in this configuration, SSB is connected to latch enable (LE) signal, when latch enable (LE) is for time low, new data is only counted latch at each SCLK rising edge by the latch in shift register.When device not accessed (as LE signal is determined, only accessing this device when LE is low), improve immunity to interference by preventing shift register from moving into new data.In order to provide this additional immunity to interference, LE signal always must remain on height by universal serial bus main device, except when bus main device is attempted new data to be loaded into general SPI device 10 (and LE is low clearly certainly).Should be appreciated that, relating in the system being connected multiple shift registers of connecting with multiple Different L E, this configuration may be infeasible.
Fig. 7 show according to alternate embodiment the block scheme of the general SPI device of content configuration of teaching.General SPI device 90 is shown to have general SPI logic 92, have provide in general SPI logic 92 outside and by multiple electric contact (being described below) from the received multiple input and output signals of the device of general SPI logic 92 outside.General SPI device 90 and general SPI logic 92 are similar to general SPI device 10 and general SPI logic 8, except three-state buffer 22 and three-state buffer 24 be multiplexed device 50 and three-state buffer 52 substitute, and electric contact 44 (SDO) and electric contact 46 (SDOD) substitute by single electric contact 48 (SDO).In addition, the new electric contact 48 being called as SDOSEL (SDO selection) is provided.
In the present embodiment, export D with the data of its latch 14 and be provided to three-state buffer 22 as input, also when three-state buffer 22 is not tri-state (see Fig. 1), output also as three-state buffer 22 is provided by electric contact 44, and the data of latch 14 export D and are provided to multiplexer 50 as the first input (signal 13).And, the data being electrically coupled to latch 20 with the data input of its three-state buffer 24 export D (signal 15), also when three-state buffer 24 is not tri-state (see Fig. 1), output as three-state buffer 24 is provided by electric contact 46, and the data of latch 20 export D and are provided to multiplexer 50 as the second input (signal 15).Multiplexer 50 be electrically coupled to electric contact 48 and be configured to receive select signal 25 (SDOSEL) using the first input (signal 13) and second being determined to multiplexer 50 input in (signal 15) which the output as multiplexer 50 is provided.M50 is also coupled in three-state buffer 52.Three-state buffer 52 is configured to output (signal 13 or signal 15) the conduct input receiving multiplexer 50.Three-state buffer 52 also comprises output and is configured to high impedance status, or exports at it and be provided in its input (signal 13 or signal 15) identical signal of providing as output signal 29.Three-state buffer 52 is also configured to reception control signal (specification signal 9) and is called as SDOEB (serial data output enable impact damper) to determine that whether three-state buffer 52 exports at it identical signal providing and receive in its input (signal 13 or signal 15), or whether its output enters high impedance status.The input of three-state buffer 24 is electrically coupled to data output D (signal 15) of latch 20.Should be appreciated that, when signal 25 selects the output of signal 13 as multiplexer 50, multiplexer 50 will provide signal 13 to three-state buffer 52, and when signal 9 is low, signal 13 also will be provided as output signal 29 by electric contact 48 by three-state buffer 52.When signal 25 selects the output of signal 15 as multiplexer 50, multiplexer 50 will provide signal 15 to three-state buffer 52, and when signal 9 is low, signal 15 also will be provided as output signal 29 by electric contact 48 by three-state buffer 52.By this way, according to the value of SDOSEL (signal 25) and SDOEB (signal 9), three-state buffer 52 will provide SDO or SDOD signal at electric contact 48.In fact, this alternate embodiment allows by using multiplexer to eliminate electric contact that SDO or SDOD signal is individual in which will be provided as output to select.
Should be appreciated that, in alternative embodiments, power on signal state can be used to force the Q of general SPI device 10 to output to known predefined state.In other alternate embodiment, reset signal can be provided to known predefined state when displacement and image register being reset to startup.In addition, the input of attached Parallel interface and selection pin can be provided to contribute to operating under parallel bus environment.In other alternate embodiment, general SPI device 10 may be implemented as a part for the integrated circuit also with other functional block, processor, storer, logic and interface circuit.In another alternate embodiment, general SPI device 10 may be implemented as independently integrated circuit.
In alternate embodiment (not shown), usually all component shown in Fig. 1 with Fig. 7 can together with on single substrate formed and integrally device be provided.In another alternate embodiment (not shown), usually can be coupled in single module at all component shown in Fig. 1 and Fig. 7.In another alternate embodiment, usually can be implemented in fuse, in other logic or in the treatment circuit being configured or programming to generate signal at the signal generated by assembly shown in Fig. 1 and Fig. 7, and signal can be connected by the difference outside with more or less pin and provide.
Embodiment described in the invention provide can with the general SPI interface of various processor, microcontroller and other function i ntegration, and allow these products and existing ready-made microcontroller, RF and other device and have employed serial to use together with the system of other bus.These embodiments provide to be implemented and various parallel and serial line interface neatly, comprises SPI, built-in compatibility, and do not need the space increasing cost, complicacy and additional interface logical requirements.There is provided the product of built-in and each multiple bus protocol compatibility to provide can be easy to the added benefit dropped into by these products in existing design, and no matter existing bus protocol how, and without the need to redesigning or changing main circuit plate.
On the one hand, general SPI interface is provided, without the need to additional interface logical OR software, with spi bus, existing DSA and make use of the other products that has and be similar to the interface of (but incompatible) SPI and the universal serial bus of agreement and require and 74xx164 type signal to send compatible parallel bus mutually compatible.On the other hand, provide the general SPI interface reducing number of pins, it provide identical general-purpose interface, but use less outside output pin.This general SPI interface can be configured in different modes (having dissimilar bus, interface and agreement) work, and this depends on how the input of general SPI interface arrangement is configured, and which signal input is connected to.Therefore, provide the design object the dirigibility of raising existing system design use simultaneously that achieve and keep low cost, and realize the device with existing apparatus interface compatibility.
Although describe in detail and describe the preferred embodiments of the present invention, clearly for those skilled in the art, when not departing from the present invention's spirit or appended claims, can make various amendment described by above-mentioned.
Claims (20)
1. a USB interface device, comprising:
First latch, comprises the first data input, clock input, latch enable input and the first data and exports; Described first latch is configured to: when enable signal is present in the input of described latch enable, is present in the data in described first data input and in described first data output, provides this data in response to the signal provided the input of described clock;
Second latch, the second data input that described first data that latch enable inputs, the second data export and be electrically coupled to described first latch comprise clock input, being electrically coupled to the described latch enable input of described first latch export, described second latch is configured to: when enable signal is present in the input of described latch enable, in response to the signal provided the input of described clock, being present in the data in described second data input and exporting in described second data provides this data; And
3rd latch, comprise clock input, the 3rd data input that described second data that 3rd data exported and be electrically coupled to described second latch export, described 3rd latch is configured to the signal in response to providing the input of described clock, be present in the data in described 3rd data input and export in described 3rd data and this data are provided, wherein export in described 3rd data the data that provide and export the data that provide by time delay relative to described second data at described second latch, and wherein said first latch, second latch is electrically coupled to share identical clock signal with the clock input of the 3rd latch.
2. USB interface device according to claim 1, also comprise the first impact damper, the first buffer data that described first impact damper comprises the described second data output that the first buffer data exports, the first buffer control inputs and be electrically coupled to described second latch inputs, wherein said first impact damper is configured to, in response to the signal being present in described first buffer control input, export the data providing described second data being present in described second latch to export at described first buffer data.
3. USB interface device according to claim 2, also comprise the second impact damper, the second buffer data that described second impact damper comprises the described 3rd data output that the second buffer data exports, the second buffer control inputs and be electrically coupled to described 3rd latch inputs, wherein said second impact damper is configured to, in response to the signal being present in described second buffer control input, export the data providing described 3rd data being present in described 3rd latch to export at described 3rd buffer data.
4. USB interface device according to claim 1, also comprise the second impact damper, the second buffer data that described second impact damper comprises the described 3rd data output that the second buffer data exports, the second buffer control inputs and be electrically coupled to described 3rd latch inputs, wherein said second impact damper is configured to, in response to the signal being present in described second buffer control input, export the data providing described 3rd data being present in described 3rd latch to export at described 3rd buffer data.
5. USB interface device device according to claim 1, also comprise the 4th reflection latch, the 4th data input that described first data that described 4th reflection latch comprises clock input, the 4th data export and be electrically coupled to described first latch export, described 4th reflection latch is configured to the signal provided in response to the described clock input at described 4th reflection latch, is present in the data of described 4th data input and provides this data in described 4th data output.
6. USB interface device according to claim 1, also comprise multiplexer, described multiplexer has selects input, the first multiplexer input that described second data being electrically coupled to described second latch export, the second multiplexer input that described 3rd data being electrically coupled to described 3rd latch export and multiplexer export, wherein said multiplexer is configured to Ying Yu and is present in the described signal selecting input, the data providing and be present in described first multiplexer input and the data being present in described second multiplexer input are exported at described multiplexer.
7. USB interface device according to claim 5, also comprise the 5th reflection latch, the 5th data input that described second data that clock inputs, the 5th data export and be electrically coupled to described second latch that described 5th reflection latch comprises the described clock input being electrically coupled to described 4th reflection latch export, described 5th reflection latch is configured to the signal in response to being provided in the input of described clock, and being present in the data in described 5th data input and exporting in described 5th data provides this data.
8. USB interface device according to claim 3, also comprises:
4th reflection latch, the 4th data input that described first data that described 4th reflection latch comprises clock input, the 4th data export and be electrically coupled to described first latch export, described 4th reflection latch is configured to the signal in response to providing the input of described clock, and being present in the data in described 4th data input and exporting in described 4th data provides this data; And
5th reflection latch, the 5th data input that described second data that clock inputs, the 5th data export and be electrically coupled to described second latch that described 5th reflection latch comprises the described clock input being electrically coupled to described 4th reflection latch export, described 5th reflection latch is configured to the signal in response to providing the input of described clock, and being present in the data in described 5th data input and exporting in described 5th data provides this data.
9. USB interface device according to claim 3, also comprise and there is SSB, SCLK, the spi bus of SDI and SDO signal, the described latch enable input of wherein said first and second latchs and the buffer control input of described first and second impact dampers are electrically coupled together and are electrically coupled to the described SSB signal of described spi bus, wherein said first latch, the described clock signal of the second latch and the 3rd latch is electrically coupled together and is electrically coupled to the described SCLK signal of described spi bus, the described first data input of wherein said first latch is electrically coupled to the described sdi signal of described spi bus, and wherein said second impact damper exports the described SDO signal being electrically coupled to described spi bus.
10. USB interface device according to claim 3, also comprise and there is SDI, the universal serial bus of SCLK and LE signal, the described latch enable input of wherein said first and second latchs and the buffer control input of described first and second impact dampers are electrically coupled together and are electrically coupled to ground, wherein said first latch, the described clock signal of the second latch and the 3rd latch is electrically coupled together and is electrically coupled to the described SCLK signal of described universal serial bus, the described first data input of wherein said first latch is electrically coupled to the described sdi signal of described universal serial bus, and at least one during wherein said first impact damper output and described second impact damper export is electrically coupled to the described SDO signal of described universal serial bus.
11. USB interface devices according to claim 3, also comprise and there is SDI, the universal serial bus of SCLK and LE signal, the described buffer control input of wherein said first and second impact dampers is electrically coupled to ground, the described latch enable input of wherein said first and second latchs and the described clock input of described reflection latch are electrically coupled together and are electrically coupled to the described LE signal of described universal serial bus, wherein said first latch, second latch, the described clock signal of the 3rd latch is electrically coupled together and is electrically coupled to the described SCLK signal of described universal serial bus, and the described first data input of wherein said first latch is electrically coupled to the described sdi signal of described universal serial bus, wherein said first impact damper exports and at least one in described second impact damper output is electrically coupled to the described SDO signal of described universal serial bus, and wherein said LE signal is except when new data is maintained at logic high state when the described data input of described first latch is provided to described USB interface device.
12. USB interface devices according to claim 8, also comprise and there is SDI, the parallel bus of SCLK and LE signal, the described enable input of wherein said first and second latchs and the buffer control input of described first and second impact dampers are electrically coupled together and are electrically coupled to ground, the described clock input of wherein said reflection latch is electrically coupled together and is electrically coupled to the described LE signal of described parallel bus, wherein said first latch, second latch, the described clock signal of the 3rd latch is electrically coupled together and is electrically coupled to the described SCLK signal of described parallel bus, the described first data input of wherein said first latch is electrically coupled to the described sdi signal of described parallel bus, and wherein said first reflection latch data is defeated and described second at least one of videoing in latch data output is electrically coupled to described parallel bus.
13. USB interface devices according to claim 8, also comprise and there is SDI, the parallel bus of SCLK and LE signal, the described buffer control input of wherein said first and second impact dampers is electrically coupled to ground, the described latch enable input of wherein said first and second latchs and the described clock input of described reflection latch are electrically coupled together and are electrically coupled to the described LE signal of described parallel bus, wherein said first latch, second latch, the described clock signal of the 3rd latch is electrically coupled together and is electrically coupled to the described SCLK signal of described parallel bus, the described first data input of wherein said first latch is electrically coupled to the described sdi signal of described parallel bus, wherein said first reflection latch data exports and described second at least one of videoing in latch data output is electrically coupled to described parallel bus, and wherein said LE signal is except when new data is maintained at logic high state when the described data input of described first latch is provided to described USB interface device.
14. 1 kinds of USB interface devices, comprising:
Shift circuit, has enable input SSB, clock input SCLK, shift circuit input SDI and shift circuit and exports, and is configured to receive data at shift circuit input SDI and export at shift circuit provide data;
Delay circuit, there is the clock input SCLK that delay circuit inputs, delay circuit exports and be electrically coupled to the input of described shift circuit clock being electrically coupled at least one shift circuit and exporting, wherein said delay circuit is configured to export to receive data and export at described delay circuit from least one shift circuit of described shift circuit provide this data, and the data wherein provided on described delay circuit exports are delayed by time relative to exporting at described shift circuit the data provided;
There is enable input SDOEB, be electrically coupled to the buffer circuit that data input and data export that described shift circuit exports and delay circuit exports; And
There is clock input RCLK, be electrically coupled to the reflection circuit of the data input of described shift circuit output and data output; Wherein when RCLK, SSB and SDOEB input be electrically coupled together, SCLK is electrically coupled to clock signal and SDI is electrically coupled to data-signal time, described USB (universal serial bus) is configured to operate in spi modes, and wherein when described SDOEB signal be electrically coupled to ground, SCLK be electrically coupled to clock signal and SDI be electrically coupled to data-signal time, described USB (universal serial bus) is configured to operate with at least one in DSA and shift register mode.
15. USB interface devices according to claim 6, also comprise the first impact damper, described first impact damper comprises the first buffer data output, the first buffer control input and is electrically coupled to the first buffer data input of described multiplexer output, wherein said first impact damper is configured to, in response to the signal being present in described first buffer control input, export the data providing and be present in described multiplexer and export at described first buffer data.
16. USB interface devices according to claim 6, also comprise:
4th reflection latch, the 4th data input that described first data that described 4th reflection latch comprises clock input, the 4th data export and be electrically coupled to described first latch export, described 4th reflection latch is configured to the signal in response to providing the input of described clock, is present in the data of described 4th data input and provides this data in described 4th data output; And
5th reflection latch, the 5th data input that described second data that clock inputs, the 5th data export and be electrically coupled to described second latch that described 5th reflection latch comprises the described clock input being electrically coupled to described 4th reflection latch export, described 5th reflection latch is configured to the signal in response to providing the input of described clock, and being present in the data in described 5th data input and exporting in described 5th data provides this data.
17. USB interface devices according to claim 15, also comprise:
4th reflection latch, the 4th data input that described first data that described 4th reflection latch comprises clock input, the 4th data export and be electrically coupled to described first latch export, described 4th reflection latch is configured to the signal in response to providing the input of described clock, and being present in the data in described 4th data input and exporting in described 4th data provides this data; And
5th reflection latch, the 5th data input that described second data that clock inputs, the 5th data export and be electrically coupled to described second latch that described 5th reflection latch comprises the described clock input being electrically coupled to described 4th reflection latch export, described 5th reflection latch is configured to the signal in response to providing the input of described clock, and being present in the data in described 5th data input and exporting in described 5th data provides this data.
18. 1 kinds of USB interface devices, comprising:
Serial shift register, be configured to store at least the first and second data bit and there is data input, enable input, clock input and the first and second shift register outputs, described first and second shift register outputs are configured to provide the output of corresponding first and second data bit as exporting described first and second, described serial shift register is configured to the enable and clock signal in response to being applied to described enable input and clock input, the data being applied to the input of described data are input to described first register from described data, and from described first register to the displacement in order of described second register, and
Delay time register, be configured to storage data bit and there is enable input, clock inputs, delay time register exports and is electrically coupled to the delay time register input that described second of described serial shift register exports, wherein said delay time register is configured to the signal in response to providing the input of described clock, be present in the data of described delay time register input and provide this data in described delay time register output, the described data wherein provided on described delay time register exports are delayed by time relative to exporting at described second of described serial shift register the data provided, and wherein said serial shift register is electrically coupled to share identical clock signal with the described clock input of delay time register.
19. USB interface devices according to claim 18, also comprise and be configured to store at least one data bit and there is at least one data input being electrically coupled in described first shift register output and described second shift register output at least one, clock input and at least one be configured to be provided in data that described at least one data input provides as the image register output exported, described image register is configured to input in response to described clock, the data being applied to described at least one data input are displaced to described image register from described data input, and exporting at least one data described provides these data as output.
20. USB interface devices according to claim 19, also comprise at least one comprise buffer data export, buffer control input and be electrically coupled to described serial shift register or delay time register at least one export buffer data input impact damper, wherein said impact damper is configured to, in response to the signal being present in described first buffer control input, export the described data providing and be present in the input of described buffer data or high impedance at described buffer data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/023,781 US9658971B2 (en) | 2013-09-11 | 2013-09-11 | Universal SPI (serial peripheral interface) |
| US14/023,781 | 2013-09-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104424154A true CN104424154A (en) | 2015-03-18 |
| CN104424154B CN104424154B (en) | 2019-09-10 |
Family
ID=51542142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410404682.2A Active CN104424154B (en) | 2013-09-11 | 2014-08-18 | General serial peripheral interface |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US9658971B2 (en) |
| EP (1) | EP2849079B1 (en) |
| CN (1) | CN104424154B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109075886A (en) * | 2016-03-30 | 2018-12-21 | 华为技术有限公司 | Exempt to interfere multiplexer |
| CN111666245A (en) * | 2019-03-08 | 2020-09-15 | 亚德诺半导体国际无限责任公司 | Multi-chip programming of phased arrays |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9904644B2 (en) * | 2013-10-09 | 2018-02-27 | Goodrich Corporation | Systems and methods of using an SPI controller |
| GB2539445A (en) * | 2015-06-16 | 2016-12-21 | Nordic Semiconductor Asa | Data processing |
| US20170017584A1 (en) * | 2015-07-15 | 2017-01-19 | Microchip Technology Incorporated | SPI Interface With Less-Than-8-Bit Bytes And Variable Packet Size |
| US9858213B2 (en) * | 2015-12-14 | 2018-01-02 | Afero, Inc. | Interface and method for efficient communication between a microcontroller and a communication module |
| US10880116B2 (en) * | 2016-07-28 | 2020-12-29 | Skyworks Solutions, Inc. | Multi mode interface and detection circuit |
| US10324889B2 (en) * | 2016-08-07 | 2019-06-18 | Demand Peripherals, Inc. | System and method to tolerate ringing on a serial data bus |
| JP2018092690A (en) * | 2016-11-30 | 2018-06-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor integrated system |
| WO2019112088A1 (en) * | 2017-12-07 | 2019-06-13 | 주식회사 로보티즈 | Universal input/output interface device and method for controlling same |
| FR3115149B1 (en) * | 2020-10-09 | 2024-02-23 | St Microelectronics Grenoble 2 | Memory device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7499519B1 (en) * | 2007-12-12 | 2009-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bidirectional shift register |
| CN102750975A (en) * | 2005-09-30 | 2012-10-24 | 莫塞德技术公司 | Daisy chain cascading devices |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2327579B (en) | 1997-07-22 | 2000-06-07 | Motorola Israel Ltd | Apparatus for controlling of data transportation and a method |
| US7082481B2 (en) * | 2003-11-25 | 2006-07-25 | Atmel Corporation | Serial peripheral interface (SPI) apparatus with write buffer for improving data throughput |
| US7434084B1 (en) | 2005-03-10 | 2008-10-07 | Cisco Technology, Inc. | Method and apparatus for eliminating sampling errors on a serial bus |
| US7788438B2 (en) | 2006-10-13 | 2010-08-31 | Macronix International Co., Ltd. | Multi-input/output serial peripheral interface and method for data transmission |
| CN101436170A (en) | 2007-11-12 | 2009-05-20 | 鸿富锦精密工业（深圳）有限公司 | SPI equipment communication circuit |
| US8135881B1 (en) | 2010-09-27 | 2012-03-13 | Skyworks Solutions, Inc. | Dynamically configurable serial data communication interface |
-
2013
- 2013-09-11 US US14/023,781 patent/US9658971B2/en active Active
-
2014
- 2014-08-18 CN CN201410404682.2A patent/CN104424154B/en active Active
- 2014-09-04 EP EP14183591.8A patent/EP2849079B1/en active Active
-
2017
- 2017-04-18 US US15/490,465 patent/US10318447B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102750975A (en) * | 2005-09-30 | 2012-10-24 | 莫塞德技术公司 | Daisy chain cascading devices |
| US7499519B1 (en) * | 2007-12-12 | 2009-03-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bidirectional shift register |
Non-Patent Citations (1)
| Title |
|---|
| TI: "《SN74AHC595-Q1 8-BIT SHIFT REGISTER WITH 3-STATE OUTPUT REGISTERS》", 31 January 2008, TEXAS INSTRUMENTS * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109075886A (en) * | 2016-03-30 | 2018-12-21 | 华为技术有限公司 | Exempt to interfere multiplexer |
| CN111666245A (en) * | 2019-03-08 | 2020-09-15 | 亚德诺半导体国际无限责任公司 | Multi-chip programming of phased arrays |
| CN111666245B (en) * | 2019-03-08 | 2023-08-18 | 亚德诺半导体国际无限责任公司 | Semiconductor device and SPI system |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2849079A1 (en) | 2015-03-18 |
| EP2849079B1 (en) | 2020-10-21 |
| US20170220519A1 (en) | 2017-08-03 |
| CN104424154B (en) | 2019-09-10 |
| US20150074319A1 (en) | 2015-03-12 |
| US9658971B2 (en) | 2017-05-23 |
| US10318447B2 (en) | 2019-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104424154A (en) | Universal Spi (serial Peripheral Interface) | |
| US6507214B1 (en) | Digital configurable macro architecture | |
| US6603330B1 (en) | Configuring digital functions in a digital configurable macro architecture | |
| US10817443B2 (en) | Configurable interface card | |
| US7779286B1 (en) | Design tool clock domain crossing management | |
| CN104050146B (en) | Micro control unit (MCU) chip | |
| CN109446145B (en) | Server mainboard I2C channel expansion chip, circuit and control method | |
| CN104156333A (en) | FPGA-based UART multi-interface extension system and method | |
| CN104239259B (en) | For the bridgt circuit to communicate with dynamic reconfigurable circuit | |
| CN107743621B (en) | Integrated circuit input and output | |
| CN103246628A (en) | SMI (Serial Management Interface) management method and programmable logic device | |
| US20050193178A1 (en) | Systems and methods for flexible extension of SAS expander ports | |
| EP2500827A2 (en) | Memory controller address and data pin multiplexing | |
| US10250419B2 (en) | Data transmission between asychronous environments | |
| US9594715B2 (en) | Integrated circuit devices, systems and methods having automatic configurable mapping of input and/or output data connections | |
| CN104572560A (en) | USB (universal serial bus) and ADC (analog to digital converter) interface multiplex circuit and multiplex method | |
| US9148155B1 (en) | Clock distribution architecture for integrated circuit | |
| CN114020669B (en) | CPLD-based I2C link system and server | |
| CN113032321B (en) | Address extension circuit, communication interface chip and communication system | |
| CN113033134B (en) | Trigger signal synchronization system between multi-service boards | |
| CN208580401U (en) | A kind of multiplexed port system based on SPI communication | |
| CN204189089U (en) | A kind of server | |
| CN110765057A (en) | Port multiplexing system based on SPI communication | |
| CN105760327A (en) | Internal bus of aerospace electronic product | |
| US20110316616A1 (en) | Semiconductor integrated circuit for controlling power supply |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: Texas in the United States Applicant after: NXP America Co Ltd Address before: Texas in the United States Applicant before: Fisical Semiconductor Inc. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |