CN104156333A - FPGA-based UART multi-interface extension system and method - Google Patents

Abstract

The invention provides an FPGA-based UART multi-interface extension system and method. FPGA-based UART multi-interface extension is achieved. Due to the fact that a polling method is adopted, serial devices lack priorities, priority processing cannot be carried out on data needing the higher priority, however, the requirement for a large number of serial devices is met, and more UARTs can be conveniently added as long as FPGA resources are enough. The system has the advantages of being compact and flexible, resources can be saved, the cost can be reduced, and the system is of great importance in practical application.

Description

A kind of many Interface Expandings of UART system and method based on FPGA

Technical field

The present invention relates to Interface Expanding field, relate in particular to a kind of many Interface Expandings of UART system and method based on FPGA.

Background technology

Along with the develop rapidly of electronic technology, it is more and more important that interfacing seems, many serial ports dynamic expansion and single parallel port/many serial ports full-duplex communication technology are also more and more extensive in the application in the field such as computer interface, Microprocessor Interface.What wherein, the exchanges data between the TT&C system taking single-chip microcomputer as core and host computer computing machine adopted conventionally is exactly serial communication mode.

Along with the development of embedded technology and the variation of embedded device, the multi-computer system being made up of embedded device has obtained significant progress, between multiple embedded devices, carries out data transmission with serial interface UART, forms complicated master-slave mode communication network.Universal asynchronous receiving-transmitting interface UART (UniversalAsynchronous Receiver/Transmitter) was born in for the 1970's, was widely used at present computing machine, communication, Industry Control, household electrical appliance, the every field such as consumer electronics.UART is first large scale integrated circuit, occurs several years ago just having produced UART at chip microprocessor, and current UART is compared with before 30 years, and structure is substantially similar.

As a kind of general serial data bus, UART is mainly used in asynchronous communication.This bus two-way communication, can realize full duplex transmission and reception.In embedded design, UART is used for communicating with PC, comprises and monitoring debugger and other device, as EEPROM communication.

UART has simple to operate, reliable operation, anti-interference strong, long transmission distance (composition 485 networks can transmit more than 1200 meters), designer generally believes that UART is the best mode of other parts transmission data from central processor CPU or microcontroller to system, and therefore they are applied in industry, communication, embedded and field of household appliances in large quantities.Because UART is easy to use, and can design by facilitating chip, the demand of UART is always very vigorous separately.

Up to now, in global range, have and exceed 40 kinds of UART devices and can select, but because multiple UART work and relate to inside sequential and the collaborative work processing of more complicated simultaneously, so current UART until today its versatility, pin, register still seldom change, can really realize the very few of Full Featured UART expansion.Most of UART devices are changed UART into application foundation with computer bus, ubiquity complicated operation, and pin is many, high in cost of production weakness.

In Embedded Application, microprocessor controller MCU and peripheral communication substantially all adopt serial ports, and most of microprocessor controller MCU are only with a serial ports, traditional serial ports expansion IC generally need to take the IO of a large amount of MCU, is not suitable for being applied in embedded system.

In actual applications, often running into a main process equipment need to connect various from machine equipment simultaneously, and main process equipment and often adopt UART communication interface from the communication mode between machine equipment, UART communication interface can only One-to-one communication, communication can not multiple communication interfaces connects together, implementation in the past: the 1. microprocessor of selecting to have multichannel UART communication interface in the time designing and developing main process equipment, and the model of microprocessor in fact with multichannel UART communication interface is fewer, bring the restriction on parts selection, and more expensive, increase cost of products, 2. adopt serial port extended chip to realize, as ST16C550, ST16C554, SP2538, MAX3110 etc., although cost is higher, the reliability of system is guaranteed, and is applicable to that data volume is large, the more system of serial ports demand, 3. adopt the method for timesharing switching by a serial ports expansion and multiple serial equipment communicating, the method cost of time-sharing multiplex is low, but is only applicable to the little occasion of data volume, and can only be by this single-chip microcomputer active and multiple devices communicating, and real-time is poor, 4. with the method extended serial port of software simulation, its advantage is that cost is low, real-time good, but need to take some CPU time.

Therefore, need to a kind of scheme that can effectively expand UART interface be proposed for the problems referred to above.

Summary of the invention

The object of the invention is to be achieved through the following technical solutions.

According to an embodiment of the invention, a kind of many Interface Expandings of UART system based on FPGA is provided, comprise single chip microcontroller, SFR bus, be arranged at a RAM and the 2nd RAM of FPGA inside, and system clock, it is characterized in that, the one RAM is set to send expansion module, and the 2nd RAM is set to receive expansion module, when microcontroller will be when the outside UART equipment sending data, by SFR bus, data are sent to the corresponding RAM of UART equipment that sends expansion module, re-send to UART external unit, described system clock is set to 1.

According to an embodiment of the invention, a described RAM and the 2nd RAM are set to first-in first-out (FIFO) buffer circle.

According to an embodiment of the invention, a described RAM and the 2nd RAM are set to 32B.

According to an embodiment of the invention, described transmission expansion module input signal comprises system master clock signal, UART equipment clock signal, SFR data bus output signal, SFR address bus signal and writes enable signal.

According to an embodiment of the invention, described transmission expansion module output signal comprises the data that export multiple UART equipment to.

According to another implementation of the invention, provide a kind of many Interface Expandings of UART method based on FPGA, comprise step:

(1) when single chip microcontroller will be when a certain UART equipment sending data by SFR bus, first according to SFR bus timing, when to write enable signal be high, and high 4 of SFR address bus signal is 1 o'clock entirely, the data of SFR data bus output signal is sent to the input of a RAM;

(2) judge which UART is data mail to, use a token to carry out poll between multiple UART equipment, determine that by token which UART equipment uses described the 2nd RAM, writes the space in the 2nd RAM that this UART equipment is corresponding data;

(3) again by the 2nd RAM sense data to output terminal, send to corresponding UART equipment.

Beneficial effect of the present invention is as follows:

The present invention has realized the many Interface Expandings of UART based on FPGA, owing to having adopted the method for poll, between serial equipment, lack priority, can not need to some the high priority data processing of high priority, but meet the requirement of a large amount of serial equipments, and as long as FPGA resource is enough, can add easily more UART.System has compactness, feature flexibly, can economize on resources again, reduces costs, and has in actual applications vital role.

Brief description of the drawings

By reading below detailed description of the preferred embodiment, various other advantage and benefits will become cheer and bright for those of ordinary skill in the art.Accompanying drawing is only for the object of preferred implementation is shown, and do not think limitation of the present invention.And in whole accompanying drawing, represent identical parts by identical reference symbol.In the accompanying drawings:

Accompanying drawing 1 shows many Interface Expandings of the UART system architecture schematic diagram based on FPGA according to embodiment of the present invention;

Accompanying drawing 2 shows many Interface Expandings of the UART method flow diagram based on FPGA according to an embodiment of the invention.

Embodiment

Illustrative embodiments of the present disclosure is described below with reference to accompanying drawings in more detail.Although shown illustrative embodiments of the present disclosure in accompanying drawing, but should be appreciated that and can realize the disclosure and the embodiment that should do not set forth limits here with various forms.On the contrary, it is in order more thoroughly to understand the disclosure that these embodiments are provided, and can be by the those skilled in the art that conveys to complete the scope of the present disclosure.

According to the embodiment of the present invention, provide a kind of many Interface Expandings of UART system based on FPGA, as shown in Figure 1, comprise single chip microcontroller, SFR bus, is arranged at a RAM and the 2nd RAM of FPGA inside and system clock.

The expansion of multiple UART realizes by two FPGA internal RAM, and these two RAM can be regarded as a bridge, and wherein a RAM is as sending expansion module, and the 2nd RAM is as receiving expansion module.When microcontroller will when the outside UART equipment sending data, by SFR bus, send to data the corresponding ram space of UART equipment that sends expansion module, re-send to UART external unit.One section of space of the corresponding RAM of each UART, for example the tx-ram-a space of the corresponding sending module RAM of uart-a.Use the same method, be provided with one and receive expanded mode block RAM.In design, single chip microcontroller and UART are the IP kernels that adopts Actel company to provide.So what system mainly needed realization is to send expansion module and receive expansion module.

In Design of Digital Circuit, general design is all to use same sequential, and all triggers are all to overturn under a clock, and such design is easy to process, and accuracy is also high.But when design and external interface, external clock and internal clocking are often asynchronous, namely have multiple clock zones, and output driving and the input sample of signal carry out under different sequential, so may just produce metastable state.Supposing the system clock is clk, and UART clock is uart-clk, and these two clocks might not be in full accord, and this just causes multiple clock zones, and output driving and the input sample of signal carry out under different sequential, so may just produce metastable state.In order to ensure the accuracy of data, must carry out clock correction or synchronous.If but adopt the method for proofreading and correct, each cycle will proofread and correct, and this has just greatly wasted system resource, so design employing is the method for clock synchronous, in expansion module, uses same clock uart-clk-r.

The expansion of multiple UART equipment in design, relates to multiple UART and uses same transmission expanded mode block RAM and receive expanded mode block RAM.Send or receive expansion RAM if only have a UART equipment to use within a time, can not compete, but having lost the meaning that UART expands.Send or receive expansion RAM if there are multiple UART to use, will compete so, therefore in design, using a token (uart-arb-cnt) poll between these 5 UART, deciding which UART equipment to use RAM by token.

Due to the expansion of many serial ports, data are easily lost, also in order to improve the utilization rate of CPU, so need to design buffer zone.In this system, use two transmitting-receiving RAM to carry out bridge joint, and they are designed to FIFO buffer circle, the independently transmitting-receiving annular fifo buffer size that each UART is corresponding is designed to 32B (can carry out as required size adjustment).Design file leader and the last person that two pointers point to respectively data, ensure that the data that newly deposit in can not cover the data that not yet obtain processing.Need to send data time, ready data are sent into Round Buffer Area, then taken out Data Concurrent by interrupt handling routine from Round Buffer Area and send.And in the time that interrupt handling routine receives the data that serial ports sends here, deposited in and receive Round Buffer Area, upper layer drivers just can be from these Round Buffer Area taking-up data.Usage counter determines that buffer zone is full or empty.

The function that will realize according to design, the main input/output signal that transmission expansion module needs is as follows:

Input signal:

Clk: system major clock;

Uart-clk:UART equipment clock;

The output of sfrdatao:SFR data bus;

Sfraddr:SFR address bus;

Sfrwe: write and enable.

Output signal:

The data of uart-in-a:UART equipment a;

The data of uart-in-b:UART equipment b;

The data of uart-in-c:UART equipment c;

The data of uart-in-d:UART equipment d;

The data of uart-in-e:UART equipment e.

Because adopting RAM, design realizes transmission expansion module, so very important work is exactly to realize the operation of the write and read of data under the effect of clock signal, control signal.

According to the embodiment of the present invention, also provide a kind of many Interface Expandings of UART method based on FPGA, as shown in Figure 2, comprise step:

(1) when single chip microcontroller will be when a certain UART equipment sending data by SFR bus, first be will be according to SFR bus timing, when sfrwe (write and enable) signal is high, and for " 1 ", (special function register because of the UART distributing is F8 to high 4 of sfraddr entirely, F9, FA, FB, FC, Gao Siwei is 1 entirely, indicate UART communication) time, the data of sfrdatao are sent to the input (the data input of RAM shares) of RAM.

(2) judge which UART is data mail to, use a token to carry out poll between multiple UART equipment, determine that by token which UART equipment uses described the 2nd RAM, writes data the space in RAM that this UART equipment is corresponding.Each UART equipment corresponding a fixed size in RAM, the space of position, the fixed size that this design is used is 32B.

(3) again by RAM sense data to output terminal uart-in-x (x represents a, b, c, d, e), send to corresponding UART equipment.The limited space of the corresponding RAM of each UART, therefore will constantly judge its capacity status.

The implementation method that receives expansion module and transmission expansion module is similar, and those skilled in the art can realize easily according to the description of aforementioned transmission expansion module, just repeat no more.

The above; only for preferably embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection domain of claim.

Claims (6)

1. many Interface Expandings of the UART system based on FPGA, comprise single chip microcontroller, SFR bus, be arranged at a RAM and the 2nd RAM of FPGA inside, and system clock, it is characterized in that, the one RAM is set to send expansion module, the 2nd RAM is set to receive expansion module, when microcontroller will when the outside UART equipment sending data, by SFR bus, send to data the corresponding RAM of UART equipment that sends expansion module, re-send to UART external unit, described system clock is set to 1.

2. the system as claimed in claim 1, a described RAM and the 2nd RAM are set to first-in first-out (FIFO) buffer circle.

3. the system as claimed in claim 1, a described RAM and the 2nd RAM are set to 32B.

4. the system as claimed in claim 1, described transmission expansion module input signal comprises system master clock signal, UART equipment clock signal, SFR data bus output signal, SFR address bus signal and writes enable signal.

5. the system as claimed in claim 1, described transmission expansion module output signal comprises the data that export multiple UART equipment to.

6. a method of carrying out Interface Expanding as many Interface Expandings of the UART system based on FPGA of claim 1-5 as described in one of them, comprises step:

(1) when single chip microcontroller will be when a certain UART equipment sending data by SFR bus, first according to SFR bus timing, when to write enable signal be high, and high 4 of SFR address bus signal is 1 o'clock entirely, the data of SFR data bus output signal is sent to the input of a RAM;

(2) judge which UART is data mail to, use a token to carry out poll between multiple UART equipment, determine that by token which UART equipment uses described the 2nd RAM, writes the space in the 2nd RAM that this UART equipment is corresponding data;

(3) again by the 2nd RAM sense data to output terminal, send to corresponding UART equipment.