CN110120922B - FPGA-based data interaction network management system and method - Google Patents
FPGA-based data interaction network management system and method Download PDFInfo
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- CN110120922B CN110120922B CN201910398813.3A CN201910398813A CN110120922B CN 110120922 B CN110120922 B CN 110120922B CN 201910398813 A CN201910398813 A CN 201910398813A CN 110120922 B CN110120922 B CN 110120922B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9005—Buffering arrangements using dynamic buffer space allocation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9026—Single buffer per packet
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
Abstract
The invention discloses a data interaction network management system and a method based on FPGA, the system of the invention comprises a DPRAM interface unit, a data handling unit, a pointer analyzing unit and N transceivers which are constructed based on FPGA, N is a positive integer which is more than or equal to 1; the DPRAM interface unit, the data handling unit and the pointer analyzing unit are in communication connection with each other, and the data handling unit is in communication connection with the transceiver; the system performs data interaction with an external DPRAM through a DPRAM interface unit, and realizes the data interaction with external hardware through a transceiver. The invention realizes the independence of the pointer and the data, the independence of the buffer area and the transceiver, simple and clear interaction interfaces among all functional modules, and the dynamic access to the DPRAM and the read-write operation are carried out according to the self state of the modules without depending on the control of a CPU. The flexibility of data receiving and sending is improved, and meanwhile, the consumption of the CPU running time by the communication task is reduced.
Description
Technical Field
The invention relates to the technical field of nuclear security level digital control, in particular to a data interaction network management system and method based on an FPGA (field programmable gate array).
Background
In a CPU + FPGA architecture system, the data interaction mode of a CPU and an FPGA is very important to the whole system. Since the CPU runs asynchronously with the FPGA, buffering is essential. In the design of the instrument control system of the nuclear power plant, a user can carry out configuration according to the requirement of the user, the realization of the configuration in a CPU is a very mature technology, but the FPGA is not mature at present, so the flexibility of interaction with the CPU needs to be fully considered in the FPGA design. The nuclear power plant instrument control system belongs to a safety-level product, a CPU has definite time limit on communication, the packet length of the communication is limited by considering the integrity of data in the communication, and meanwhile, the FPGA is limited by self resources and also has limitation on the packet length of the communication. Therefore, the FPGA needs to send communication data sent by the CPU in batches.
And managing an FPGA data buffer area of the CPU + FPGA architecture system. At present, a fixed-length transceiving method is generally adopted. The fixed-length transceiving requires that the FPGA firmware can support the maximum packet length in any application scenario, so it is often difficult to implement or resource-consuming with one FPGA firmware version.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a data interaction network management system and method based on an FPGA (field programmable gate array) for solving the problems; the invention adopts the way that the pointer and the data are independent and the buffer area and the transceiver are independent to carry out interaction. The invention can realize data transmission to the same destination address in batches in a CPU running period, dynamic allocation of the buffer area and data forwarding with low CPU occupation, thereby improving the flexibility of data receiving and transmitting and reducing the consumption of the communication task on the CPU running time.
The invention is realized by the following technical scheme:
a data interaction network management system based on FPGA comprises a DPRAM interface unit, a data handling unit, a pointer analyzing unit and N transceivers, wherein the DPRAM interface unit, the data handling unit, the pointer analyzing unit and the N transceivers are constructed based on FPGA, and N is a positive integer greater than or equal to 1; the DPRAM interface unit, the data handling unit and the pointer analyzing unit are in communication connection with each other, and the data handling unit is in communication connection with the transceiver; the system carries out data interaction with an external DPRAM through a DPRAM interface unit, realizes the data interaction with external hardware through a transceiver, and has no direct data interaction with a CPU.
Preferably, the DPRAM interface unit is configured to perform data interaction with an external DPRAM in local communication, so that a standard EMIF timing sequence and a local read-write timing sequence are converted with each other.
Preferably, the pointer analyzing unit obtains pointer data of each transceiver through the DPRAM interface unit, obtains status information of the corresponding transceiver according to a destination address of the pointer, and determines an operation of generating the read-write command according to the status information of the transceivers and the pointer.
Preferably, the transceivers are embedded in the respective channels, and provide an interactive interface with external hardware while taking charge of internal data communication, data synchronization and clock recovery.
Preferably, the system employs a polling mechanism, which is carried when there is prepared data and polls to the next transceiver for operation when there is no prepared data.
Preferably, a data buffer is provided in the data transfer unit.
Preferably, the data buffer area may be dynamically allocated, mapping between the data buffer area and the transceiver is performed according to the pointer information obtained by the pointer analyzing unit, so as to implement dynamic allocation of the data buffer area, and it is able to implement free switching between the receiving buffer area and the sending buffer area, where multiple buffer areas correspond to one transceiver and one buffer area corresponds to multiple transceivers.
Preferably, the external DPRAM comprises a pointer area and a data area; the pointer area comprises transceiver information, a data head address, data length and state information; the data area comprises 2 data receiving areas and 1 data sending area; the CPU only needs to write and update the state in the DPRAM, and the subsequent data forwarding carries out the mapping, the transportation and the long packet decomposition of the pointer and the data among all the module units of the system.
On the other hand, the invention also provides a data interaction network management method based on the FPGA, which comprises the following steps:
firstly, constructing an FPGA-based data interaction network management system according to any one of claims 1 to 8;
the pointer analyzing unit acquires pointer data of each transceiver through a DPRAM interface unit, acquires state information of the corresponding transceiver according to a destination address of the pointer, and judges and generates read-write command operation according to the state information of the transceivers and the pointer;
and step three, the data handling unit accesses the external DPRAM through the DPRAM interface unit according to the read-write control information given by the pointer analysis module, selectively controls the data flow direction, and completes data mapping, handling and long packet decomposition of each channel transceiver and the external DPRAM.
Preferably, in the method, a direct data interaction interface is not arranged between the FPGA and the CPU, the data issued by the CPU is not limited by the transmission condition of the FPGA any more, only the DPRAM is required to be operated, the data area and the state area are directly updated by new data, and the FPGA only needs to judge whether prepared data and states exist when operating one transceiver.
The invention has the following advantages and beneficial effects:
1. the invention is based on the mode that the pointer and the data are independent and the buffer area and the transceiver are independent to carry out interaction, can reduce the consumption of CPU operation time by data forwarding, can support larger data packet length, has low communication delay, and does not limit the whole issuing process to be blocked by the condition that the CPU issues data by the FPGA.
2. The interaction interfaces among the functional modules are simple and clear, and the DPRAM is dynamically accessed and read-write operated according to the self states of the modules without depending on the control of a CPU. Meanwhile, the method can realize the data sending and the buffer area dynamic allocation to the same destination address in batches in one CPU running period, thereby improving the flexibility of data receiving and sending and reducing the consumption of the CPU running time by communication tasks.
3. The invention can improve the data buffering capacity and reduce the resource overhead. In a system with high real-time requirement, the real-time performance of system communication can be ensured. In a system with various communication capacity requirements, the communication capacity of each port can be independently configured, and the requirement of the whole communication capacity does not need to be improved, so that the resource overhead is reduced. The method supports the use of single-port multi-buffer areas, namely, a specific port is subjected to multiple times of transceiving within one transmission period. The reliability and the efficiency of the nuclear security level DCS data communication can be effectively improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a schematic diagram of the system of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
The embodiment provides a data interaction network management system based on an FPGA, and as shown in fig. 1, the system includes a DPRAM interface unit, a data handling unit, a pointer parsing unit, and a transceiver, which are constructed based on the FPGA.
In this embodiment, the number of the transceivers is N, as shown in fig. 1. Wherein N is a positive integer greater than or equal to 1.
In this embodiment, the DPRAM interface unit, the data handling unit, and the pointer analyzing unit are connected in a pairwise communication manner, and the data handling unit is connected in a communication manner with the transceiver; as shown in fig. 1, the DPRAM interface unit, the data handling unit and the pointer parsing unit form a ring network, and the ring network and the N transceivers form a 1-to-N star network structure.
In this embodiment, the DPRAM interface unit is configured to perform data interaction with an external DPRAM locally, so that a standard EMIF timing sequence and a local read-write timing sequence are converted with each other.
In this embodiment, the ports are separated from the buffer, and the number of the ports and the buffer capacity of each port can be defined according to an application scenario; the invention constructs a star network structure, and adopts the fragmented polling transmission, thereby avoiding the communication delay increase of the whole system caused by the blockage of a communication interface by a port with large data volume.
In this embodiment, the pointer analyzing unit obtains pointer data of each transceiver through the DPRAM interface unit, obtains state information of the corresponding transceiver according to a destination address of the pointer, and determines an operation of generating a read-write command according to the state information of the transceiver and the pointer.
In this embodiment, the transceivers are embedded in each channel, and provide an interactive interface with external hardware, and are responsible for internal data communication, data synchronization, and clock recovery.
In this embodiment, the system performs data interaction with an external DPRAM through a DPRAM interface unit, and realizes data interaction with external hardware through a transceiver, and there is no direct data interaction between the system and the CPU.
In this embodiment, the system uses a polling mechanism, and when there is prepared data, the system carries the data, and when there is no prepared data, the system polls the next transceiver to operate.
In this embodiment, the data handling unit is provided with a data buffer.
In this embodiment, the data buffer area may be dynamically allocated, mapping between the data buffer area and the transceiver is performed according to the pointer information obtained by the pointer parsing unit, so as to implement dynamic allocation of the data buffer area, and enable free switching between the receiving buffer area and the sending buffer area, one transceiver corresponding to multiple buffer areas, and multiple transceivers corresponding to one buffer area.
In this embodiment, the external DPRAM includes a pointer area and a data area; the pointer area comprises configuration information such as transceiver information, a data head address, data length, state information and the like; the specific configuration information is shown in the following table:
| name (R) | Description of the preferred embodiment |
| PORT | Current communication channel type and slot information |
| Cycle | Data reception/transmission cycle |
| Ptr | Data receiving/transmitting buffer pointer (head address) |
| Len | Data receive/transmit buffer length |
| Status | Data receive/transmit buffer status |
| FSEQN | Frame sequence number in data receiving buffer |
| Link_Status | Communication link status |
The data area comprises 2 data receiving areas Bx _ Buf _ n _1 and Bx _ Buf _ n _2 and 1 data transmitting area Tx _ Buf _ n; wherein, two data receiving areas 1 both comprise a data area and a diagnosis area, and the data sending area only comprises the data area.
The CPU only needs to write and update the state in the DPRAM, and the subsequent data forwarding carries out mapping, carrying and long packet decomposition of pointers and data among all the module units of the system.
The method for interacting the pointer and the data independently and the buffer area and the transceiver independently by the FPGA-based data interaction network management system comprises the functions of pointer analysis, transceiving state updating, data transceiving and transceiver selection.
Pointer resolution essentially completes the mapping of the buffer and the transceiver. This function is implemented by the pointer resolution unit.
The receiving and sending state updating mainly completes the updating of a data sending state and a data receiving state, wherein the data receiving state updating comprises a data writing state, a data writing completion state, a data reading state and a data reading completion state. The CPU only needs to write and update the state in the DPRAM.
Data transceiving is mainly used for completing data transportation work of data from a buffer area to a transceiver and from the transceiver to the buffer area.
The transceiver selects the data flow direction according to the mapping relation between the buffer and the transceiver.
In the embodiment, the functional units are mutually independent, and the interaction between data does not depend on the period of a CPU (central processing unit), so that the consumption of the CPU operation period by data forwarding is greatly reduced; for the forwarding of the long data packet, the CPU only needs to write and update the state in the DPRAM, the subsequent data forwarding only needs to carry out mapping and carrying of pointers and data among all modules of the system and decomposition of the long packet, a polling mechanism is adopted among all channels in the star network structure, prepared data is carried, and if the data is not carried, polling is carried to the next channel for operation, so that the communication delay is effectively reduced. By adopting the star-shaped network structure, a direct data interaction interface does not exist between the FPGA and the CPU, the CPU sends data without being limited by the sending condition of the FPGA, only the DPRAM is needed to be operated, the data area and the state area are directly updated by new data, and the FPGA only needs to judge whether prepared data and states exist when operating the channel.
In this embodiment, the network management system implements the following operations: 1) the DPRAM interface is responsible for local communication and interaction with an external DPRAM, so that the standard EMIF time sequence and the local read-write time sequence are converted with each other. 2) The pointer analysis part acquires pointer data of each configuration channel through a DPRAM interface, acquires state information of a corresponding channel according to a destination address of a pointer, and judges the operation of generating a read-write command by combining the channel and the state information of the pointer; 3) and the data carrying module accesses the data area, the state area, the address and the length information of the external DPRAM through the DPRAM interface according to the read-write control information given by the pointer analysis module, selectively controls the data flow direction, and completes data mapping, carrying, unpacking, processing and the like of each channel transceiver and the external DPRAM. 4) The transceiver module is embedded in each channel, that is, each operation channel comprises a transceiver, the transceiver provides an interactive interface with external hardware, and the transceiver is internally responsible for algorithm control of data communication data, data synchronization, clock recovery and the like.
By constructing the data interaction network management system architecture shown in fig. 1, pointer and data independence, buffer area and transceiver independence can be realized, interaction interfaces between the functional modules are simple and clear, and the DPRAM is dynamically accessed and read-write operation is performed according to the states of the modules, without depending on the control of a CPU. Meanwhile, the method can realize the data sending and buffer area dynamic allocation to the same destination address in batches in one CPU running period, thereby improving the flexibility of data receiving and sending and reducing the consumption of the CPU running time by the communication task.
Example 2
The embodiment provides a data interaction network management method based on an FPGA, which comprises the following steps:
step one, constructing a data interaction network management system based on the FPGA according to the embodiment 1;
the pointer analyzing unit acquires pointer data of each transceiver through a DPRAM interface unit, acquires state information of the corresponding transceiver according to a destination address of the pointer, and judges and generates read-write command operation according to the state information of the transceivers and the pointer;
and step three, the data handling unit accesses the external DPRAM through the DPRAM interface unit according to the read-write control information given by the pointer analysis module, selectively controls the data flow direction, and completes data mapping, handling and long packet decomposition of each channel transceiver and the external DPRAM.
In this embodiment, there is no direct data interaction interface between the FPGA and the CPU, the CPU issues data no longer limited by the FPGA transmission condition, the data area and the state area are directly updated with new data only by operating the DPRAM, and the FPGA only needs to judge whether there is prepared data and state when operating a certain transceiver.
In this embodiment, the pointer and the data are independent, and the buffer area and the transceiver are independent, and mapping between the data buffer area and the transceiver is performed according to the pointer information, so that dynamic allocation of the buffer area can be realized, and free switching between multiple buffer areas corresponding to one transceiver and multiple transceiver, multiple receiving/transmitting buffer areas corresponding to one buffer area, and multiple receiving/transmitting buffer areas and transmitting buffer areas can be realized. The method can realize data forwarding with low CPU occupation, buffer dynamic allocation and data transmission from batch to the same destination address in one CPU operation period, thereby improving the flexibility of data transceiving and reducing the consumption of the CPU operation time by communication tasks.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A data interaction network management system based on FPGA is characterized by comprising a DPRAM interface unit, a data handling unit, a pointer analyzing unit and N transceivers, wherein the DPRAM interface unit, the data handling unit, the pointer analyzing unit and the N transceivers are constructed based on FPGA, and N is a positive integer greater than or equal to 1; the DPRAM interface unit, the data handling unit and the pointer analyzing unit are in communication connection with each other, and the data handling unit is in communication connection with the transceiver; the system carries out data interaction with an external DPRAM through a DPRAM interface unit, realizes the data interaction with external hardware through a transceiver, and has no direct data interaction with a CPU;
the pointer analysis unit acquires pointer data of each transceiver through the DPRAM interface unit, acquires state information of the corresponding transceiver according to a destination address of the pointer, and judges the operation of generating a read-write command by combining the state information of the transceivers and the pointer;
and the data carrying unit accesses the external DPRAM through the DPRAM interface unit according to the read-write command information given by the pointer analysis unit, selectively controls the data flow direction, and finishes data mapping, carrying and long packet decomposition of the transceivers of all channels and the external DPRAM.
2. The FPGA-based data interaction network management system as claimed in claim 1, wherein the DPRAM interface unit is used for local communication and data interaction with an external DPRAM, so that a standard EMIF time sequence and a local read-write time sequence are converted with each other.
3. The FPGA-based data interaction network management system of claim 1, wherein the transceivers are embedded in the channels, and provide an interaction interface with external hardware and are responsible for internal data communication, data synchronization and clock recovery.
4. An FPGA-based data interaction network management system according to any one of claims 1-3, wherein the system employs a polling mechanism, wherein the system is configured to perform a transport when there is prepared data and to poll a next transceiver for operation when there is no prepared data.
5. The FPGA-based data interaction network management system of claim 4, wherein a data buffer is provided in the data handling unit.
6. The FPGA-based data interaction network management system of claim 5, wherein the data buffer is dynamically allocated, mapping between the data buffer and the transceiver is performed according to the pointer information obtained by the pointer parsing unit, so as to realize dynamic allocation of the data buffer, free switching between the receiving buffer and the sending buffer is realized, and multiple buffers correspond to one transceiver and one buffer corresponds to multiple transceivers.
7. The FPGA-based data interaction network management system of any one of claims 1-3, wherein the external DPRAM comprises a pointer area and a data area; the pointer area comprises transceiver information, a data head address, data length and state information; the data area comprises 2 data receiving areas and 1 data sending area; the CPU only needs to write and update the state in the DPRAM, and the subsequent data forwarding carries out mapping, carrying and long packet decomposition of pointers and data among all the module units of the system.
8. The FPGA-based data interaction network management system as defined in any one of claims 1 to 3, wherein a direct data interaction interface is not provided between the FPGA and the CPU, the data issued by the CPU is not limited by the transmission condition of the FPGA any more, only the DPRAM is required to be operated, the data area and the state area are directly updated with new data, and the FPGA only needs to judge whether prepared data and state exist when operating a certain transceiver.
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