CN104239232A - Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) - Google Patents
Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention relates to a Ping-Pong cache operation structure based on a DPRAM (Dual Port Random Access Memory) in an FPGA (Field Programmable Gate Array), which is used for receiving a frame of data and reading a frame of complete data to realize the cache of the frame of data. The Ping-Pong cache operation structure based on the DPRAM in the FPGA comprises a writing operation control module, a reading operation control module and a DPRAM module. By judging the highest bit of a writing address of the DPRAM, an address space of the DPRAM is divided into a low address space and a high address space, and Ping-Pong cache operation is completed in one DPRAM; under the situation that an externally input reading control signal exists, the highest bit of the writing address is used for generating a judgment signal of a reading address; under the situation that the externally input reading control signal does not exist, cache data is automatically read. The Ping-Pong cache operation structure based on the DPRAM in the FPGA avoids the disadvantages that the traditional Ping-Pong cache operation generates a principal DPRAM module and a standby DPRAM module, two groups of writing control logics and reading control logics of the DPRAM modules are generated and the consumed resources of the FPGA are greater.
Description
Technical field
The present invention relates to a kind of ping-pong buffer operating structure based on DPRAM in FPGA, belong to signal processing technology field.
Background technology
FPGA is used for data processing, and wherein ping-pong buffer operation is the most basic operation.BlockRAM is the basic unit of storage of FPGA, DPRAM module on the basis of BlockRAM, increases steering logic produce, produced by FPGA design tool, manually can not intervene, it is increase to read steering logic and write control logic generation on the basis of DPRAM module that ping-pong buffer operates.The operation of DPRAM ping-pong buffer is made up of BlockRAM unit, BlockRAM steering logic, DPRAM Read-write Catrol logic.
At present, as shown in Figure 5 and Figure 6, traditional operation of the ping-pong buffer based on DPRAM in FPGA generally uses main part and backup two DPRAM modules, for active and standby ping-pong operation, does existence so significantly not enough;
1, because produce main part DPRAM module, backup DPRAM module, so 2 groups of BlockRAM steering logics can be produced, BlockRAM steering logic resource use amount is caused to increase;
2, in FPGA, the address space of BlockRAM is generally 1024 (18bit*1K),
When a frame buffer data less (being less than 512), one frame data also will use a BlockRAM unit to store, and such ping-pong buffer operation produces main part DPRAM, backup DPRAM, produce 2 BlockRAM unit, cause BlockRAM unit use amount to increase by 1 times;
When a frame buffer data comparatively large (being greater than 2048), one frame data need use 2 and above BlockRAM unit to store, such ping-pong buffer operation produces main part DPRAM, backup DPRAM, produce 4 and above BlockRAM unit, be unfavorable for that FPGA design tool uses BlockRAM block splicing optimisation technique.
3, ping-pong buffer operation comprises write control logic, reads steering logic, if produce main part write control logic, backup write control logic, main part read steering logic, steering logic is read in backup, and active and standby output data selection circuit, cause DPRAM Read-write Catrol logical resource use amount significantly to increase.Three kinds of DPRAM ping-pong buffers operate the fpga logic resource use amount comparison diagram that uses as shown in Figure 7, and when FPGA timing performance is identical, the present invention reduces logical resource relative to the operation of traditional DPRAM ping-pong buffer and reaches 50%.
Summary of the invention
The technical matters that the present invention solves is: overcome the deficiencies in the prior art, provide a kind of ping-pong buffer operating structure based on DPRAM in FPGA, the present invention completes ping-pong buffer operation in a DPRAM, the FPGA resource use amount reducing the use amount of BlockRAM unit, reduce the FPGA resource use amount of BlockRAM steering logic, reduce DPRAM Read-write Catrol logic.
Technical solution of the present invention is:
Based on a ping-pong buffer operating structure of DPRAM in FPGA, comprising: write operation control module, read operation control module, DPRAM module; What the present invention was operated in ping-pong buffer operation effectively writes data bandwidth when being less than or equal to valid reading according to bandwidth.
Write operation control module comprises write data register group, writes enable register, write address counter;
Write data register group deposits a Ge Sui road clock period to the cache data signals that outside inputs, and produces write data signal, and is input to DPRAM module;
Write enable register and one Ge Sui road clock period was deposited to the data cached effective marker position signal that outside inputs, produce write enable signal, and be input to write address counter, DPRAM module;
When there being the write control signal of outside input:
When the write control signal of outside input is effective, the negate of write address counter most significant digit, the address bit assignment ' 0 ' of write address counter except most significant digit, produces writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit equals threshold value time, write address counter is constant, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit is not equal to threshold value time, write address counter adds 1, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, and write enable invalid time, write address counter is constant, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit equals threshold value time, the first frame buffer settling signal becomes effectively, produces the first frame buffer settling signal, and is input to read address counter;
When the write control signal without outside input:
When write enable signal is effective, and the address bit of write address counter except most significant digit is when equaling threshold value, the negate of write address counter most significant digit, the address bit assignment ' 0 ' of write address counter except most significant digit, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is effective, and when the address bit of write address counter except most significant digit is not equal to threshold value, write address counter adds 1, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is invalid, write address counter is constant, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is effective, and the address bit of write address counter except most significant digit is when equaling threshold value, the first frame buffer settling signal becomes effectively, and the first frame buffer settling signal becomes effectively, produce the first frame buffer settling signal, and be input to read address counter;
Read operation control module adopts read address counter;
When there being the read control signal of outside input:
When the read control signal of outside input is effective, the first frame buffer settling signal is effective and write address most significant digit points to main part spatial cache, read address counter assignment is the initial address of backup spatial cache, address signal is read in generation, and is input to DPRAM module;
When the read control signal of outside input is effective, the first frame buffer settling signal is effective and write address most significant digit points to backup spatial cache, read address counter assignment is the initial address of main part spatial cache, address signal is read in generation, and is input to DPRAM module;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit equals threshold value, read address counter is constant, produces and reads address signal, and be input to DPRAM module;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit is not equal to threshold value, read address counter adds 1, produces and reads address signal, and be input to DPRAM module;
When the read control signal of outside input is effective, and when the first frame buffer settling signal is effective, read data effective marker position signal becomes effectively, produces read data effective marker position signal, and outputs to outside;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit equals threshold value, it is invalid that read data effective marker position signal becomes, and produces read data effective marker position signal, and output to outside;
When the read control signal without outside input:
When the first frame buffer settling signal is effective, and when the sensing of write address most significant digit becomes backup spatial cache from main part spatial cache, the initial address of the main part spatial cache of read address counter assignment, produces and reads address signal, and be input to DPRAM module;
When the first frame buffer settling signal is effective, and the sensing of write address most significant digit from back up spatial cache become main part spatial cache time, the initial address of read address counter assignment backup spatial cache, produces and reads address signal, and be input to DPRAM module;
When the address bit of read address counter except most significant digit equals threshold value, read address counter is constant, produces and reads address signal, and be input to DPRAM module;
When the address bit of read address counter except most significant digit is not equal to threshold value, read address counter adds 1, produces and reads address signal, and be input to DPRAM module;
When the first frame buffer settling signal is effective, and when the sensing of write address most significant digit becomes backup spatial cache from main part spatial cache, read data effective marker position signal becomes effectively, produces read data effective marker position signal, and outputs to outside;
When the first frame buffer settling signal is effective, and the sensing of write address most significant digit from back up spatial cache become main part spatial cache time, read data effective marker position signal becomes effectively, generation read data effective marker position signal, and outputs to outside;
When the address bit of read address counter except most significant digit equals threshold value, it is invalid that read data effective marker position signal becomes, and produces read data effective marker position signal, and output to outside;
Described main part spatial cache and backup spatial cache are that the write address most significant digit exported by write address counter carries out distinguishing, and main part spatial cache and backup spatial cache are all positioned at same DPRAM;
When write address most significant digit is ' 0 ', represent that write operation is at main part spatial cache; When write address most significant digit is ' 1 ', represent that write operation is at backup spatial cache;
The initial address of main part spatial cache is complete ' 0 ', and the initial address of backup spatial cache is " 100 ... 0 "; The address of main part spatial cache and the address of backup spatial cache represent can be contrary;
When there being the write control signal of outside input, the write control signal inputted by outside controls the switching of main part spatial cache and backup spatial cache; When without the outside write control signal inputted, controlled the switching of main part spatial cache and backup spatial cache by write address most significant digit signal;
The address signal of reading that described read operation control module outputs to DPRAM module exports to DPRAM module and reads to have between data that address stores 1 to read clock period or 2 to read the delay that clock period or 3 read the clock period, now carry out corresponding the delay to read data effective marker position signal and deposit.
The present invention also comprises and reads clock register; Write clock zone and read clock zone and can be the same or different; When the clock zone of write operation event is different from the clock zone of read operation event, reads clock register and at least twice is deposited to write address most significant digit signal, produce the write address most significant digit signal reading clock synchronous, and be input to read address counter; First frame buffer settling signal at least deposits twice with reading clock register, produces the first frame buffer settling signal reading clock synchronous, and is input to read address counter.
The present invention's advantage is compared with prior art:
(1) the present invention completes ping-pong buffer operation in a DPRAM, and when reducing the generation of DPRAM module, the steering logic resource use amount of BlockRAM, improve the work efficiency of FPGA, provide cost savings, practicality strengthens greatly.
(2) the present invention completes ping-pong buffer operation in a DPRAM, and when a frame buffer data is less than 512, BlockRAM unit use amount reduces by one times; When a frame buffer data is greater than 2048, facilitate FPGA design tool to use BlockRAM block splicing optimisation technique, thus reduce the use amount of BlockRAM unit, BlockRAM utilization ratio of storage resources nervous in FPGA has the raising of matter.
(3) the present invention adopts in a DPRAM, completes ping-pong buffer operation, reduce the write control logic of DPRAM outside, read the FPGA resource use amount of the DPRAM Read-write Catrol logic such as steering logic, active and standby output data selection logic, improve the work efficiency of FPGA, provide cost savings, practicality strengthens greatly.
Accompanying drawing explanation
Fig. 1 is module diagram of the present invention;
Fig. 2 be the present invention read clock zone identical with writing clock zone time structural representation;
Fig. 3 is that the present invention reads clock zone and writes the asynchronous structural representation of clock zone;
Fig. 4 is the BlockRAM block optimisation technique schematic diagram that the present invention realizes;
Fig. 5 is traditional DPRAM ping-pong buffer operating structure schematic diagram;
Fig. 6 is traditional DPRAM ping-pong buffer operating structure schematic diagram;
Fig. 7 is the effect contrast figure of three kinds of DPRAM ping-pong buffer operations.
Embodiment
Just by reference to the accompanying drawings the present invention is described further below.
As shown in Figure 1, 2, a kind of ping-pong buffer operating structure based on DPRAM in FPGA of the present invention, comprising: write operation control module, read operation control module, DPRAM module, read clock register; What work of the present invention was generally operational in ping-pong buffer operation effectively writes data bandwidth when being less than or equal to valid reading according to bandwidth.
Write data register group deposits a Ge Sui road clock period to the cache data signals that outside inputs, and produces write data signal, and is input to DPRAM module;
Write enable register and one Ge Sui road clock period was deposited to the data cached effective marker position signal that outside inputs, produce write enable signal, and be input to write address counter, DPRAM module;
Write operation control module comprises write data register group, writes enable register, write address counter;
When there being the write control signal of outside input:
When the write control signal of outside input is effective, the negate of write address counter most significant digit, the address bit assignment ' 0 ' of write address counter except most significant digit, produces writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, it is effectively enable to write, and the address bit of write address counter except most significant digit is when equaling threshold value, write address counter is constant, produces writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit is not equal to threshold value time, write address counter adds 1, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, and write enable invalid time, write address counter is constant, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit equals threshold value time, the first frame buffer settling signal becomes effectively, produces the first frame buffer settling signal, and is input to read address counter;
When the write control signal without outside input:
When write enable signal is effective, and the address bit of write address counter except most significant digit is when equaling threshold value, the negate of write address counter most significant digit, the address bit assignment ' 0 ' of write address counter except most significant digit, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is effective, and when the address bit of write address counter except most significant digit is not equal to threshold value, write address counter adds 1, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is invalid, write address counter is constant, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is effective, and the address bit of write address counter except most significant digit is when equaling threshold value, the first frame buffer settling signal becomes effectively, and the first frame buffer settling signal becomes effectively, produce the first frame buffer settling signal, and be input to read address counter;
Read operation control module adopts read address counter;
When there being the read control signal of outside input:
When the read control signal of outside input is effective, the first frame buffer settling signal is effective and write address most significant digit points to main part spatial cache, read address counter assignment is the initial address of backup spatial cache, address signal is read in generation, and is input to DPRAM module;
When the read control signal of outside input is effective, the first frame buffer settling signal is effective, and during write address most significant digit sensing backup spatial cache, read address counter assignment is the initial address of main part spatial cache, produces and reads address signal, and be input to DPRAM module;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit equals threshold value, read address counter is constant, produces and reads address signal, and be input to DPRAM module;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit is not equal to threshold value, read address counter adds 1, produces and reads address signal, and be input to DPRAM module;
When the read control signal of outside input is effective, and when the first frame buffer settling signal is effective, read data effective marker position signal becomes effectively, produces read data effective marker position signal, and outputs to outside;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit equals threshold value, it is invalid that read data effective marker position signal becomes, and produces read data effective marker position signal, and output to outside;
When the read control signal without outside input:
When the first frame buffer settling signal is effective, and when the sensing of write address most significant digit becomes backup spatial cache from main part spatial cache, the initial address of the main part spatial cache of read address counter assignment, produces and reads address signal, and be input to DPRAM module;
When the first frame buffer settling signal is effective, and the sensing of write address most significant digit from back up spatial cache become main part spatial cache time, the initial address of read address counter assignment backup spatial cache, produces and reads address signal, and be input to DPRAM module;
When the address bit of read address counter except most significant digit equals threshold value, read address counter is constant, produces and reads address signal, and be input to DPRAM module;
When the address bit of read address counter except most significant digit is not equal to threshold value, read address counter adds 1, produces and reads address signal, and be input to DPRAM module;
When the first frame buffer settling signal is effective, and when the sensing of write address most significant digit becomes backup spatial cache from main part spatial cache, read data effective marker position signal becomes effectively, produces read data effective marker position signal, and outputs to outside;
When the first frame buffer settling signal is effective, and the sensing of write address most significant digit from back up spatial cache become main part spatial cache time, read data effective marker position signal becomes effectively, generation read data effective marker position signal, and outputs to outside;
When the address bit of read address counter except most significant digit equals threshold value, it is invalid that read data effective marker position signal becomes, and produces read data effective marker position signal, and output to outside;
Main part spatial cache and backup spatial cache
Main part spatial cache and backup spatial cache are that the write address most significant digit exported by write address counter carries out distinguishing, and main part spatial cache and backup spatial cache are all positioned at same DPRAM;
When write address most significant digit is ' 0 ', represent that write operation is at main part spatial cache; When write address most significant digit is ' 1 ', represent that write operation is at backup spatial cache;
The initial address of main part spatial cache is complete ' 0 ', and the initial address of backup spatial cache is " 100 ... 0 "; The address of main part spatial cache and the address of backup spatial cache represent can be contrary;
When there being the write control signal of outside input, the write control signal inputted by outside controls the switching of main part spatial cache and backup spatial cache; When without the outside write control signal inputted, controlled the switching of main part spatial cache and backup spatial cache by write address most significant digit signal;
The address signal of reading that read operation control module outputs to DPRAM module exports to DPRAM module and reads to have between data that address stores 1 to read clock period or 2 to read the delay that clock period or 3 read the clock period, now carry out corresponding the delay to read data effective marker position signal and deposit.
As shown in Figure 3, this structure is also to comprise: read clock register; Write clock zone and read clock zone and can be the same or different.When the clock zone of write operation event is different from the clock zone of read operation event, reads clock register and at least twice is deposited to write address most significant digit signal, produce the write address most significant digit signal reading clock synchronous, and be input to read address counter; First frame buffer settling signal at least deposits twice with reading clock register, produces the first frame buffer settling signal reading clock synchronous, and is input to read address counter.Write operation event, is operated in and writes clock zone, is driven by the edge writing clock; Read operation event, is operated in and reads clock zone, is driven by the edge reading clock.
As shown in Figure 4, the present invention completes ping-pong buffer operation in a DPRAM, and when a frame buffer data is less than 512, BlockRAM unit use amount reduces by one times; When a frame buffer data is greater than 2048, facilitate FPGA design tool to use BlockRAM block splicing optimisation technique, thus reduce the use amount of BlockRAM unit, BlockRAM utilization ratio of storage resources nervous in FPGA has the raising of matter.
The non-detailed description of the present invention is known to the skilled person technology.
Claims (4)
1. based on a ping-pong buffer operating structure of DPRAM in FPGA, it is characterized in that comprising: write operation control module, read operation control module, DPRAM module;
Write operation control module comprises write data register group, writes enable register, write address counter;
Write data register group deposits a Ge Sui road clock period to the cache data signals that outside inputs, and produces write data signal, and is input to DPRAM module;
Write enable register and one Ge Sui road clock period was deposited to the data cached effective marker position signal that outside inputs, produce write enable signal, and be input to write address counter, DPRAM module;
When there being the write control signal of outside input:
When the write control signal of outside input is effective, the negate of write address counter most significant digit, the address bit assignment ' 0 ' of write address counter except most significant digit, produces writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit equals threshold value time, write address counter is constant, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit is not equal to threshold value time, write address counter adds 1, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, and write enable invalid time, write address counter is constant, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When the write control signal of outside input is invalid, write enable effectively and the address bit of write address counter except most significant digit equals threshold value time, the first frame buffer settling signal becomes effectively, produces the first frame buffer settling signal, and is input to read address counter;
When the write control signal without outside input:
When write enable signal is effective, and the address bit of write address counter except most significant digit is when equaling threshold value, the negate of write address counter most significant digit, the address bit assignment ' 0 ' of write address counter except most significant digit, produce writing address signal, and be input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is effective, and when the address bit of write address counter except most significant digit is not equal to threshold value, write address counter adds 1, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is invalid, write address counter is constant, produces writing address signal, and is input to DPRAM module, write address most significant digit signal is input to read address counter simultaneously;
When write enable signal is effective, and the address bit of write address counter except most significant digit is when equaling threshold value, the first frame buffer settling signal becomes effectively, and the first frame buffer settling signal becomes effectively, produce the first frame buffer settling signal, and be input to read address counter;
Read operation control module adopts read address counter;
When there being the read control signal of outside input:
When the read control signal of outside input is effective, the first frame buffer settling signal is effective and write address most significant digit points to main part spatial cache, read address counter assignment is the initial address of backup spatial cache, address signal is read in generation, and is input to DPRAM module;
When the read control signal of outside input is effective, the first frame buffer settling signal is effective and write address most significant digit points to backup spatial cache, read address counter assignment is the initial address of main part spatial cache, address signal is read in generation, and is input to DPRAM module;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit equals threshold value, read address counter is constant, produces and reads address signal, and be input to DPRAM module;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit is not equal to threshold value, read address counter adds 1, produces and reads address signal, and be input to DPRAM module;
When the read control signal of outside input is effective, and when the first frame buffer settling signal is effective, read data effective marker position signal becomes effectively, produces read data effective marker position signal, and outputs to outside;
When the read control signal of outside input is invalid, and when the address bit of read address counter except most significant digit equals threshold value, it is invalid that read data effective marker position signal becomes, and produces read data effective marker position signal, and output to outside;
When the read control signal without outside input:
When the first frame buffer settling signal is effective, and when the sensing of write address most significant digit becomes backup spatial cache from main part spatial cache, the initial address of the main part spatial cache of read address counter assignment, produces and reads address signal, and be input to DPRAM module;
When the first frame buffer settling signal is effective, and the sensing of write address most significant digit from back up spatial cache become main part spatial cache time, the initial address of read address counter assignment backup spatial cache, produces and reads address signal, and be input to DPRAM module;
When the address bit of read address counter except most significant digit equals threshold value, read address counter is constant, produces and reads address signal, and be input to DPRAM module;
When the address bit of read address counter except most significant digit is not equal to threshold value, read address counter adds 1, produces and reads address signal, and be input to DPRAM module;
When the first frame buffer settling signal is effective, and when the sensing of write address most significant digit becomes backup spatial cache from main part spatial cache, read data effective marker position signal becomes effectively, produces read data effective marker position signal, and outputs to outside;
When the first frame buffer settling signal is effective, and the sensing of write address most significant digit from back up spatial cache become main part spatial cache time, read data effective marker position signal becomes effectively, generation read data effective marker position signal, and outputs to outside;
When the address bit of read address counter except most significant digit equals threshold value, it is invalid that read data effective marker position signal becomes, and produces read data effective marker position signal, and output to outside.
2. a kind of ping-pong buffer operating structure based on DPRAM in FPGA according to claim 1, it is characterized in that: described main part spatial cache and backup spatial cache are that the write address most significant digit exported by write address counter carries out distinguishing, main part spatial cache and backup spatial cache are all positioned at same DPRAM;
When write address most significant digit is ' 0 ', represent that write operation is at main part spatial cache; When write address most significant digit is ' 1 ', represent that write operation is at backup spatial cache;
The initial address of main part spatial cache is complete ' 0 ', and the initial address of backup spatial cache is " 100 ... 0 "; The address of main part spatial cache and the address of backup spatial cache represent can be contrary;
When there being the write control signal of outside input, the write control signal inputted by outside controls the switching of main part spatial cache and backup spatial cache; When without the outside write control signal inputted, controlled the switching of main part spatial cache and backup spatial cache by write address most significant digit signal.
3. a kind of ping-pong buffer operating structure based on DPRAM in FPGA according to claim 1, it is characterized in that: the address signal of reading that described read operation control module outputs to DPRAM module exports to DPRAM module and reads to have between data that address stores 1 to read clock period or 2 to read the delay that clock period or 3 read the clock period, now carry out corresponding the delay to read data effective marker position signal and deposit.
4. a kind of ping-pong buffer operating structure based on DPRAM in FPGA according to claim 1, is further characterized in that and comprises: read clock register; Write clock zone and read clock zone and can be the same or different; When the clock zone of write operation event is different from the clock zone of read operation event, reads clock register and at least twice is deposited to write address most significant digit signal, produce the write address most significant digit signal reading clock synchronous, and be input to read address counter; First frame buffer settling signal at least deposits twice with reading clock register, produces the first frame buffer settling signal reading clock synchronous, and is input to read address counter.
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| CN110120922A (en) * | 2019-05-14 | 2019-08-13 | 中国核动力研究设计院 | A kind of data interaction Network Management System and method based on FPGA |
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| CN110120922B (en) * | 2019-05-14 | 2022-09-20 | 中核控制系统工程有限公司 | FPGA-based data interaction network management system and method |
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| CN114822385A (en) * | 2022-05-27 | 2022-07-29 | 中科芯集成电路有限公司 | Write protection circuit of LED display driving chip |
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