CN102789424B - External extended DDR2 (Double Data Rate 2) read-write method on basis of FPGA (Field Programmable Gate Array) and external extended DDR2 particle storage on basis of FPGA - Google Patents

External extended DDR2 (Double Data Rate 2) read-write method on basis of FPGA (Field Programmable Gate Array) and external extended DDR2 particle storage on basis of FPGA Download PDF

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CN102789424B
CN102789424B CN201210244513.8A CN201210244513A CN102789424B CN 102789424 B CN102789424 B CN 102789424B CN 201210244513 A CN201210244513 A CN 201210244513A CN 102789424 B CN102789424 B CN 102789424B
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ddr2
data
fpga
controller
read
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CN102789424A (en
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刘大同
彭宇
刘连胜
见其拓
刘川
庞业勇
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Harbin Nuoxin Measurement And Control Technology Co ltd
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Harbin Institute of Technology
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Abstract

The invention relates to an external extended DDR2 (Double Data Rate 2) read-write method on the basis of a FPGA (Field Programmable Gate Array) and an external extended DDR2 particle storage on the basis of the FPGA, and belongs to the field of storage media. The invention aims to solve the problem that an existing DDR2 data storage technology does not have the universality. According to the invention, massive data generated in the high-speed data acquisition, the high-speed communication and the digital signal processing is stored in a large-capacity DDR2 storage unit through processing and conversion by the FPGA and is read when a request is made; storage and read control signals are completed by a DDR2 control logic in the FPGA; when external devices or other logic modules in the FPGA make a read-write request, the DDR2 control logic converts request signals into control signals of DDR2 particles and carries out corresponding conversion on read-write data and addresses to exchange data with the DDR2; and a core part of the hardware design is the logic design inside the FPGA and the part is implemented by adopting a Verilog language.

Description

The reading/writing method that extends out DDR2 based on FPGA and extend out DDR2 particle storer based on FPGA
Technical field
The present invention relates to the reading/writing method that extends out DDR2 based on FPGA and based on FPGA extend out DDR2 particle storer, belong to field of storage mediums.
Background technology
DDR2 is as present utilization one of storage medium the most widely, its stability and overall performance all have more advantage than other storage mediums, but in the application such as high-speed data acquisition, communication and digital signal processing, still be there are to a lot of problems in the technology of DDR2 particle access by FPGA.
Conclude and sum up with regard to the DDR2 data storage technology existing at present, all have some problems, do not form mentality of designing unified, standard, though differ from one another, do not possess versatility.
Summary of the invention
The present invention seeks to not have in order to solve existing DDR2 data storage technology the problem of versatility, a kind of reading/writing method that extends out DDR2 based on FPGA is provided and has extended out DDR2 particle storer based on FPGA.
The reading/writing method that extends out DDR2 based on FPGA of the present invention, the equipment that the method relates to comprises FPGA and DDR2,
DDR2 steering logic module is set, the read-write operation of DDR2 steering logic module controls DDR2 in FPGA;
DDR2 steering logic module comprises WFIFO, RFIFO, DDR2 controller driver module and DDR2 controller,
The method comprises to be write step and reads step:
Writing step comprises the following steps:
In the time that WFIFO is idle, external logic is to the step of WFIFO data writing;
WFIFO completes after write operation, sends the step of zone bit to external logic;
In the time that DDR2 controller is idle, external logic sends and writes DDR2 request signal to DDR2 controller driver module, and sendaisle information, data allow the step of position, address and address significance bit simultaneously;
DDR2 controller driver module is write DDR2 request signal and passes to the step of DDR2 controller by this;
When DDR2 controller driver module receives after the request data signal that DDR2 controller returns, DDR2 controller driver module reads and in WFIFO, writes full data, and these data are stored in to the step in DDR2 by DDR2 controller;
Reading step comprises the following steps:
In the time that DDR2 controller is idle, external logic sends and reads DDR2 request signal to DDR2 controller driver module, sends the step of address, permission position, address and data permission position simultaneously;
DDR2 controller driver module is read DDR2 request signal and sends to the step of DDR2 controller by this;
DDR2 controller takes out data in appropriate address from DDR2, and data significance bit mark is set to effective step simultaneously;
Written request signal using data significance bit mark as RFIFO, writes the step in RFIFO by the data of taking out in DDR2;
Complete after the read operation of request number of times, external logic sends read request to RFIFO, the step of from RFIFO, data being exported.
Based on FPGA extend out DDR2 particle storer, it comprises FPGA and DDR2,
DDR2 steering logic module is set, the read-write operation of DDR2 steering logic module controls DDR2 in FPGA;
DDR2 steering logic module comprises WFIFO, RFIFO, DDR2 controller driver module and DDR2 controller,
WFIFO: under idle condition, allow external logic data writing; Complete under write operation state, send zone bit to external logic; Write the device that full data are read by DDR2 controller driver module;
RFIFO: for DDR2 controller driver module, for accepting the read request of external logic, by the device of the data output of reading from DDR2;
DDR2 controller driver module: write DDR2 request signal for what receive that external logic sends, be stored in the device in DDR2 by writing full data in WFIFO by DDR2 controller; Read DDR2 request signal for what receive that external logic sends, the data in appropriate address in DDR2 are write to the device of RFIFO;
DDR2 controller: the device of the conversion for decoding, data bit width and the address signal of control signal from single data speed pattern to Double Data Rate pattern, decoding, the generation of data mask and the generation of clock of address signal.
Advantage of the present invention: the present invention, for the large batch of data that produce in high-speed data acquisition, high speed communication and digital signal processing, by processing and the conversion of FPGA, is stored in jumbo DDR2 storage unit, and reads in the time filing a request.Storage and the control signal reading are completed by the DDR2 steering logic in FPGA, in the time that other logic modules in external devices or FPGA (general designation external logic) propose read-write requests, DDR2 steering logic module is converted to request signal the control signal of DDR2, and will read and write data and change accordingly with address, carry out exchanges data with DDR2.
DDR2 particle memory technology based on FPGA mainly should embody following functions:
1, high speed storing and reading out data;
2, jumbo storage medium;
3, interface operation is simple;
4, hyperchannel storage and reading;
5, stable.
Its beneficial effect is:
1. realize the data storage to several data width and read;
2. bits per inch is according to the highest support of line 200MHz/400Mbps communication speed;
3. storage or to read DDR2 simple to operate, without to DDR2 direct control;
4. support multi-channel data zero access;
5. high storage capacity can reach 9GB.
Brief description of the drawings
Fig. 1 is the logic diagram that extends out DDR2 particle storer based on FPGA of the present invention;
Fig. 2 is FPGA and DDR2 annexation schematic diagram;
Fig. 3 is DDR2 controller internal logic block diagram.
Embodiment
Embodiment one: below in conjunction with Fig. 1 to Fig. 3, present embodiment is described, the reading/writing method that extends out DDR2 based on FPGA described in present embodiment, the equipment that the method relates to comprises FPGA and DDR2,
DDR2 steering logic module 1 is set in FPGA, and DDR2 steering logic module 1 is controlled the read-write operation of DDR2;
DDR2 steering logic module 1 comprises WFIFO1-1, RFIFO1-2, DDR2 controller driver module 1-3 and DDR2 controller 1-4,
The method comprises to be write step and reads step:
Writing step comprises the following steps:
In the time that WFIFO1-1 is idle, external logic is to the step of WFIFO1-1 data writing;
WFIFO1-1 completes after write operation, sends the step of zone bit to external logic;
In the time that DDR2 controller 1-4 is idle, external logic sends and writes DDR2 request signal to DDR2 controller driver module 1-3, and sendaisle information, data allow the step of position, address and address significance bit simultaneously;
DDR2 controller driver module 1-3 writes DDR2 request signal and passes to the step of DDR2 controller 1-4 by this;
When DDR2 controller driver module 1-3 receives after the request data signal that DDR2 controller 1-4 returns, DDR2 controller driver module 1-3 reads and in WFIFO1-1, writes full data, and these data are stored in to the step in DDR2 by DDR2 controller 1-4;
Reading step comprises the following steps:
In the time that DDR2 controller 1-4 is idle, external logic sends and reads DDR2 request signal to DDR2 controller driver module 1-3, sends the step of address, permission position, address and data permission position simultaneously;
DDR2 controller driver module 1-3 reads DDR2 request signal and sends to the step of DDR2 controller 1-4 by this;
DDR2 controller 1-4 takes out data in appropriate address from DDR2, and data significance bit mark is set to effective step simultaneously;
Written request signal using data significance bit mark as RFIFO1-2, writes the step in RFIFO1-2 by the data of taking out in DDR2;
Complete after the read operation of request number of times, external logic sends read request to RFIFO1-2, the step of from RFIFO1-2, data being exported.
DDR2 adopts the DDR2 particle of BGA encapsulation to realize.
FPGA adopts the FPGA of the EP2SGX series of altera corp.
DDR2 controller 1-4 adopts the DDR2SDRAM Controller IP kernel of altera corp to realize.
Give concrete implementation procedure below:
When 1.WFIFO1-1 is empty, effectively, external logic can ask to write data to WFIFO1-1 to write_ready mark;
2. external logic sends and writes WFIFO request, completes writing after WFIFO number of operations of request, waits for;
3. complete and write after WFIFO operation, under DDR2 controller 1-4 idle condition, external logic can send the DDR2 request of writing to DDR2 controller driver module 1-3, and sendaisle information, data allow position (Byte enable) and address and address significance bit simultaneously.
4. for each effective write request, DDR2 controller 1-4 can return to a data request signal, and expression can data writing, the read request using this request signal as WFIFO1-1, and the data of reading in WFIFO1-1 are sent into DDR2.
5. in the time that DDR2 controller 1-4 is idle, external logic can propose to read the request of DDR2.
6.DDR2 controller driver module 1-3 receives read request, address and address and allows position and data to allow, behind position, the data in DDR2 appropriate address to be taken out, and data significance bit mark is set to effectively simultaneously.
7. the write request using data significance bit mark as RFIFO1-2, writes the data of taking out from DDR2 in RFIFO1-2.
8. complete after the read operation of respective request number of times, read_ready is set to effectively, and external logic can send read request to RFIFO1-2, from RFIFO1-2 by data reading.
Embodiment two: below in conjunction with Fig. 1 to Fig. 3, present embodiment is described, described in present embodiment based on FPGA extend out DDR2 particle storer, it comprises FPGA and DDR2,
DDR2 steering logic module 1 is set in FPGA, and DDR2 steering logic module 1 is controlled the read-write operation of DDR2;
DDR2 steering logic module 1 comprises WFIFO1-1, RFIFO1-2, DDR2 controller driver module 1-3 and DDR2 controller 1-4,
WFIFO1-1: under idle condition, allow external logic data writing; Complete under write operation state, send zone bit to external logic; Write the device that full data are read by DDR2 controller driver module 1-3;
RFIFO1-2: for DDR2 controller driver module 1-3, for accepting the read request of external logic, by the device of the data output of reading from DDR2;
DDR2 controller driver module 1-3: write DDR2 request signal for what receive that external logic sends, be stored in the device in DDR2 by writing full data in WFIFO1-1 by DDR2 controller 1-4; Read DDR2 request signal for what receive that external logic sends, the data in appropriate address in DDR2 are write to the device of RFIFO1-2;
DDR2 controller 1-4: the device of the conversion for decoding, data bit width and the address signal of control signal from single data speed pattern to Double Data Rate pattern, decoding, the generation of data mask and the generation of clock of address signal.
DDR2 adopts the DDR2 particle of BGA encapsulation to realize.
FPGA adopts the FPGA of the EP2SGX series of altera corp.
DDR2 controller 1-4 adopts the DDR2SDRAM Controller IP kernel of altera corp to realize.
The core of hardware design is the logical design of FPGA inside, and this part adopts Verilog language to realize, and mainly completes the generation of control signal, generation, the conversion of data bit width and the generation of clock of address signal.
The inner DDR2 steering logic of FPGA block diagram as shown in Figure 1, with 64bit data instance, illustrates the function of each parts:
1, WFIFO1-1 and RFIFO1-2 are asynchronous FIFO, mainly complete cross clock domain data buffer storage and data bit width conversion.When WFIFO1-1 is empty, external logic can data writing, writes the logics to be driven such as Man Hou and reads.RFIFO1-2 writes rear wait external logic and reads.
2, the function of DDR2 controller driver module 1-3 mainly contains: receive read-write requests, the management read-write state machine of external logic and operate for DDR2 controller provides the control signal that sequential is correct, generation and the address pointer of address signal.Be specially:
1) receive external logic request and management read-write state machine
WFIFO1-1 completes after write operation, send zone bit to external logic, send by external logic the DDR2 request of writing, described in receiving, DDR2 controller driver module 1-3 writes after DDR2 request, pass to DDR2 controller 1-4, wait for that DDR2 controller 1-4 provides the signal of request msg, DDR2 controller driver module 1-3 just produces the reading request signal of WFIFO1-1, and the data in WFIFO1-1 are sent to DDR2 controller 1-4.
DDR2 controller 1-4 is receiving after the read request of external logic and the signal of reading out data quantity, DDR2 controller driver module 1-3 sends to DDR2 controller 1-4 the DDR2 request of reading, DDR2 controller 1-4 provides data effective marker take out corresponding data from DDR2 time, DDR2 controller driver module 1-3 is converted to data effective marker the written request signal of RFIFO1-2, writes in RFIFO1-2.
2) operation of address pointer
The equal zero setting of the each passage read/write address of original state pointer, when a certain passage read or write, if address significance bit is effective, the address using the address signal of current input as read-write DDR2, is assigned to address pointer by current read/write address after a series of read-writes complete.If address significance bit is invalid, the value of address pointer is assigned to the read/write address of DDR2.
3) generation of address signal
Convert bank address, row address, column address to by address pointer or from the address signal of external logic input.
3, DDR2 controller 1-4
DDR2 controller 1-4 uses the DDR2SDRAM Controller IP kernel of altera corp to realize, and by the setting of the parameter to used FPGA and DDR2 and mode of operation, generates DDR2 controller module.The function of DDR2 controller has comprised the conversion from single data speed pattern to Double Data Rate pattern of decoding, data bit width and address signal, decoding, the generation of data mask and the generation of clock of address signal of control signal.Logic forms as shown in Figure 3.
DDR2 controller 1-4 is converted to the signal of read-write requests the control signal CAS/RAS/WE/CS of DDR2, directly controls DDR2.
The input data width of DDR2 controller 1-4 is 2 or 4 times of DDR2 data-bus width, because the read-write of DDR2 is Double Data Rate, clock rising and falling edges is is all read and write, and inner exchanging data clock is frequency (FULL) or its half (HALF) of DDR2 clock, the column address width of input also therefore and different.
DDR2 controller 1-4 is converted to bank address, row address and column address the address bus of N position, and address bus is that rank addresses is multiplexing, and bank address is independent.DDR2 controller 1-4 also allows position (Byte enable) to be converted to the data mask of DDR2 the data byte of external logic input.
PLL in DDR2 controller 1-4 produces the work clock of DDR2, generates the clock of DDR2 steering logic inside, the HALF/FULL model selection when ratio of clock frequency and DDR2 work clock is generated by IP kernel simultaneously.

Claims (6)

1. the reading/writing method that extends out DDR2 based on FPGA, the equipment that the method relates to comprises FPGA and DDR2,
DDR2 steering logic module (1) is set in FPGA, and DDR2 steering logic module (1) is controlled the read-write operation of DDR2;
DDR2 steering logic module (1) comprises WFIFO (1-1), RFIFO (1-2), DDR2 controller driver module (1-3) and DDR2 controller (1-4),
It is characterized in that, the method comprises to be write step and reads step:
Writing step comprises the following steps:
In the time that WFIFO (1-1) is idle, external logic is to the step of WFIFO (1-1) data writing;
WFIFO (1-1) completes after write operation, sends the step of zone bit to external logic;
In the time that DDR2 controller (1-4) is idle, external logic sends and writes DDR2 request signal to DDR2 controller driver module (1-3), and sendaisle information, data allow the step of position, address and address significance bit simultaneously;
DDR2 controller driver module (1-3) is write DDR2 request signal and passes to the step of DDR2 controller (1-4) by this;
When DDR2 controller driver module (1-3) receives after the request data signal that DDR2 controller (1-4) returns, DDR2 controller driver module (1-3) reads in WFIFO (1-1) and writes full data, and these data are stored in to the step in DDR2 by DDR2 controller (1-4);
Reading step comprises the following steps:
In the time that DDR2 controller (1-4) is idle, external logic sends and reads DDR2 request signal to DDR2 controller driver module (1-3), sends the step of address, permission position, address and data permission position simultaneously;
DDR2 controller driver module (1-3) is read DDR2 request signal and sends to the step of DDR2 controller (1-4) by this;
DDR2 controller (1-4) takes out data in appropriate address from DDR2, and data significance bit mark is set to effective step simultaneously;
Written request signal using data significance bit mark as RFIFO (1-2), writes the step in RFIFO (1-2) by the data of taking out in DDR2;
Complete after the read operation of request number of times, external logic sends read request to RFIFO (1-2), the step of from RFIFO (1-2), data being exported.
2. the reading/writing method that extends out DDR2 based on FPGA according to claim 1, is characterized in that, FPGA adopts the FPGA of the EP2SGX series of altera corp.
3. the reading/writing method that extends out DDR2 based on FPGA according to claim 1, is characterized in that, DDR2 controller (1-4) adopts the DDR2SDRAM Controller IP kernel of altera corp to realize.
Based on FPGA extend out DDR2 particle storer, it is characterized in that, it comprises FPGA and DDR2,
DDR2 steering logic module (1) is set in FPGA, and DDR2 steering logic module (1) is controlled the read-write operation of DDR2;
DDR2 steering logic module (1) comprises WFIFO (1-1), RFIFO (1-2), DDR2 controller driver module (1-3) and DDR2 controller (1-4),
WFIFO (1-1): under idle condition, allow external logic data writing; Complete under write operation state, send zone bit to external logic; Write the device that full data are read by DDR2 controller driver module (1-3);
RFIFO (1-2): for DDR2 controller driver module (1-3), for accepting the read request of external logic, by the device of the data output of reading from DDR2;
DDR2 controller driver module (1-3): write DDR2 request signal for what receive that external logic sends, be stored in the device in DDR2 by writing full data in WFIFO (1-1) by DDR2 controller (1-4); Read DDR2 request signal for what receive that external logic sends, the data in appropriate address in DDR2 are write to the device of RFIFO (1-2);
DDR2 controller (1-4): the device of the conversion for decoding, data bit width and the address signal of control signal from single data speed pattern to Double Data Rate pattern, decoding, the generation of data mask and the generation of clock of address signal.
According to claim 4 based on FPGA extend out DDR2 particle storer, it is characterized in that, FPGA adopts the FPGA of the EP2SGX series of altera corp.
According to claim 4 based on FPGA extend out DDR2 particle storer, it is characterized in that, DDR2 controller (1-4) adopts the DDR2SDRAM Controller IP kernel of altera corp to realize.
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Denomination of invention: The read and write method of external DDR2 based on FPGA and external DDR2 granular memory based on FPGA

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Denomination of invention: FPGA based read and write method for external expansion DDR2 and FPGA based external expansion DDR2 granular memory

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