CN104156907A - FPGA-based infrared preprocessing storage system and FPGA-based infrared preprocessing storage method - Google Patents
FPGA-based infrared preprocessing storage system and FPGA-based infrared preprocessing storage method Download PDFInfo
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- CN104156907A CN104156907A CN201410400589.4A CN201410400589A CN104156907A CN 104156907 A CN104156907 A CN 104156907A CN 201410400589 A CN201410400589 A CN 201410400589A CN 104156907 A CN104156907 A CN 104156907A
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Abstract
The invention provides an FPGA-based infrared preprocessing storage system and an FPGA-based infrared preprocessing storage method. The storage system comprises an FPGA module, an SDRAM module used for storing input and output signals, a signal input module used for receiving an input signal from a signal source and transmitting the input signal to the FPGA module, a signal output module used for receiving an output signal from the FPGA module and providing data flow for backend peripheral equipment, a USB module, a single chip microcomputer module, and a principal computer module. Based on an 'FPGA+MCU' architecture, the FPGA-based infrared preprocessing storage system uses an SDRAM as a cache. The FPGA is responsible for image signal transmission, the MCU is responsible for instruction parsing, task division is clear between the FPGA and the MCU, and the advantages of the FPGA and the MCU are fully utilized. The requirement for real-time image processing is fully met. No high-speed DDR series memory is needed. The cost of the system is greatly reduced.
Description
Technical field
The invention belongs to image processing field, a kind of infrared preprocessing storage system and the storage means based on FPGA in relating to.
Background technology
In the whole process of image processing, the transmission of image and pre-service are basis and the prerequisites of image processing, particularly the image preprocessing part key point especially of high speed.Along with scientific and technical in recent years high speed development, transmission to image and pretreated speed and image quality have proposed very high requirement, traditional image pretreatment system normally DSP or single-chip microcomputer carries the framework of peripheral storage device, but this framework cannot meet the pretreated requirement of present high speed image.
Along with the development of memory technology, SDRAM because its aspect capacity, access speed aspect and advantage in price, more and more be widely used in various need to carrying out in the middle of the equipment of data buffering, especially in high-speed image sampling and storage system, need the temporary transient storage of mass data, be large middle buffer memory, make SDRAM become the data buffer storage device of main flow.At present, the pattern of SDRAM memory read/write generally all can adopt to happen suddenly reads and happens suddenly the operator scheme of writing, and burst-length has 1,2,4,8 and the mode of full page, under the less pattern of burst-length (burst-length is 1,2,4,8), the utilization factor of SDRAM is very high, but read or write speed is slow, and burst-length is full page mode, SDRAM read or write speed is fast, but the utilization factor of its storage space is lower.
Summary of the invention
The object of the invention is to overcome prior art defect, a kind of infrared preprocessing storage system and the storage means based on FPGA that can read and write any burst-length data from SDRAM is provided.
For achieving the above object, the technical solution used in the present invention is:
An infrared preprocessing storage system based on FPGA, comprises FPGA module, for storing the SDRAM module of input signal and output signal, being transferred to the signal input module of FPGA module, providing signal output module, USB module, one-chip computer module, the upper computer module of data stream for receiving from the output signal of FPGA module and for the peripherals of rear end for receiving from the input signal of signal source and by input signal; FPGA module connects respectively SDRAM module, signal input module, signal output module, USB module and one-chip computer module by bus, and USB module is connected with upper computer module by bus respectively with one-chip computer module; Wherein, described FPGA module, for generation of counting enable, the addressing of address of SDRAM module, realize the orderly switching of input signal and output signal; Described USB module, for the control signal of host computer is sent to FPGA module, sends to host computer by the feedback signal of FPGA module; Described one-chip computer module, for by host computer send command to FPGA module.
Described FPGA module comprises input buffer cell, output buffer cell and sdram controller, and input buffer cell is connected with sdram controller by signal transmssion line with output buffer cell; Wherein, described input buffer cell is for input signal is cushioned, and output buffer cell is for cushioning output signal; Described sdram controller writes input signal in an orderly manner SDRAM module and reads output signal from SDRAM module.
Described SDRAM module comprises the outside SDRAM of even number sheet number; Wherein, the half SDRAM in described SDRAM module is connected with the input buffer cell in FPGA module by bus, and the SDRAM of half is connected with the output buffer cell in FPGA module by bus in addition.
Described signal input module is a DVI interface and DVI coding chip; Described signal output module comprise a DVI interface, VGA interface, LVDS interface and respectively with the corresponding decoding chip of each interface.
An infrared preprocessing storage means based on FPGA, comprises the steps:
(1). initialization sdram controller, SDRAM mode register is set, operator scheme is set to burst and reads the WriteMode that happens suddenly, and burst-length is set to full page pattern;
(2) .SDRAM controller is carried out write operation
2a) sdram controller will write the line activating of advancing of the storage space of input signal;
The row that 2b) sdram controller will write the storage space of input signal activate;
2c) sdram controller writes a burst-length data;
2d) sdram controller produces a look-at-me, and records current rank addresses;
2e) sdram controller judges whether the remaining storage space of current line can store the data of a burst-length, if can, continue to write the data of a burst-length; If cannot, a part for a burst-length data is stored in the remaining storage space of current line, sdram controller activates the first row storage space of next line and next line, and the remainder of a burst-length data is stored in the storage space of next line;
2f) sdram controller carries out precharge to SDRAM module, carries out write operation next time;
(3) .SDRAM controller is carried out read operation
3a) sdram controller will be read the line activating of advancing of the storage space of output signal;
The row that 3b) sdram controller will be read the storage space of output signal activate;
3c) sdram controller is read a burst-length data;
3d) sdram controller produces a look-at-me, and records current rank addresses;
3e) sdram controller judgement, judges whether the data of the remaining storage space of current line have the data of a burst-length, if had, continues to read the data of a burst-length; If no, the remaining data of current line is read out, sdram controller activates the first row storage space of next line and next line, reads the remainder of a burst-length data from next line storage space;
3f) sdram controller carries out precharge to SDRAM module, carries out read operation next time.
The present invention compared with prior art has as follows a little:
1. the resolution based on current infrared eye and frame frequency are generally not high, so the capacity of the infrared image collecting is little, the bandwidth of transmission is not high yet, the present invention is based on the framework of FPGA+MCU, infrared preprocessing storage system based on FPGA is used SDRAM as buffer memory, FPGA is responsible for the transmission of picture signal, and MCU is responsible for the parsing of instruction, FPGA and the MCU division of labor are clear and definite, give full play to separately a little, meet the requirement of real-time of image processing completely, do not need DDR series memory at a high speed, greatly reduce the cost of system.
The present invention by FPGA can activate arbitrarily the SDRAM that will read and write row and and row storage space, can from SDRAM, read and write the data of any burst-length, thereby in the situation that improving SDRAM read or write speed, avoid the waste of SDRAM storage space, improve the utilization factor of cache resources, this system interface is simple, easy to operate, there is higher use value.
Brief description of the drawings
Fig. 1 is system architecture diagram of the present invention;
Fig. 2 is the state of a control figure of SDRAM in the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.
As shown in Figure 1, the infrared preprocessing storage system based on FPGA, comprises FPGA module, SDRAM module, signal input module, signal output module, USB module, one-chip computer module, upper computer module; FPGA module connects respectively SDRAM module, signal input module, signal output module, USB module and one-chip computer module by bus, and USB module is connected with upper computer module respectively by bus with one-chip computer module; Wherein,
Described FPGA module, for generation of counting enable, the addressing of address of SDRAM module, realize the orderly switching of input signal and output signal;
Described SDRAM module, for storing input signal and output signal;
Described signal input module, for receiving the input signal from signal source, is transferred to FPGA module by input signal;
Described signal output module, for receiving the output signal from FPGA module, for the peripherals of rear end provides data stream;
Described USB module, for the control signal of host computer is sent to FPGA module, sends to host computer by the feedback signal of FPGA module;
Described one-chip computer module, for by the command of host computer to FPGA module;
Described upper computer module, for sending instruction.
Infrared preprocessing storage system based on FPGA according to claim 1, it is characterized in that, described FPGA module comprises input buffer cell, output buffer cell and sdram controller, and input buffer cell is connected with sdram controller by signal transmssion line with output buffer cell; Wherein,
Described input buffer cell is for input signal is cushioned, and output buffer cell is for cushioning output signal; Described sdram controller writes input signal in an orderly manner SDRAM module and reads output signal from SDRAM module.
Described SDRAM module comprises at least two outside SDRAM, can be also that other are the SDRAM of even number sheet number; Wherein, the half SDRAM in described SDRAM module is connected with the input buffer cell in FPGA module by bus, and the SDRAM of half is connected with the output buffer cell in FPGA module by bus in addition.Described signal input module is a DVI interface and DVI coding chip.
Signal output module comprises a DVI interface, a VGA interface, a LVDS interface and its corresponding decoding chip.USB module comprises a USB interface and a USB2.0 chip.
If Fig. 2 is SDRAM state of a control figure, a kind of infrared preprocessing storage means based on FPGA, comprises the steps:
(1). initialization sdram controller, SDRAM mode register is set, operator scheme is set to burst and reads the WriteMode that happens suddenly, and burst-length is set to full page pattern;
(2) .SDRAM controller is carried out write operation
2a) sdram controller will write the line activating of advancing of the storage space of input signal;
The row that 2b) sdram controller will write the storage space of input signal activate;
2c) sdram controller writes a burst-length data;
2d) sdram controller produces a look-at-me, and records current rank addresses;
2e) sdram controller judges whether the remaining storage space of current line can store the data of a burst-length, if can, continue to write the data of a burst-length; If cannot, a part for a burst-length data is stored in the remaining storage space of current line, sdram controller activates the first row storage space of next line and next line, and the remainder of a burst-length data is stored in the storage space of next line;
2f) sdram controller carries out precharge to SDRAM module, carries out write operation next time.
(3) .SDRAM controller is carried out read operation
3a) sdram controller will be read the line activating of advancing of the storage space of output signal;
The row that 3b) sdram controller will be read the storage space of output signal activate;
3c) sdram controller is read a burst-length data;
3d) sdram controller produces a look-at-me, and records current rank addresses;
3e) sdram controller judgement, judges whether the data of the remaining storage space of current line have the data of a burst-length, if had, continues to read the data of a burst-length; If no, the remaining data of current line is read out, sdram controller activates the first row storage space of next line and next line, reads the remainder of a burst-length data from next line storage space;
3f) sdram controller carries out precharge to SDRAM module, carries out read operation next time.
Claims (5)
1. the infrared preprocessing storage system based on FPGA, is characterized in that: comprise FPGA module, for storing the SDRAM module of input signal and output signal, being transferred to the signal input module of FPGA module, providing signal output module, USB module, one-chip computer module, the upper computer module of data stream for receiving from the output signal of FPGA module and for the peripherals of rear end for receiving from the input signal of signal source and by input signal; FPGA module connects respectively SDRAM module, signal input module, signal output module, USB module and one-chip computer module by bus, and USB module is connected with upper computer module by bus respectively with one-chip computer module; Wherein,
Described FPGA module, for generation of counting enable, the addressing of address of SDRAM module, realize the orderly switching of input signal and output signal;
Described USB module, for the control signal of host computer is sent to FPGA module, sends to host computer by the feedback signal of FPGA module;
Described one-chip computer module, for by host computer send command to FPGA module.
2. the infrared preprocessing storage system based on FPGA according to claim 1, it is characterized in that: described FPGA module comprises input buffer cell, output buffer cell and sdram controller, input buffer cell is connected with sdram controller by signal transmssion line with output buffer cell; Wherein,
Described input buffer cell is for input signal is cushioned, and output buffer cell is for cushioning output signal;
Described sdram controller writes input signal in an orderly manner SDRAM module and reads output signal from SDRAM module.
3. the infrared preprocessing storage system based on FPGA according to claim 2, is characterized in that: described SDRAM module comprises the outside SDRAM of even number sheet number; Wherein,
Half SDRAM in described SDRAM module is connected with the input buffer cell in FPGA module by bus, and the SDRAM of half is connected with the output buffer cell in FPGA module by bus in addition.
4. according to the infrared preprocessing storage system based on FPGA described in claim 1,2 or 3, it is characterized in that: described signal input module is a DVI interface and DVI coding chip; Described signal output module comprise a DVI interface, VGA interface, LVDS interface and respectively with the corresponding decoding chip of each interface.
5. the infrared preprocessing storage means based on FPGA, is characterized in that comprising the steps:
(1). initialization sdram controller, SDRAM mode register is set, operator scheme is set to burst and reads the WriteMode that happens suddenly, and burst-length is set to full page pattern;
(2) .SDRAM controller is carried out write operation
2a) sdram controller will write the line activating of advancing of the storage space of input signal;
The row that 2b) sdram controller will write the storage space of input signal activate;
2c) sdram controller writes a burst-length data;
2d) sdram controller produces a look-at-me, and records current rank addresses;
2e) sdram controller judges whether the remaining storage space of current line can store the data of a burst-length, if can, continue to write the data of a burst-length; If cannot, a part for a burst-length data is stored in the remaining storage space of current line, sdram controller activates the first row storage space of next line and next line, and the remainder of a burst-length data is stored in the storage space of next line;
2f) sdram controller carries out precharge to SDRAM module, carries out write operation next time;
(3) .SDRAM controller is carried out read operation
3a) sdram controller will be read the line activating of advancing of the storage space of output signal;
The row that 3b) sdram controller will be read the storage space of output signal activate;
3c) sdram controller is read a burst-length data;
3d) sdram controller produces a look-at-me, and records current rank addresses;
3e) sdram controller judgement, judges whether the data of the remaining storage space of current line have the data of a burst-length, if had, continues to read the data of a burst-length; If no, the remaining data of current line is read out, sdram controller activates the first row storage space of next line and next line, reads the remainder of a burst-length data from next line storage space;
3f) sdram controller carries out precharge to SDRAM module, carries out read operation next time.
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Application publication date: 20141119 |