CN112100098A - DDR control system and DDR memory system - Google Patents

DDR control system and DDR memory system Download PDF

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Publication number
CN112100098A
CN112100098A CN202010980629.2A CN202010980629A CN112100098A CN 112100098 A CN112100098 A CN 112100098A CN 202010980629 A CN202010980629 A CN 202010980629A CN 112100098 A CN112100098 A CN 112100098A
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ddr
mcu
module
register
chip
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CN112100098B (en
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刘锴
宋宁
崔明章
杜金凤
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Gowin Semiconductor Corp
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Gowin Semiconductor Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

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  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

The invention provides a DDR control system and a DDR storage system, which are based on an SoC framework consisting of an MCU core and an FPGA core integrated in the same system on chip, realize the DDR control system between the MCU and an off-chip DDR memory based on logic resources in the FPGA core, the DDR control system is an on-chip DDR control system and comprises an MCU bus mapping module, a DDR data cache module and a DDR controller module, and based on the programmable characteristic of the FPGA, the number of DDR controller modules and the number of subsystem buses mapped by the MCU bus mapping module can be dynamically adjusted, a user can dynamically configure the number of DDR controller modules outside the MCU, and further dynamically configuring the accessed off-chip DDR memory through the DDR controller module, the method and the device achieve the purpose of function and data dynamic configuration of the off-chip DDR memory, improve the expansibility and usability of the MCU, and are beneficial to a user to quickly apply the DDR memory.

Description

DDR control system and DDR memory system
Technical Field
The invention relates to the technical field of DDR storage, in particular to a DDR control system and a DDR storage system.
Background
Compared with a traditional single Data Rate (DDR) memory, the DDR memory technology realizes two read/write operations within one clock cycle, that is, one read/write operation is performed at each of a rising edge and a falling edge of a clock. The DDR memory has a speed advantage and is widely used in the fields of image processing and the like.
With the rapid development of the DDR memory technology, higher requirements are put forward in the field of Microcontroller (MCU) control, and particularly in the field of image processing, it is necessary for the MCU to directly access the DDR memory. However, a special DDR interface is not provided in the conventional MCU single core architecture, the MCU core accesses the external DDR memory, and the access is also realized by an off-chip DDR control chip, and the design and application complexity of the external DDR memory of the MCU is high, which is not favorable for the user to quickly apply the DDR memory.
Disclosure of Invention
The invention aims to provide a DDR control system and a DDR storage system, which can realize an on-chip DDR control system based on FPGA (field programmable gate array) logic resources so as to solve the problem that a traditional MCU can read and write a DDR memory only by means of an external DDR control chip.
In order to solve the technical problem, the invention provides a DDR control system, which comprises an MCU core and an FPGA core integrated in the same system on a chip, wherein logic resources of the FPGA core are provided with:
the DDR controller module is used for realizing a DDR bus standard protocol based on the logic resources of the FPGA kernel and is connected with a corresponding off-chip DDR memory positioned outside the on-chip system;
the MCU bus mapping module is used for mapping an MCU system bus of the MCU kernel into a plurality of subsystem buses with dynamically configurable quantity;
and the DDR data cache module is used for connecting the corresponding DDR controller module with the MCU bus mapping module and realizing the clock-crossing data synchronization between the MCU kernel and the corresponding DDR controller module.
Optionally, the DDR controller modules are further configured to connect to the corresponding subsystem buses, and the DDR controller modules are arranged in one-to-one correspondence with the DDR data cache modules.
Optionally, the MCU bus mapping module extends to the FPGA core through an internal boundary of the FPGA core, and is connected to the corresponding DDR controller module, so as to realize interaction between the MCU core and the off-chip DDR memory.
Optionally, the MCU bus mapping module includes an address decoder and a multiplexer; the address decoder is used for mapping the address signals in the MCU system bus into the address signals of each subsystem bus; and the multiplexer is used for mapping the data signals in the MCU system bus into the data signals of each subsystem bus.
Optionally, the DDR controller modules are connected to corresponding off-chip DDR memories located outside the system on chip, and the DDR controller modules include one or more of:
the DDR function control module is used for realizing a DDR bus standard protocol based on the logic resources of the FPGA kernel and is connected with the corresponding off-chip DDR memory to realize the read-write control of the off-chip DDR memory;
and the DDR bus internal interface is connected with the DDR function control module and the DDR data cache module and is used for realizing the interaction between the DDR function control module and the DDR data cache module.
Optionally, the DDR controller module further includes a general register set, where the general register set includes a control register, a status register, a read data register, a write data register, and an address register; and each register in the general register group is connected with a corresponding pin of the DDR function control module.
Optionally, the DDR function control module includes: the device comprises a clock pin, a reset pin, a control pin, a state pin, a data reading pin, a data writing pin and an address pin; the clock pin is externally connected with a clock signal of the MCU kernel, the reset pin is externally connected with a reset signal of the MCU kernel, the control pin is connected with the control register, the state pin is connected with the state register, the data reading pin is connected with the data reading register, and the data writing pin is connected with the data writing register.
Optionally, the DDR data cache module includes a cache register group and an on-chip memory, the cache register group includes a cache control register, a cache state register, a cache read data register, a cache write data register and a cache address register, and the on-chip memory is connected to the general register group and the cache register group and is accessed to the clock signal of the MCU system bus and the clock signal of the DDR controller module, so as to synchronize the read-write data of the MCU system bus and the DDR controller module.
Optionally, the DDR control system further includes a DDR bus interrupt mapping module, where the DDR bus interrupt mapping module is connected to the DDR controller module and is configured to map an interrupt signal of the DDR controller module into an interrupt vector table of the MCU core according to a specified priority, so as to implement control of the MCU core on the priority of the DDR controller module.
Optionally, the DDR controller module includes a combinational logic circuit, and the combinational logic circuit is configured to generate an interrupt signal of the DDR controller module and provide the interrupt signal to the DDR bus interrupt mapping module.
Based on the same inventive concept, the invention also provides a DDR storage system, which comprises the DDR control system and at least one off-chip DDR memory connected with the DDR control system, wherein the off-chip DDR memory is connected with a corresponding DDR controller module in the DDR control system.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
1. the design is based on an SoC framework composed of an MCU core and an FPGA core integrated in the same system on chip, and a DDR control system between the MCU and an off-chip DDR memory is realized based on logic resources in the FPGA core, namely, an on-chip DDR control system is realized, so that the on-chip DDR control system realized in the FPGA can be used as external equipment of the MCU, and the expansibility of the MCU is improved.
2. Based on the programmable characteristic of the FPGA, the number of DDR controller modules and the number of subsystem buses mapped by the MCU bus mapping module can be dynamically adjusted, so that the design has good expansibility, a user can dynamically configure the number of DDR controller modules outside the MCU, and further dynamically configure the accessed off-chip DDR memory through the DDR controller module, so that the purpose of dynamically configuring functions and data of the off-chip DDR memory is achieved, the expansibility and the usability of the MCU are improved, the design and application complexity of the off-chip DDR memory hung outside the MCU is reduced, and the DDR memory is favorably and quickly applied by the user.
3. Furthermore, the DDR control system also realizes a DDR bus interrupt mapping module based on FPGA logic resources, and can map the interrupt signals of the DDR controller module into an interrupt vector table of the MCU kernel according to a specified priority, so that the classification control of the MCU kernel on the priority of the DDR controller module can be realized, the controllability of the MCU on the priority of the off-chip DDR memory is enhanced, and the expansibility and the usability of the off-chip DDR memory outside the MCU are improved.
Drawings
Fig. 1 is a schematic structural diagram of an on-chip DDR control system based on an MCU and an FPGASoC architecture according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an MCU bus mapping module according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a DDR controller module according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a mapping process of the MCU bus mapping module according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a DDR data cache module according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of an on-chip DDR control system based on an MCU and an FPGASoC architecture according to another embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a DDR controller module according to another embodiment of the present invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, an embodiment of the present invention provides a DDR control system, which is an on-chip DDR control system implemented based on an MCU and an FPGA SoC architecture 1, and includes an MCU core 1a and an FPGA core 1b integrated in a same on-chip SoC architecture, where logic resources inside the FPGA core 1b mainly include Logic Control Block (LCB) resources, clock network resources, clock processing resources, Block random access memory (Block RAM), digital signal processing resources (DSP core), and interface resources. The logic control block resources include display look-up tables, adders, registers, multiplexers, etc. In this embodiment, the internal logic resource of the FPGA core 1b is provided with an MCU bus mapping module 10, n DDR data cache modules 11 to 1n, and n DDR controller modules 21 to 2n, where n is not less than 2 and is an integer.
The MCU bus mapping module 10 is in communication connection with the MCU kernel 1a through an MCU system bus (such as an SPI bus or an I2C bus), the MCU bus mapping module 10 is used for mapping the MCU system bus into a plurality of subsystem buses with dynamically configurable quantity, and each subsystem bus is used for being connected with a corresponding one of the n DDR data cache modules 11-1 n one to one. Optionally, the MCU bus mapping module 10 extends into the FPGA core 1b through an internal boundary of the FPGA core 1b to be connected with the n DDR data cache modules 11 to 1n, so as to realize interaction between the MCU core 1a and the n DDR data cache modules 11 to 1 n.
Referring to fig. 2, the MCU bus mapping module 10 includes An address decoder 10a and a multiplexer 10b, where the address decoder 10a is configured to decode An external device address space of the MCU core 1a occupied by each subsystem bus, that is, decode An external device address space depth of the MCU core 1a used by each of the off-chip DDR memories 31 to 3n, so as to map An address signal sent by the MCU core 1a through the MCU system bus to An address signal a1 to An of the off-chip DDR memory 31 to 3n (also referred to as the DDR data cache module 11 to 1n and the DDR controller module 21 to 2n), so as to implement reading, writing, and controlling of the off-chip DDR memory 31 to 3n by the MCU core 1 a. Further, the address decoder 10a is further configured to analyze the number of the dynamically configured off-chip DDR memories 31 to 3n, calculate the depth of the external device address space of the MCU core 1a commonly used by all the off-chip DDR memories 31 to 3n, the MCU core 1a can allocate the depth of the address block of each off-chip DDR memory in the external address space thereof according to the calculated depth of the address commonly used by the off-chip DDR memories 31 to 3n by the address decoder 10a, and each address block maps one off-chip DDR memory, thereby implementing the read, write and control of each off-chip DDR memory by the MCU core 1 a. The multiplexer 10b is configured to map a data signal in the MCU system bus to data signals D1-Dn corresponding to the off-chip DDR memories 31-3 n (also the DDR data cache modules 11-1 n and the DDR controller modules 21-2 n) under control of a control signal sent by the MCU core 1a, that is, each data channel established in the multiplexer 10b is a channel for reading and writing data of the off-chip DDR memory corresponding to each address block and the MCU core 1a controls to select one data channel, so as to implement reading, writing and controlling of the off-chip DDR memory by the MCU core 1 a. Thus, the MCU system bus is mapped to n sub-system buses 1 to n corresponding to the off-chip DDR memories 31 to 3n by the address decoder 10a and the multiplexer 10 b.
Further, the MCU bus mapping module 10 is configured to receive an operation instruction sent by the MCU core 1a from the MCU system bus, and determine the type of the operation instruction.
Referring to fig. 1, n DDR data cache modules 11 to 1n are disposed in one-to-one correspondence with the DDR controller modules 21 to 2n, and are used to connect the corresponding DDR controller modules to the MCU bus mapping module 10, and implement the inter-clock data synchronization between the MCU core 1a and the corresponding DDR controller modules, that is, cache the high-speed clock data of the DDR controller modules connected thereto and the clock data of the MCU system bus through the DDR data cache modules, so as to implement the synchronization between the data of the MCU system bus and the data of the DDR controller modules,
referring to fig. 5, each of the DDR data cache modules includes a cache register set and an on-chip memory 100. The cache register group includes a cache control register 101, a cache status register 102, a cache read data register 103, a cache write data register 104, and a cache address register 105. The cache control register 101 is used for caching relevant signals for controlling and determining the operation mode of the off-chip DDR memory and the characteristics of the currently executed task; the cache status register 102 is used to cache two types of information: one type is various state information reflecting the execution result of the current instruction, and the other type is storage control information; the cache read data register 103 is used for caching data read by the DDR controller module from the off-chip DDR memory; the cache write data register 104 is used for temporarily storing data which needs to be written into the off-chip DDR memory by the DDR controller module; the cache address register 105 is used to cache address signals on the required subsystem bus. The on-chip memory 100 is connected to a cache register group and a corresponding general register group of the DDR control module, and is connected to a clock signal of the MCU system bus and a clock signal of the DDR controller module, so as to synchronize read and write data of the MCU system bus and the DDR controller module. Specifically, the on-chip memory 100 can map an address signal of the MCU system bus to an address bus of the corresponding DDR controller module in a cross-clock manner, map a write data signal of the MCU system bus to a write data bus of the corresponding DDR controller module in a cross-clock manner, and map a read data signal of the corresponding DDR controller module to a read data signal of the MCU system bus in a cross-clock manner, thereby achieving synchronization of read and write data between the MCU system bus and the DDR controller module.
Referring to fig. 1, each of the DDR controller modules 21 to 2n is configured to implement a DDR bus standard protocol based on logic resources of the FPGA core 10, and is connected to the off-chip DDR memories 31 to 3n disposed outside the SoC and the DDR data cache modules 11 to 1n disposed inside the SoC in a one-to-one correspondence manner. In practical application, the number of the off-chip DDR memories actually accessed to the system may be smaller than the number n of the DDR controller modules, and at this time, some of the DDR controller modules are not connected with the off-chip DDR memories and are in an idle state.
Referring to FIG. 3, each of the DDR controller modules 21-2 n includes a DDR function control module 200, a bus internal interface (not shown), and a general register set. The DDR function control module 200 is configured to implement a DDR bus standard protocol based on the logic resources of the FPGA core 1b, and implement connection with an off-chip DDR memory. The bus internal interface is connected with the DDR function control module 200 and the corresponding DDR data cache module, and is used for realizing interaction between the DDR function control module 200 and the DDR data cache module.
The general register set comprises a control register 201, a status register 202, a read data register 203, a write data register 204 and an address register 205, wherein the control register 201 is used for controlling and determining the operation mode and the characteristics of the currently executed task, and the status register 202 is used for storing two types of information: one type is various state information reflecting the execution result of the current instruction, and the other type is storage control information; the read data register 203 is used for temporarily storing read data; the write data register 204 is used for temporarily storing data to be written, and the address registers 2-5 are used for temporarily storing address signals.
The DDR function control module 200 comprises a clock pin, a reset pin, a control pin, a state pin, a data reading pin, a data writing pin, an address pin and a DDR control pin of the DDR memory connected outside the chip; the clock pin is externally connected with a clock signal of the DDR controller module, the reset pin is externally connected with a reset signal of the MCU core 1a, the control pin is connected with the control register 201, the status pin is connected with the status register 202, the read data pin is connected with the read data register 203, the write data pin is connected with the write data register 204, and the address pin is connected with the address register 205.
As an example, the MCU bus mapping module 10 performs address segmentation on the external device address space of the MCU core 1a according to the address depth of the general register set in each of the DDR controller modules 21 to 2n and the number of the accessed off-chip DDR memories 31 to 3n, forms a mapping relationship between the address segmentation and the register set address of the general register set, and further sends the mapping relationship to the MCU core 1a through the MCU system bus, so that the MCU core 1a can generate an external device address signal dedicated to each of the accessed off-chip DDR memories 31 to 3n according to the mapping relationship. Further, the MCU bus mapping module 10 further maps the external device address signal dedicated to each off-chip DDR memory 31 to 3n to a general register set address signal of the off-chip DDR memory 31 to 3n, and further sends the address signal to the DDR controller module through the DDR data cache module, and the DDR controller module operates the general register set according to the general register set address signal, so as to further operate the connected off-chip DDR memory by using the general register set, and thus, read, write, and control of the MCU core 1a and the off-chip DDR memories 31 to 3n are achieved.
The following describes a specific process when the MCU needs to operate an off-chip DDR memory 3i (i is not less than 1 and not more than n) with reference to fig. 1 to 4, at this time, the system on chip SoC where the MCU core 1a is located has access to a plurality of off-chip DDR memories 31 to 3n including the off-chip DDR memory 3i, and the MCU bus mapping module 10 has mapped the external device address space of the MCU core 1a into n number of dynamically configurable subsystem buses according to the address depth of the general register set in each of the DDR controller modules 21 to 2n and the number of the accessed off-chip DDR memories 31 to connect to an off-chip DDR memory, where the i-th subsystem bus is connected to the data cache module 1i, the DDR controller module 2i is connected to the DDR data cache module 1i and the off-chip DDR memory 3i, and interaction between the system-on-chip SoC and the off-chip DDR memory 3i is realized. The specific process that the MCU core 1a needs to operate the off-chip DDR memory 3i includes:
firstly, an MCU (microprogrammed control Unit) kernel 1a sends an operation instruction, an MCU bus mapping module 10 decodes the operation instruction to judge whether the ith subsystem bus corresponding to an off-chip DDR memory 3i is selected or not, if not, a DDR data cache module 1i and a DDR controller module 2i connected with the off-chip DDR memory 3i are both continuously in a standby state, if so, the DDR data cache module 1i is enabled, the operation type is analyzed from the operation instruction, and whether the operation is a read operation or a write operation is judged;
if the external DDR memory 3i is in read operation, the DDR controller module 2i selects a register to be operated from the general register set according to the general register set address signal of the external DDR memory 3i provided by the MCU bus mapping module 10, wherein the register to be operated comprises a state register, a control register, an address register and a read data register, and the selected register is used for controlling and reading data of the external DDR memory 3 i. Address signals related to the read operation can be buffered and cross-clocked through a buffer address register of the DDR buffer data module 1i and then temporarily stored in an address register of the DDR controller module 2 i; the temporarily stored and read data can be temporarily stored in a read data register of the DDR controller module 2i and further cached in a cache read data register of the DDR cache data module 1 i; controlling and determining the operation mode, the characteristics of the currently executed task and other information to be temporarily stored in a cache control register of the DDR cache data module 1i, and further cached in a control register of the DDR controller module 2i after being processed by a cross-clock of the DDR cache data module 1 i; various state information reflecting the current instruction execution result, control information generated by the DDR controller module 2i and used for controlling the off-chip DDR memory 3i, and the like are temporarily stored in the state register of the DDR controller module 2i, and are further cached in the cache state register of the DDR cache data module 1i after being subjected to cross-clock processing by the DDR cache data module 1 i. The DDR controller module 2i further sends the data in the read data register to the MCU core 1a through the MCU bus mapping module 10 and the DDR cache data module 1i to complete the read data operation.
If the write operation is performed, the DDR controller module 2i selects a register to be operated, which includes an address register, a control register and a write data register, from the general register set according to the general register set address signal of the off-chip DDR memory 3i provided by the MCU bus mapping module 10, and controls and writes data into the off-chip DDR memory 3i through the selected register. Data to be written into the off-chip DDR memory 3i can be temporarily stored in a cache write data register of the DDR cache data module 1i, and is further cached in a write data register of the DDR controller module 2i after being subjected to cross-clock processing by the DDR cache data module 1 i; address signals related to the write operation can be buffered and subjected to clock crossing processing through a buffer address register of the DDR buffer data module 1i, and then are temporarily stored in an address register of the DDR controller module 2 i; the information of controlling and determining the operation mode, the characteristics of the currently executed task and the like is temporarily stored in a cache control register of the DDR cache data module 1i, and is further cached in a control register of the DDR controller module 2i after being processed by the DDR cache data module 1i in a clock crossing manner. The DDR controller module 2i further completes the write data operation by writing the data in its write data register into the off-chip DDR memory 3 i.
The embodiment provides an on-chip DDR control system design based on an MCU and FPGASoC framework, the design has the characteristic of FPGA (field programmable gate array) programming, the on-chip DDR control system has good expansibility and usability, a user can dynamically manage the functions and the number of off-chip DDR memories outside the MCU, the control capability of the on-chip DDR memories inside the MCU to the off-chip DDR memories is improved, the expandability and the universality of the MCU functions are enhanced, the read-write design and the application complexity of the off-chip DDR memories outside the MCU are reduced, and the DDR memories can be rapidly applied by the user.
Referring to fig. 5 and 6, in order to realize the classification control of the priority of each of the DDR controller modules 21 to 2n by the MCU core 1a and improve the scalability and the usability of the off-chip DDR memory outside the MCU, another embodiment of the present invention further provides a DDR control system based on the MCU and the FPGAs Soc architecture, which includes the MCU core 1a and the FPGA core 1b integrated in the same system on chip Soc, and an MCU bus mapping module 10, n DDR data cache modules 11 to 1n, n DDR controller modules 21 to 2n, and a DDR bus interrupt mapping module 40 are provided based on the logic resources inside the FPGA core 1b, where n is not less than 2 and is an integer.
Compared with the DDR control system in the previous embodiment, in the DDR control system of this embodiment, the MCU bus mapping module 10 and the n DDR data cache modules 11 to 1n have the same structure and function, each DDR controller module 21 to 2n is additionally provided with a combinational logic circuit 206, and the combinational logic circuit 206 is connected to the control register and the status register of the DDR controller module, and is configured to generate an interrupt signal of the DDR controller module according to information of the control register and the status register of the DDR controller module, and provide the interrupt signal to the DDR bus interrupt mapping module 40.
The DDR interrupt mapping module 40 is mainly implemented by some combinational logic circuits in the FPGA core 10, and the output of the combinational logic circuit at any time is only dependent on the input at that time, and is unrelated to the original state of the circuit. The input side of the DDR interrupt mapping module 40 is connected with the output ends of the combinational logic circuits of the DDR controller modules 21-2 n, and the output side of the DDR interrupt mapping module 40 is connected with an interrupt vector table of the MCU core 1A. The DDR interrupt mapping module 40 is configured to map the interrupt signals of the DDR controller modules 21 to 2n to an interrupt vector table of the MCU core 1a according to a specified priority, so as to implement control of the MCU core 1a on the priority of the DDR controller modules 21 to 2 n.
Compared with the previous embodiment, the DDR control system based on the MCU and the FPGASoC architecture of the embodiment can further achieve the classification control of the MCU core on the priority of each DDR controller module, enhance the classification control of the MCU on the priority of the off-chip DDR memory, and improve the extensibility and usability of the off-chip DDR memory outside the MCU.
Based on the same inventive concept, please refer to fig. 1 to 7, an embodiment of the present invention further provides a DDR memory system, including the DDR control system according to any one of the embodiments, and at least one off-chip DDR memory 31 to 3n connected to the DDR control system (i.e., the system on chip SoC), where each of the off-chip DDR memories 31 to 3n is connected to a corresponding one of the DDR controller modules 21 to 2n in the DDR control system.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
It is to be further understood that the present invention is not limited to the particular methodology, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.

Claims (11)

1. The DDR control system is characterized by comprising an MCU core and an FPGA core which are integrated in the same system on a chip, wherein logic resources of the FPGA core are provided with:
the DDR controller module is used for realizing a DDR bus standard protocol based on the logic resources of the FPGA kernel;
the MCU bus mapping module is used for mapping an MCU system bus of the MCU kernel into a plurality of subsystem buses with dynamically configurable quantity;
and the DDR data cache module is used for connecting the corresponding DDR controller module with the MCU bus mapping module and realizing the clock-crossing data synchronization between the MCU kernel and the corresponding DDR controller module.
2. The DDR control system of claim 1, wherein the DDR controller modules are further configured to connect to respective ones of the subsystem buses, and the DDR controller modules are arranged in a one-to-one correspondence with DDR data cache modules.
3. The DDR control system of claim 1, wherein the MCU bus mapping module extends to the FPGA core through an internal boundary of the FPGA core and connects to the corresponding DDR controller module to enable interaction of the MCU core with the off-chip DDR memory.
4. The DDR control system of claim 1, wherein the MCU bus mapping module includes an address decoder and a multiplexer; the address decoder is used for mapping the address signals in the MCU system bus into the address signals of each subsystem bus; and the multiplexer is used for mapping the data signals in the MCU system bus into the data signals of each subsystem bus.
5. The DDR control system of claim 1, wherein the DDR controller modules connect to respective off-chip DDR memories located external to the system-on-chip, the DDR controller modules being one or more and comprising:
the DDR function control module is used for realizing a DDR bus standard protocol based on the logic resources of the FPGA kernel and is connected with the corresponding off-chip DDR memory to realize the read-write control of the off-chip DDR memory;
and the DDR bus internal interface is connected with the DDR function control module and the DDR data cache module and is used for realizing the interaction between the DDR function control module and the DDR data cache module.
6. The DDR control system of claim 5, wherein the DDR controller module further comprises a general purpose register set comprising a control register, a status register, a read data register, a write data register, and an address register; and each register in the general register group is connected with a corresponding pin of the DDR function control module.
7. The DDR control system of claim 6, wherein the DDR function control module comprises: the device comprises a clock pin, a reset pin, a control pin, a state pin, a data reading pin, a data writing pin and an address pin; the clock pin is externally connected with a clock signal of the MCU kernel, the reset pin is externally connected with a reset signal of the MCU kernel, the control pin is connected with the control register, the state pin is connected with the state register, the data reading pin is connected with the data reading register, and the data writing pin is connected with the data writing register.
8. The DDR control system of claim 6, wherein the DDR data cache module comprises a cache register group and an on-chip memory, the cache register group comprises a cache control register, a cache status register, a cache read data register, a cache write data register and a cache address register, and the on-chip memory is connected to the general register group and the cache register group and accesses a clock signal of the MCU system bus and a clock signal of the DDR controller module to achieve synchronization of read and write data of the MCU system bus and the DDR controller module.
9. The DDR control system of any one of claims 1 to 8, further comprising a DDR bus interrupt mapping module, wherein the DDR bus interrupt mapping module is connected to the DDR controller module and is configured to map interrupt signals of the DDR controller modules into an interrupt vector table of the MCU core according to a specified priority, so as to control the priority of the DDR controller modules by the MCU core.
10. The DDR control system of claim 9, wherein the DDR controller module includes combinational logic circuitry to generate interrupt signals for the DDR controller module and to provide to the DDR bus interrupt mapping module.
11. A DDR memory system, comprising the DDR control system according to any one of claims 1 to 10, and at least one off-chip DDR memory connected to the DDR control system, wherein the off-chip DDR memory is connected to a corresponding one of the DDR controller modules in the DDR control system.
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