CN110806997A - System on chip and memory - Google Patents
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- CN110806997A CN110806997A CN201910984051.5A CN201910984051A CN110806997A CN 110806997 A CN110806997 A CN 110806997A CN 201910984051 A CN201910984051 A CN 201910984051A CN 110806997 A CN110806997 A CN 110806997A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
Abstract
The application discloses system on chip and memory, wherein, this system on chip includes treater and memory, and the system bus of treater is connected to the memory, and the memory is realized based on FPGA's logic resource, and this memory includes: the system bus interface is connected with the system bus and used for establishing communication connection with the processor; the functional interface modules are used for storing data and instructions; and the controller is connected with the system bus interface and the plurality of functional interface modules and is used for performing read operation or write operation on the corresponding functional interface module according to the storage address signal received by the system bus interface from the processor. By the mode, the capacity of the memory can be dynamically allocated by utilizing the programmable characteristic of the FPGA, so that the usability of the FPGA is improved, and the design difficulty of the memory is reduced.
Description
Technical Field
The present application relates to the field of system-on-chip technologies, and in particular, to a system-on-chip and a memory.
Background
System-on-a-chip (SoC) refers to a technology for grouping all or part of necessary electronic circuits by integrating a complete System on a single chip. A so-called complete system typically includes a processor, memory, and peripheral circuits, among others. SoC is developed in parallel with other technologies, such as Silicon On Insulator (SOI), which can provide enhanced clock frequencies, thereby reducing the power consumption of the microchip.
The memory in the existing system on chip has fixed memory capacity, can not be dynamically configured, is relatively inflexible, and has complex design.
Disclosure of Invention
In order to solve the above problems, the present application provides an on-chip system and a memory, which can dynamically allocate the capacity of the memory by using the programmable feature of the FPGA, thereby improving the usability of the FPGA and reducing the design difficulty of the memory.
The technical scheme adopted by the application is as follows: the system on chip comprises a processor and a memory, wherein the memory is connected with a system bus of the processor and is realized based on logic resources of an FPGA (field programmable gate array), and the memory comprises: the system bus interface is connected with the system bus and used for establishing communication connection with the processor; the functional interface modules are used for storing data and instructions; and the controller is connected with the system bus interface and the plurality of functional interface modules and is used for performing read operation or write operation on the corresponding functional interface module according to the storage address signal received by the system bus interface from the processor.
The system bus interface carries out address segmentation on the storage address space of the processor according to the address depth of a register in the controller and the storage capacity distribution condition in the plurality of functional interface modules, forms a mapping relation between the address segmentation and the register address of the register, and further sends the mapping relation to the processor through the system bus, so that the processor can generate a storage address signal according to the mapping relation.
The address decoder is connected with the system bus, and is used for mapping a storage address signal sent by the processor through the system bus into a register address signal mapped by the corresponding functional interface module and further sending the register address signal to the controller; the chip selection selector is connected with the system bus and used for sending the chip selection signal to the controller according to the chip selection signal sent by the processor through the system bus so that the controller can select the corresponding functional interface module according to the chip selection signal and establish connection to transmit the data signal; and the data channel is connected with the system bus and the controller.
The address decoder is further connected with the chip selection selector, and after the address decoder successfully maps the storage address signal into the register address signal, the address decoder further generates a read-write enabling signal and sends the read-write enabling signal to the chip selection selector, and the read-write enabling signal is further forwarded to the selected functional interface module by the chip selection selector through the controller.
The controller comprises a control module and a plurality of registers; the control module is connected with the system bus interface, each register is respectively connected with one port of the control module and one port of the functional interface module, and the control module is used for operating the corresponding register according to a register address signal sent by the processor through the system bus.
The plurality of registers include a control register, a status register, a read data register, and a write data register.
The controller comprises a plurality of register groups, each register group corresponds to one functional interface module, and each register group respectively comprises a control register, a state register, a read data register and a write data register.
Wherein, the functional interface module includes: the memory interface is connected with the controller and the system bus interface and is used for carrying out data communication with the controller and the system bus interface; the memory function module is connected with the memory interface and used for storing data; the memory interface comprises a clock port, a reset port, a control port, a state port, a read data port and a write data port.
Wherein, the memory is a random access memory.
Another technical scheme adopted by the application is as follows: providing a memory implemented based on logic resources of an FPGA, the FPGA being connected to a processor through a system bus of the processor, the memory comprising: the system bus interface is connected with the system bus and used for establishing communication connection with the processor; the functional interface modules are respectively connected with the system bus interface, are used for interacting with the system bus interface and are used for storing data and instructions; and the controller is connected with the system bus interface and the plurality of functional interface modules and is used for performing read operation or write operation on the corresponding functional interface module according to the storage address signal received by the system bus interface from the processor.
The system on chip provided by the application comprises a processor and a memory, wherein the memory is connected with a system bus of the processor, the memory is realized based on logic resources of an FPGA, and the memory comprises: the system bus interface is connected with the system bus and used for establishing communication connection with the processor; the functional interface modules are used for storing data and instructions; and the controller is connected with the system bus interface and the plurality of functional interface modules and is used for performing read operation or write operation on the corresponding functional interface module according to the storage address signal received by the system bus interface from the processor. By the mode, due to the programmable characteristic of the FPGA, research personnel can dynamically allocate the capacity and the address of the memory, the expansibility and the usability of the FPGA are improved, the flexibility of using storage resources by the system on chip is improved, and in addition, due to the fact that the scheme is easy to operate, the complexity of the design of the memory is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram of a first configuration of a system-on-chip provided herein;
FIG. 2 is a schematic diagram of a memory structure provided herein;
FIG. 3 is a schematic structural diagram of a controller provided in an embodiment of the present application;
FIG. 4 is a schematic diagram of the connection of a controller and a functional interface module provided herein;
FIG. 5 is a schematic structural diagram of a functional interface module provided in the present application;
FIG. 6 is a schematic diagram of the connection of a controller and a plurality of functional interface modules provided herein;
FIG. 7 is a schematic diagram of a system bus interface provided in the present application;
fig. 8 is a schematic workflow diagram provided herein.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish between different objects and not to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic diagram of a first structure of a system on chip provided in the present application, where the system on chip 10 includes a processor 11 and an FPGA (Field-Programmable Gate Array) 12, and the processor 11 and the FPGA12 are connected through a system bus 13 of the processor 11. Wherein the memory 20 is implemented based on the logic resources of the FPGA 12.
In this embodiment, the logic resources inside the FPGA mainly include an LCB (Logical control Block) (including a display lookup table, an adder, a register, and a multiplexer), a clock network resource, a clock processing unit, a Block random access memory (Block RAM), a DSP core, and an interface resource.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory provided in the present application, where the memory 20 includes a system bus interface 21, a controller 22, and a plurality of functional interface modules 23.
The system bus interface 21 is connected to the system bus 13 for establishing a communication connection with the processor 11; the plurality of functional interface modules 23 are used for storing data and instructions; the controller 22 is connected to the system bus interface 21 and the plurality of functional interface modules 23, and is configured to perform a read operation or a write operation on the corresponding functional interface module 23 according to a storage address signal received by the system bus interface 21 from the processor 11.
Referring to fig. 3 again, fig. 3 is a schematic structural diagram of the controller according to the embodiment of the present application, where the controller 22 includes a control module 221 and a register set 222, the control module 221 is connected to the system bus interface 21 and each register in the register set 222, and one register set 222 is connected to one of the plurality of function interface modules 23, that is, each register in one register set 222 is respectively connected to one port in one function interface module 23.
In an alternative embodiment, the control module 221 may be implemented by a combinational logic circuit, and the logic function of the combinational logic circuit is characterized in that the output at any time is only dependent on the input at that time, and is independent of the original state of the circuit. Optionally, in an embodiment, the plurality of register sets 222 may respectively correspond to one control module 221, and in another embodiment, the plurality of register sets 222 may correspond to the same control module 221.
The control module 221 is connected to the system bus interface 21, each register is connected to one port of the control module 221 and one port of the functional interface module 23, and the control module 221 is configured to operate the corresponding register according to a register address signal sent by the processor 11 through the system bus 13.
Optionally, the plurality of registers includes a control register, a status register, a read data register, and a write data register.
With reference to fig. 4 and fig. 5, fig. 4 is a schematic connection diagram of a controller and a functional interface module provided in the present application, and fig. 5 is a schematic structural diagram of the functional interface module provided in the present application, wherein the functional interface module 23 includes a memory interface 231 and a memory functional module 232, and wherein the controller 22 and the system bus interface 21 are connected for data communication with the controller 22 and the system bus interface 21; the memory function module 232 is connected to the memory interface 231 for storing data.
The memory interface 231 includes a clock port, a reset port, a control port, a status port, a read data port, and a write data port. The clock port and the reset port are connected to the system bus 13 and configured to receive a clock signal and a reset signal, and the status port, the read data port and the write data port are respectively connected to the control register, the status register, the read data register and the write data register of the controller 22.
As shown in fig. 6, fig. 6 is a schematic diagram illustrating connection between a controller and a plurality of functional interface modules provided in the present application, in the above embodiment, the controller 22 may include a plurality of register sets, each register set corresponds to one functional interface module, and each register set includes a control register, a status register, a read data register, and a write data register, respectively.
Referring to fig. 2 again, in the above embodiment, the system bus interface 21 performs address segmentation on the storage address space of the processor 11 according to the address depth of the register in the controller 22 and the storage capacity allocation condition in the plurality of functional interface modules 23, forms a mapping relationship between the address segmentation and the register address of the register, and further sends the mapping relationship to the processor 11 through the system bus 13, so that the processor 11 can generate the storage address signal according to the mapping relationship.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a system bus interface provided in the present application, where the system bus interface 21 includes an address decoder 211, a chip select selector 212, and a data channel 213. The address decoder 211 is connected to the system bus 13, and configured to map a storage address signal sent by the processor 11 through the system bus 13 into a register address signal mapped by the corresponding functional interface module 23, and further send the register address signal to the controller 22; the chip selection selector 212 is connected to the system bus 13, and configured to send a chip selection signal to the controller 22 according to the chip selection signal sent by the processor 11 through the system bus 13, so that the controller 22 selects the corresponding functional interface module 23 according to the chip selection signal and establishes connection to transmit a data signal; the data channel 213 connects the system bus 13 and the controller 22.
The address decoder 211 is further connected to the chip select selector 213, and the address decoder 211 further generates a read/write enable signal after successfully mapping the storage address signal to the register address signal, and sends the read/write enable signal to the chip select selector 212, so that the read/write enable signal is forwarded to the selected functional interface module 23 by the chip select selector 212 through the controller 22.
In an alternative embodiment, the functional register addresses of the groups of functional registers share the same address segment of processor 11. The control module 221 operates on multiple sets of function registers simultaneously according to the function register addresses.
Taking write data as an example, the control module 221 obtains the register address from the system bus interface 21, and since the functional register addresses of the plurality of functional registers share the same address segment in the peripheral address space of the processor 11, the control module 221 writes corresponding data into the write data register in each register group 222. Further, each write data register performs a write data operation through the corresponding functional interface module 23.
In another alternative embodiment, the control module 221 determines the functional interface module 23 to be enabled according to the register address, and operates the register connected to the functional interface module 23 to be enabled according to the register address.
Taking data reading as an example, the control module 221 obtains a register address from the system bus interface 21, operates the corresponding enable bit of the register according to the register address, and controls the enable state of the functional interface module 23 corresponding to the enable bit. Further, the control module 221 determines the functional interface module 23 to be enabled according to the register address, and performs a data reading operation on the functional register connected to the functional interface module 23 to be enabled according to the register address.
In addition, the processor 11 sets offset addresses of a plurality of sets of function registers based on the same base address. Taking the processor 11 controlling the three functional interface modules 23 as an example, the base address 0x10 is defined, and the offset addresses of the control register, the status register, the read data register, and the write data register are 0x0, 0x1, 0x2, and 0x3, respectively, and only 4 address spaces need to be occupied. Compared with using three system buses to control three functional interface modules 23, each address comprises 5 offset addresses, 15 address spaces are occupied, and 11 address spaces can be saved. In this way, the more the number of the functional interface modules 23 is, the more the number of the address spaces is saved, and the more the effect is obvious.
Referring to fig. 8, fig. 8 is a schematic view of a work flow provided by the present application.
1) And judging whether the system bus is selected.
Specifically, when the processor needs to perform read-write operation, the register address that needs to be read-write operated is sent to the address bus, and the control module can control the enabling register to enable the corresponding functional interface according to the register address.
2) It is determined whether a read operation or a write operation.
Specifically, the processor sends a "read" or "write" signal to the control bus, and the control module adjusts the data transfer direction of the register to "read" or "write" according to the signal.
Furthermore, when reading operation is carried out, the control module controls the corresponding read data register, the control register and the state register to work; when writing operation is carried out, the control module controls the corresponding write data register, the control register and the state register to work.
In the above embodiments, the Memory may be a Random Access Memory (RAM), and the time required for data reading and writing in the Random Access Memory is independent of the location of the data or the location of the data being written. The RAM is a memory which can randomly access each storage unit through instructions, has the characteristics of random access, volatility, electrostatic sensitivity and high-speed access, and is usually used as an internal memory for directly exchanging data by the MCU and a temporary data storage medium of an operating system or other programs in operation.
Different from the prior art, the system on chip provided by this embodiment includes a processor and a memory, the memory is connected to a system bus of the processor, the memory is implemented based on logic resources of an FPGA, and the memory includes: the system bus interface is connected with the system bus and used for establishing communication connection with the processor; the functional interface modules are respectively connected with the system bus interface, are used for interacting with the system bus interface and are used for storing data and instructions; and the controller is connected with the system bus interface and the plurality of functional interface modules and is used for performing read operation or write operation on the corresponding functional interface module according to the storage address signal received by the system bus interface from the processor. By the mode, due to the programmable characteristic of the FPGA, research personnel can dynamically allocate the capacity and the address of the memory, the expansibility and the usability of the FPGA are improved, the flexibility of using storage resources by the system on chip is improved, and in addition, due to the fact that the scheme is easy to operate, the complexity of the design of the memory is reduced.
In the above embodiments, the processor may be an MCU (micro controller Unit), the Memory may be a Read-Only Memory (ROM), and the ROM is a solid-state semiconductor Memory capable of Only reading out data stored in advance, and can Only Read out and cannot be rewritten during operation. The ROM features stable stored data, no change of stored data after power-off, simple structure, convenient reading out and being used for storing various fixed programs and data.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made according to the content of the present specification and the accompanying drawings, or which are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A system on a chip, the system on a chip comprising a processor and a memory, the memory being connected to a system bus of the processor, the memory being implemented based on logic resources of an FPGA, the memory comprising:
the system bus interface is connected with the system bus and used for establishing communication connection with the processor;
the functional interface modules are used for storing data and instructions;
and the controller is connected with the system bus interface and the plurality of functional interface modules and is used for performing read operation or write operation on the corresponding functional interface module according to the storage address signal received by the system bus interface from the processor.
2. The system-on-chip of claim 1,
the system bus interface carries out address segmentation on a storage address space of the processor according to the address depth of a register in the controller and the storage capacity distribution condition in the functional interface modules, forms a mapping relation between the address segmentation and the register address of the register, and further sends the mapping relation to the processor through the system bus, so that the processor can generate the storage address signal according to the mapping relation.
3. The system-on-chip of claim 2,
the system bus interface includes:
the address decoder is connected with the system bus and used for mapping the storage address signal sent by the processor through the system bus into a corresponding register address signal mapped by the functional interface module and further sending the register address signal to the controller;
the chip selection selector is connected with the system bus and used for sending a chip selection signal to the controller according to the chip selection signal sent by the processor through the system bus so as to enable the controller to select the corresponding functional interface module according to the chip selection signal and establish connection to transmit a data signal;
and the data channel is connected with the system bus and the controller.
4. The system-on-chip of claim 3,
the address decoder is further connected with the chip selection selector, and the address decoder further generates a read-write enabling signal after the storage address signal is successfully mapped into the register address signal and sends the read-write enabling signal to the chip selection selector, and then the chip selection selector forwards the read-write enabling signal to the selected functional interface module through the controller.
5. The system-on-chip of claim 3,
the controller comprises a control module and a plurality of registers;
the control module is connected with the system bus interface, each register is respectively connected with one port of the control module and one port of the functional interface module, and the control module is used for operating the corresponding register according to a register address signal sent by the processor through the system bus.
6. The system-on-chip of claim 5,
the plurality of registers include a control register, a status register, a read data register, and a write data register.
7. The system-on-chip of claim 5,
the controller comprises a plurality of register groups, each register group corresponds to one functional interface module, and each register group respectively comprises a control register, a state register, a read data register and a write data register.
8. The system-on-chip of claim 1,
the functional interface module includes:
the memory interface is connected with the controller and is used for carrying out data communication with the controller and the system bus interface;
the memory function module is connected with the memory interface and used for storing data;
the memory interface comprises a clock port, a reset port, a control port, a state port, a read data port and a write data port.
9. The system-on-chip of claim 1,
the memory is a random access memory.
10. A memory implemented based on logic resources of an FPGA, the FPGA coupled to a processor through a system bus of the processor, the memory comprising:
the system bus interface is connected with the system bus and used for establishing communication connection with the processor;
the functional interface modules are used for storing data and instructions;
and the controller is connected with the system bus interface and the plurality of functional interface modules and is used for performing read operation or write operation on the corresponding functional interface module according to the storage address signal received by the system bus interface from the processor.
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