CN111427811A - Device and method for improving communication rate of DDR controlled by PCIE - Google Patents

Device and method for improving communication rate of DDR controlled by PCIE Download PDF

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Publication number
CN111427811A
CN111427811A CN202010196287.5A CN202010196287A CN111427811A CN 111427811 A CN111427811 A CN 111427811A CN 202010196287 A CN202010196287 A CN 202010196287A CN 111427811 A CN111427811 A CN 111427811A
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China
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ddr
unit
pcie
central processing
processing unit
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CN202010196287.5A
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程绪
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Shanghai Ncatest Technologies Co Ltd
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Shanghai Ncatest Technologies Co Ltd
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Priority to CN202010196287.5A priority Critical patent/CN111427811A/en
Publication of CN111427811A publication Critical patent/CN111427811A/en
Priority to PCT/CN2020/120842 priority patent/WO2021184741A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention discloses a method for improving DDR communication speed controlled by PCIE, which comprises the following steps: s01: the central processing unit issues a control instruction to the FPGA; s02: after the FPGA receives a control instruction, caching DDR data to be read into the FPGA; s03: the central processing unit issues a reading instruction to the FPGA; s04: and after receiving the reading instruction, the FPGA transmits the cached DDR data to the central processing unit through the PCIE bus. According to the device and the method for improving the DDR communication speed controlled by the PCIE, provided by the invention, the DDR data to be read are pre-read, the communication time between the PCIE unit and the DDR unit in the FPGA is saved, and the time for the central processing unit to read the DDR data through the PCIE bus is greatly improved.

Description

Device and method for improving communication rate of DDR controlled by PCIE
Technical Field
The invention relates to the field of PCIE transmission rate, in particular to a device and a method for improving the communication rate of a PCIE-controlled DDR.
Background
The pcie (peripheral Component Interconnect express) bus has been widely used in the field of communications due to its openness and versatility. When a Central Processing Unit (CPU) controls multiple ddrs (data Direction registers) mounted under an fpga (field programmable Gate array) through a PCIE bus, the following control methods are generally adopted:
s01: the central processing unit issues a reading instruction to a PCIE unit in the FPGA through a PCIE bus; the FPGA comprises a PCIE unit and a plurality of DDR units, the PCIE unit is used for being connected with a PCIE bus, and each DDR unit is connected with one corresponding DDR.
S02: after receiving the reading instruction, the PCIE transmits the reading instruction to the DDR unit through the intercommunication interface;
s03: after the DDR unit receives the reading instruction, reading data to be DDR according to the reading instruction;
s04: the DDR unit transmits the read DDR data to the PCIE unit through the intercommunication interface;
s05: the PCIE unit analyzes the DDR data and transmits the DDR data to the central processing unit through the PCIE bus.
In a complete product frame, a central processing unit needs to read DDR memory data of each VP mainboard, each VP has 32 Gb-sized DDR memory data, a single service board has 8 VPs, the number of single boards in the whole system is dozens of single boards, according to a traditional mode that PCIE controls DDR mounted under multiple FPGAs, the time needed for reading each VP (32Gb) data is nearly 1 minute, if all memory data of the whole system are read, the time is needed for several hours, and the processing analysis of upper-layer software is very slow, so that the speed of PCIE for reading the DDR data is very slow.
Disclosure of Invention
The invention aims to provide a device and a method for improving the DDR communication speed controlled by PCIE, which pre-read DDR data to be read, save the communication time between a PCIE unit and a DDR unit in an FPGA, and greatly improve the time for a central processing unit to read the DDR data through a PCIE bus.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for improving the communication rate of DDR controlled by PCIE comprises the following steps:
s01: the central processing unit issues a control instruction to the FPGA;
s02: after the FPGA receives a control instruction, caching DDR data to be read into the FPGA;
s03: the central processing unit issues a reading instruction to the FPGA;
s04: and after receiving the reading instruction, the FPGA transmits the cached DDR data to the central processing unit through the PCIE bus.
Further, the control instruction in step S01 includes a chip select register, a length register, an initial address register, and a start signal register.
Furthermore, the FPGA comprises a PCIE unit and M DDR units, and each DDR unit is connected with one DDR through a DDR bus; m is an integer greater than 0; the step S01 specifically includes:
s011: the central processing unit sends a chip selection register to the PCIE unit;
s012: the central processing unit sequentially issues a length register, an initial address register and a start signal register to the corresponding DDR unit.
Further, the step S02 specifically includes:
s021: after the DDR unit receives the starting signal register, reading DDR data to be read out, and caching the DDR data;
s022: and DDR data to be read out cached by the DDR unit is transmitted to the PCIE unit for caching through an intercommunication interface.
Further, in the step S03, the central processing unit issues a read instruction to the PCIE unit.
Further, after the PCIE unit receives the read instruction in step S04, the buffered DDR data to be read is transmitted to the central processing unit through the PCIE bus.
A device for improving the communication rate of PCIE control DDR comprises a central processing unit, an FPGA and M DDR units, wherein the FPGA comprises a PCIE unit and M DDR units, and each DDR unit is connected with one DDR through a DDR bus; the PCIE unit is connected with the central processing unit through a PCIE bus, and the DDR unit is respectively connected with corresponding DDR through DDR buses; m is an integer greater than 0;
the central processing unit issues a control instruction to the FPGA, and the DDR unit caches DDR data to be read into the FPGA according to the issued instruction; and the central processing unit issues a reading instruction, and DDR data cached in the FPGA is transmitted to the central processing unit through a PCIE bus.
Further, the control instruction comprises a chip selection register, a length register, an initial address register and a start signal register; the central processing unit issues a chip selection register to the PCIE unit, and the central processing unit sequentially issues a length register, an initial address register and a start signal register to the corresponding DDR unit.
Further, after receiving the start signal register, the DDR unit reads the DDR data to be read out and performs caching; and DDR data to be read out cached by the DDR unit is transmitted to the PCIE unit for caching through an intercommunication interface.
Further, after the central processing unit issues the read command, the DDR data to be read out buffered by the PCIE unit is transmitted to the central processing unit through the PCIE bus.
The invention has the following beneficial effects: according to the invention, DDR data to be read is pre-read through a control command and is cached in a PCIE unit of an FPGA, and the PCIE unit is directly connected with a central processing unit through a PCIE bus. In view of the limitation of each transmission of the PCIE bus, in the prior art, the control method needs to send a read instruction to the FPGA for multiple times, and each time DDR data needs to be transmitted from the DDR unit to the PCIE unit inside the FPGA, during this period, the central processing unit is in a waiting time; the invention is different from the prior art in that all DDR data can be cached to the PCIE unit at one time through a control instruction, when the central processing unit issues a reading instruction, only the reading is required to be directly carried out in the PCIE unit, the communication time between the PCIE unit and the DDR unit in the FPGA is saved, and the DDR data reading time of the central processing unit through a PCIE bus is greatly improved.
Drawings
Fig. 1 is a schematic diagram of a device for increasing the communication rate of a PCIE-controlled DDR.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a method for increasing a DDR communication rate controlled by PCIE according to the present invention includes the following steps:
s01: the central processing unit issues a control instruction to the FPGA, the FPGA comprises a PCIE unit and M DDR units, and each DDR unit is connected with one DDR through a DDR bus; m is an integer greater than 0; the PCIE unit is connected with the central processing unit through a PCIE bus, and the DDR unit is respectively connected with each DDR through a DDR bus. According to the invention, a plurality of DDR units can be externally hung under the FPGA, and each DDR unit is connected to the corresponding DDR unit through a DDR bus.
Specifically, the control instruction of the present invention includes a chip select register, a length register, an initial address register, and a start signal register. The chip selection register is used for controlling the FPGA and the DDR unit to carry out data communication, and each DDR unit corresponds to one DDR externally hung on the FPGA. The length register is used for determining the total length of the data needing to be read in the reading period. The initial address register is used for determining the starting address of the DDR data to be read in the reading period. The start signal register is used for controlling the corresponding DDR unit to read data. The chip selection register, the length register, the initial address register and the start signal register are all control signals.
The method specifically comprises the following steps:
s011: the central processing unit sends a chip selection register to the PCIE unit;
s012: the central processing unit sequentially issues the length register, the initial address register and the start signal register to the corresponding DDR unit.
S02: after the FPGA receives the control instruction, the DDR data to be read out is cached in the FPGA. The method mainly comprises the following two steps:
s021: the DDR unit receives the length register, the initial address register and the start signal register in sequence, after the DDR unit receives the start signal register, all the registers are completely received, at the moment, the DDR data to be read out are read and cached according to specific control instructions in the length register and the initial address register;
s022: DDR data to be read out cached by the DDR unit is transmitted to the PCIE unit for caching through the intercommunication interface. The PCIE unit receives the chip selection register at the earliest, automatically establishes a data communication relation with the corresponding DDR unit after receiving the chip selection register, and transmits the DDR data to the PCIE unit for caching after the DDR data is cached and ready to be read. The inter-working interface inside the FPGA includes, but is not limited to, SerDes (Serializer-Deserializer) interface.
S03: the central processing unit issues a reading instruction to a PCIE unit in the FPGA;
s04: and after receiving the reading instruction, the PCIE unit transmits the cached DDR data to be read to the central processing unit through the PCIE bus. Because the to-be-read DDR data is completely cached in the PCIE unit, at this time, the PCIE unit may directly transmit the cached to-be-read DDR data to the central processing unit.
It is worth to be noted that, the PCIE bus has limited single transmission capability, and in the prior art, when DDR data read out by the central processing unit exceeds the word transmission range of the PCIE bus, a part of the DDR data to be read out is transmitted to the PCIE unit through the corresponding DDR unit, and the PCIE unit transmits the part of DDR data to the central processing unit; then, the rest part of the DDR data to be read is transmitted to the PCIE unit through the corresponding DDR unit, and the PCIE unit transmits the part of the DDR data to the central processing unit; the DDR data is transmitted between the DDR unit and the PCIE unit very slowly, and especially under the condition that there are many DDR data to be read, the DDR data transmission needs to be performed inside the FPGA for many times, which causes the central processing unit to waste most of the waiting time. According to the invention, through the control instruction, DDR data to be read out is cached from the corresponding DDR unit to the PCIE unit at one time, even though the transmission capability of the PCIE bus is limited, the DDR data cached in the PCIE unit only needs to be transmitted to the central processing unit for multiple times, and a large amount of time for transmission in the FPGA is saved.
The invention provides a device for improving the communication rate of PCIE (peripheral component interface express) control DDR (double data rate), which comprises a central processing unit, an FPGA (field programmable gate array) and M DDR units, wherein the FPGA comprises a PCIE unit and the M DDR units, and each DDR unit is connected with one DDR through a DDR bus; the PCIE unit is connected with the central processing unit through a PCIE bus, and the DDR unit is respectively connected with M DDR units through DDR buses; m is an integer greater than 0; the central processing unit issues a control instruction to the FPGA, and the DDR unit caches DDR data to be read into the FPGA according to the issued instruction; and the central processing unit issues a reading instruction, and DDR data cached in the FPGA is transmitted to the central processing unit through the PCIE bus.
The control instruction comprises a chip selection register, a length register, an initial address register and a starting signal register; the central processing unit issues the chip selection register to the PCIE unit, and the central processing unit sequentially issues the length register, the initial address register and the start signal register to the corresponding DDR unit. After the DDR unit receives the starting signal register, reading DDR data to be read out, and caching the DDR data; DDR data to be read out cached by the DDR unit is transmitted to the PCIE unit for caching through the intercommunication interface. After the central processing unit issues the reading instruction, the DDR data to be read and cached by the PCIE unit is transmitted to the central processing unit through the PCIE bus.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.

Claims (10)

1. A method for improving the communication rate of DDR controlled by PCIE is characterized by comprising the following steps:
s01: the central processing unit issues a control instruction to the FPGA;
s02: after the FPGA receives a control instruction, caching DDR data to be read into the FPGA;
s03: the central processing unit issues a reading instruction to the FPGA;
s04: and after receiving the reading instruction, the FPGA transmits the cached DDR data to the central processing unit through the PCIE bus.
2. The method according to claim 1, wherein the control instruction in step S01 includes a chip select register, a length register, an initial address register, and a start signal register.
3. The method of claim 2, wherein the FPGA comprises a PCIE unit and M DDR units, and each DDR unit is connected to a DDR via a DDR bus; m is an integer greater than 0; the step S01 specifically includes:
s011: the central processing unit sends a chip selection register to the PCIE unit;
s012: the central processing unit sequentially issues a length register, an initial address register and a start signal register to the corresponding DDR unit.
4. The method according to claim 3, wherein the step S02 specifically includes:
s021: after the DDR unit receives the starting signal register, reading DDR data to be read out, and caching the DDR data;
s022: and DDR data to be read out cached by the DDR unit is transmitted to the PCIE unit for caching through an intercommunication interface.
5. The method according to claim 4, wherein in step S03, the central processing unit issues a read command to the PCIE unit.
6. The method according to claim 5, wherein the PCIE unit in the step S04 transmits the cached DDR data to be read to the central processing unit through the PCIE bus after receiving the read command.
7. A device for improving the communication rate of PCIE control DDR is characterized by comprising a central processing unit, an FPGA and M DDR units, wherein the FPGA comprises a PCIE unit and M DDR units, and each DDR unit is connected with one DDR through a DDR bus; the PCIE unit is connected with the central processing unit through a PCIE bus, and the DDR unit is respectively connected with corresponding DDR through DDR buses; m is an integer greater than 0;
the central processing unit issues a control instruction to the FPGA, and the DDR unit caches DDR data to be read into the FPGA according to the issued instruction; and the central processing unit issues a reading instruction, and DDR data cached in the FPGA is transmitted to the central processing unit through a PCIE bus.
8. The apparatus according to claim 7, wherein the control command includes a chip select register, a length register, an initial address register, and a start signal register; the central processing unit issues a chip selection register to the PCIE unit, and the central processing unit sequentially issues a length register, an initial address register and a start signal register to the corresponding DDR unit.
9. The device according to claim 8, wherein the DDR unit reads the DDR data to be read out after receiving the start signal register, and buffers the DDR data; and DDR data to be read out cached by the DDR unit is transmitted to the PCIE unit for caching through an intercommunication interface.
10. The device of claim 9, wherein after the central processing unit issues the read command, the DDR data to be read buffered by the PCIE unit is transmitted to the central processing unit via a PCIE bus.
CN202010196287.5A 2020-03-19 2020-03-19 Device and method for improving communication rate of DDR controlled by PCIE Pending CN111427811A (en)

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PCT/CN2020/120842 WO2021184741A1 (en) 2020-03-19 2020-10-14 Apparatus and method for increasing communication rate of ddr controlled by means of pcie

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