CN102980648A - Real-time data acquisition and signal preprocessing equipment and method for optical fiber vibration measurement system - Google Patents
Real-time data acquisition and signal preprocessing equipment and method for optical fiber vibration measurement system Download PDFInfo
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Abstract
The invention discloses real-time data acquisition and signal preprocessing equipment and a real-time data acquisition and signal preprocessing method for an optical fiber vibration measurement system. The equipment comprises a synchronous pulse generator, a photoelectric module, an analog/digital converter, a field programmable gate array (FPGA), a first double data rate (DDR) memorizer, a second DDR memorizer and a high-performance industrial computer and is characterized in that the synchronous pulse generator is connected with the photoelectric module and the FPGA respectively; the photoelectric module is connected with the analog/digital converter; the analog/digital converter is connected with the FPGA; and the FPGA is connected with the first DDR memorizer, the second DDR memorizer and the high-performance industrial computer respectively. The equipment and the method have the advantages that the FPGA has the characteristics of high-efficiency parallel processing capability and high-efficiency flow line technology, and ping-pong mechanism is used for performing data acquisition and preprocessing on the optical fiber vibration measurement system, so the problem about the system real-time property is effectively solved.
Description
Technical field
The present invention relates to the circumference safety-security area, particularly a kind of real-time data acquisition and signal conditioning equipment and method thereof for the fiber-optic vibration measuring system.
Background technology
At present, the safety-protection system that is applied to perimeter alarm mainly comprises: microwave warning system, active infrared warning system, reveal cable perimeter alarm system, electrostatic induction perimeter alarm system and camera video recognition system etc.When above-mentioned traditional perimeter alarm system is applied in monitoring under the long distance condition, there are a lot of problems.Monitor modes such as microwave warning system or active infrared warning system can only be applicable to sighting distance and flat site, be subjected to the such environmental effects such as height, complications, turning, bending of landform very large, and they are not suitable for weather extremes, are subject to the natural climate impact, and accuracy rate is also lower.Because sensor unit generally is active, so in the situation of long distance monitoring, be difficult to solve the problem of open-air power supply, the life-span of sensor unit is also shorter simultaneously, and in the situation that long-time continuous is used, the maintenance cost of equipment is also higher.
Therefore, the orientable perimeter alarm system of long distance has obvious advantage as brand-new security device.Warning system is divided into outdoor monitoring optical cable and comprehensive treatment equipment two parts.Comprehensive treatment equipment is positioned at the Control Room machine room, divides by function, can be comprised of light source, light path output module, photoelectric switching circuit, analog-to-digital conversion module, digital signal processing module and alarm module.Its course of work is: light source is under the control of light source driving circuit, and the light that sends is processed the laggard outdoor monitor optical cable that enters through the light path output module; The light that the outdoor monitoring optical cable returns arrives after the photoelectric switching circuit, processes through analog to digital conversion and digital signal processing module; Analyze afterwards and identify disturbing signal, and then carry out corresponding alarm operation according to the analysis result to disturbing signal.
In the prior art, adopt ripe on the market capture card, to industrial computer, utilize the data acquisition of processing through analog to digital conversion and digital signal processing module industrial computer to process.This class capture card function singleness, only the data acquisition function does not have preprocessing function.In addition, industrial computer is processed and adopted software processing method, the advantage of this scheme is that algorithm is transplanted simply, and development difficulty is lower, and shortcoming is because data volume is large, and the algorithm more complicated is difficult to real-time implementation, has data loss problem.But, if processing all, data realize that with hardware development difficulty is large, the cycle is long.
Summary of the invention
In order to solve problems of the prior art, the invention provides a kind of real-time data acquisition for the fiber-optic vibration measuring system and signal conditioning equipment, in order to realize real-time data acquisition and preprocessing function, reach the purpose of real-time analysis.
In order to achieve the above object, the present invention adopts following technical scheme: the real-time data acquisition and the signal conditioning equipment that are used for the fiber-optic vibration measuring system, comprise clock-pulse generator, optical-electric module, analog to digital converter, FPGA, the one DDR storer, the 2nd DDR storer and high-performance industrial computer, it is characterized in that: described clock-pulse generator connects respectively described optical-electric module and FPGA, described optical-electric module connects described analog to digital converter, described analog to digital converter connects described FPGA, and described FPGA connects respectively a described DDR storer, the 2nd DDR storer and high-performance industrial computer.
Described clock-pulse generator, in order to the synchronization pulse that generation has certain pulsewidth of certain repetition frequency, being used for synchronous optical-electric module and FPGA(is data acquisition controller), thereby so that the useful signal that system acquisition produces to optical-electric module.Described repetition frequency can arrange.
Described optical-electric module receives in order to produce Laser emission and laser interference.When described clock-pulse generator produced pulse, the optical-electric module Emission Lasers received laser interference simultaneously, and converts thereof into the input end that electric signal outputs to analog to digital converter; When the end-of-pulsing of described clock-pulse generator, optical-electric module stops Emission Lasers, and interference light is then delayed time and finished after a period of time, and delay time is relevant with the system detection range.
Described analog to digital converter, its function are to finish analog electrical signal to the conversion of digital electric signal.
Described FPGA, its function is the functions such as data acquisition, data buffer storage, data pre-service, data output.
A described DDR storer and the 2nd DDR storer, its function is data cached.
Described high-performance industrial computer, its function are to process and analyze for data.
Further, the FPGA indoor design is by the data acquisition control unit, the first memory control module, the second memory control module, the first fft processing unit, the second fft processing unit, the preprocessed data control module, FIFO storer and PCIE interface controller form, described data acquisition control unit connects respectively clock-pulse generator, analog to digital converter, the first memory control module, second memory control module and preprocessed data control module, described the first memory controller unit connects a described DDR storer, described the second memory controller unit connects described the 2nd DDR storer, described preprocessed data control module connects respectively the first fft processing unit, the second fft processing unit and FIFO storer, described FIFO storer connects the PCIE interface controller, and described PCIE interface controller connects the high-performance industrial computer.
Described data acquisition control unit, its function are to control data acquisition flow, and switch data buffer memory passage, control data data output channel are switched.
Described first memory control module, its function are to DDR memory read/write control and to described the first fft processing unit data input control.
Described second memory control module, its function are to the control of the 2nd DDR memory read/write and to described the second fft processing unit data input control.
Described the first fft processing unit and the second fft processing unit, its function are that input data sequence is carried out the FFT conversion.
Described preprocessed data control module, its function are control the first fft processing unit and the second fft processing unit data output flow process, do not produce conflict so that the data of two unit can be exported smoothly.
Described FIFO storer, its function are the data of buffer memory the first fft processing unit and the output of the second fft processing unit, realize the effect of data first in first out.
Described PCIE interface controller, its function are to realize the control of PCIE bus interface.
The present invention a kind of real-time data acquisition and signal conditioning equipment for the fiber-optic vibration measuring system are realized collection and the pre-service of real time data as follows, reach the purpose of real-time analysis:
The first step, clock-pulse generator produces the synchronizing signal with certain pulse width and repetition frequency;
Second step, when synchronizing signal produced, the optical-electric module emission pulse laser received simultaneously effective laser interference signal and converts thereof into effective voltage signal;
In the 3rd step, analog to digital converter converts voltage signal to digital signal;
In the 4th step, FPGA gathers the digital signal of analog to digital converter output, and finishes buffer memory (being that data deposit a DDR storer or the 2nd DDR storer in), data rearrangement row, FFT conversion, exports finally by the PCIE bus;
In the 5th step, the high-performance industrial computer receives the data that FPGA sends through the PCIE bus, carries out subsequent algorithm and processes and data analysis.
Because the native system data volume is large, data sampling rate is high, in order to reach the purpose of live signal acquisition and processing, adopt table tennis data buffer storage and pretreated mode in above-mentioned the 4th step, its principle is: supposition system acquisition M bar length is the curve data of N, the two-dimensional array that forms a M * N, the i.e. matrix of M * N; For example, when system's detection length is 50km, get M * N=512x50000; Then the M that collects * N two-dimensional array is carried out matrix transpose, obtains the array of M * N; Each row to this two-dimensional array of changing carries out the FFT conversion, then analyzes; So just can analyze each position in system's detection range scope.Because system needs real-time data collection and processing, therefore adopt table tennis data acquisition and processing (DAP) mode; But matrix transpose and FFT are more consuming time, and for this multitask system of computing machine, processing power is very limited; On the other hand, matrix transpose and FFT are fit to pipeline processing mode, and FPGA has efficient parallel processing capability and high performance pipeline technology, so this part data processing adopts FPGA to process proper.The specific implementation process is as follows:
In the 41st step, (1) when FPGA received synchronization pulse, the data acquisition control unit began to gather one group of data (data length is N, N=50 for example, 000), and by the first memory control module data was deposited in a DDR storer;
(2) the number of times K that synchronization pulse is produced counts;
(3) when synchronization pulse generation number of times K reached the threshold value M (such as M=512) of default, at this moment, a DDR storer had been stored a two-dimensional array, comprises M * N data; At this moment, synchronization pulse is produced number of times K zero clearing, changed for the 42nd step over to;
The 42nd step, the executed in parallel following functions:
(1) when FPGA receives synchronization pulse, the data acquisition control unit begins to gather one group of data (data length is N, N=50 for example, 000), and by the second memory control module data is deposited in the 2nd DDR storer;
(2) two-dimensional array stored from a DDR storer of first memory control module is by the sequential access certificate of row, and every column data length is M, altogether the N row; These are sent into the first fft processing unit in order by the data that row take out;
(3) first fft processing units begin every column data is carried out the FFT conversion, and its result enters the preprocessed data control module;
(4) the preprocessed data control module writes the FIFO storer to the data of the first fft processing unit output;
(5) when detecting the FIFO storer data are arranged, PCIE interface controller reading out data also uploads to the high-performance industrial computer by the PCIE bus;
(6) the number of times K that synchronization pulse is produced counts;
When the number of times K that (7) produces when synchronization pulse reached the threshold value M (such as M=512) of default, at this moment, the 2nd DDR storer had been stored a two-dimensional array, comprises M * N data; Because FPGA has efficient parallel processing capability and high performance pipeline technology, the two-dimensional array of storing in the one DDR storer this moment all be read and finish the FFT conversion, its result has been uploaded to the high-performance industrial computer; At this moment, the number of times zero clearing that synchronization pulse is produced; Changed for the 43rd step over to;
The 43rd step, the executed in parallel following functions:
(1) when FPGA receives synchronization pulse, the data acquisition control unit begins to gather one group of data (data length is N, N=50 for example, 000), and by the first memory control module data is deposited in a DDR storer;
(2) two-dimensional array stored from the 2nd DDR storer of second memory control module is by the sequential access certificate of row, and every column data length is M, altogether the N row; These are sent into the second fft processing unit in order by the data that row take out;
(3) second fft processing units begin every column data is carried out the FFT conversion, and its result enters the preprocessed data control module;
(4) the preprocessed data control module writes the FIFO storer to the data of the second fft processing unit output;
(5) when detecting the FIFO storer data are arranged, PCIE interface controller reading out data also uploads to the high-performance industrial computer by the PCIE bus;
(6) the number of times k that synchronization pulse is produced counts;
When the number of times K that (7) produces when synchronization pulse reached the threshold value M (such as M=512) of default, at this moment, a DDR storer had been stored a two-dimensional array, comprises M * N data; Because FPGA has efficient parallel processing capability and high performance pipeline technology, the two-dimensional array of storing in the 2nd DDR storer this moment all be read and finish the FFT conversion, its result has been uploaded to the high-performance industrial computer; At this moment, the number of times zero clearing that synchronization pulse is produced; Changed for the 42nd step over to;
In the 44th step, repeat above-mentioned the 42nd step and the 43rd step, until system stops data acquisition.
Beneficial effect of the present invention is: utilize FPGA to have efficient parallel processing capability and high performance pipeline technical characterstic, adopt ping-pong mechanism that the fiber-optic vibration measuring system is carried out data acquisition and pre-service, effectively solved the system real time problem.
Description of drawings
Fig. 1 is structural representation of the present invention.
Embodiment
As shown in Figure 1, a kind of real-time data acquisition and signal conditioning equipment for the fiber-optic vibration measuring system, comprise clock-pulse generator 1, optical-electric module 2, analog to digital converter 3, FPGA4, the one DDR storer 5, the 2nd DDR storer 6 and high-performance industrial computer 7, described clock-pulse generator 1 connects respectively described optical-electric module 2 and FPGA4, described optical-electric module 2 connects described analog to digital converter 3, described analog to digital converter 3 connects described FPGA4, and described FPGA4 connects respectively a described DDR storer 5, the 2nd DDR storer 6 and high-performance industrial computer 7.
Further, the FPGA4 indoor design is by data acquisition control unit 41, first memory control module 42, second memory control module 43, the first fft processing unit 44, the second fft processing unit 45, preprocessed data control module 46, FIFO storer 47 and PCIE interface controller 48 form, described data acquisition control unit 41 connects respectively clock-pulse generator 1, analog to digital converter 3, first memory control module 42, second memory control module 43 and preprocessed data control module 46, described the first memory controller unit 42 connects a described DDR storer 5, described the second memory controller unit 43 connects described the 2nd DDR storer 6, described preprocessed data control module 46 connects respectively the first fft processing unit 44, the second fft processing unit 45 and FIFO storer 47, described FIFO storer 47 connects PCIE interface controller 48, and described PCIE interface controller 48 connects high-performance industrial computer 7.
A kind of implementation method of real-time data acquisition and the signal conditioning equipment for the fiber-optic vibration measuring system, its implementation step is as follows:
The first step, clock-pulse generator 1 produces the synchronizing signal with certain pulse width and repetition frequency;
Second step, when synchronizing signal produced, optical-electric module 2 emission pulse lasers received simultaneously effective laser interference signal and convert effective voltage signal to by analog to digital converter 3;
In the 3rd step, analog to digital converter 3 converts voltage signal to digital signal;
In the 4th step, FPGA 4 gathers the digital signal of analog to digital converters 3 outputs, and finishes buffer memory, data rearrangement row, FFT conversion, exports finally by the PCIE bus;
In the 5th step, high-performance industrial computer 7 receives the data that FPGA 4 sends through the PCIE bus, carries out subsequent algorithm and processes and data analysis.
Above-mentioned the 4th step has been adopted table tennis data buffer storage and pretreatment mode, and its principle is as follows:
Suppose that system acquisition M bar length is the curve data of N, form the two-dimensional array of a M * N, i.e. the matrix of M * N; For example, when system's detection length is 50km, get M * N=512 * 50000; Then carry out matrix transpose to collecting M * N two-dimensional array, obtain the array of N * M; At last the FFT conversion is carried out in each row of this two-dimensional array of changing, then analyze; So just can analyze each position in system's detection range scope.The specific implementation process is as follows:
In the 41st step, when (1) received synchronization pulse as FPGA 4, data acquisition control unit 41 began to gather one group of data (data length is N, N=50 for example, 000), and by first memory control module 42 data was deposited in a DDR storer 5;
(2) the number of times K that synchronization pulse is produced counts;
(3) when synchronization pulse generation number of times K reached the threshold value M (such as M=512) of default, at this moment, a DDR storer 5 had been stored a two-dimensional array, comprises M * N data; At this moment, synchronization pulse is produced number of times K zero clearing, changed for the 42nd step over to;
The 42nd step, the executed in parallel following functions:
(1) when FPGA 4 receives synchronization pulse, data acquisition control unit 41 begins to gather one group of data (data length is N, N=50 for example, 000), and by second memory control module 43 data is deposited in the 2nd DDR storer 6;
(2) two-dimensional array stored from a DDR storer 5 of first memory control module 42 is by the sequential access certificate of row, and every column data length is M, altogether the N row; These are sent into the first fft processing unit 44 in order by the data that row take out;
(3) first fft processing units 44 begin every column data is carried out the FFT conversion, and its result enters preprocessed data control module 46;
(4) preprocessed data control module 46 writes FIFO storer 47 to the data of the first fft processing unit 44 outputs;
(5) when detecting FIFO storer 47 data are arranged, PCIE interface controller 48 reading out datas also upload to the high-performance industrial computer by the PCIE bus;
(6) the number of times K that synchronization pulse is produced counts;
When the number of times K that (7) produces when synchronization pulse reached the threshold value M (such as M=512) of default, at this moment, the 2nd DDR storer 6 had been stored a two-dimensional array, comprises M * N data; Because FPGA 4 has efficient parallel processing capability and high performance pipeline technology, in this moment the one DDR storer 5 two-dimensional array of storage all be read and finish the FFT conversion, its result has been uploaded to high-performance industrial computer 7; At this moment, the number of times zero clearing that synchronization pulse is produced; Changed for the 43rd step over to;
The 43rd step, the executed in parallel following functions:
(1) when FPGA 4 receives synchronization pulse, data acquisition control unit 41 begins to gather one group of data (data length is N, N=50 for example, 000), and by first memory control module 42 data is deposited in a DDR storer 5;
(2) two-dimensional array stored from the 2nd DDR storer 6 of second memory control module 43 is by the sequential access certificate of row, and every column data length is M, altogether the N row; These are sent into the second fft processing unit 45 in order by the data that row take out;
(3) second fft processing units 45 begin every column data is carried out the FFT conversion, and its result enters preprocessed data control module 46;
(4) preprocessed data control module 46 writes FIFO storer 47 to the data of the second fft processing unit 45 outputs;
(5) when detecting FIFO storer 47 data are arranged, PCIE interface controller 48 reading out datas also upload to the high-performance industrial computer by the PCIE bus;
(6) the number of times k that synchronization pulse is produced counts;
When the number of times K that (7) produces when synchronization pulse reached the threshold value M (such as M=512) of default, at this moment, a DDR storer 5 had been stored a two-dimensional array, comprises M * N data; Because FPGA 4 has efficient parallel processing capability and high performance pipeline technology, in this moment the 2nd DDR storer 6 two-dimensional array of storage all be read and finish the FFT conversion, its result has been uploaded to high-performance industrial computer 7; At this moment, the number of times zero clearing that synchronization pulse is produced; Changed for the 42nd step over to;
In the 44th step, repeat above-mentioned the 42nd step and the 43rd step, until system stops data acquisition;
Although the present invention discloses as above with preferred embodiment, so it is not to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, can do various distortion to the present invention, all belong to protection scope of the present invention.
Claims (5)
1. real-time data acquisition and signal conditioning equipment that is used for the fiber-optic vibration measuring system, comprise clock-pulse generator, optical-electric module, analog to digital converter, FPGA, a DDR storer, the 2nd DDR storer and high-performance industrial computer, it is characterized in that: described clock-pulse generator connects respectively described optical-electric module and FPGA, described optical-electric module connects described analog to digital converter, described analog to digital converter connects described FPGA, and described FPGA connects respectively a described DDR storer, the 2nd DDR storer and high-performance industrial computer.
2. real-time data acquisition and signal conditioning equipment for the fiber-optic vibration measuring system according to claim 1, it is characterized in that: described FPGA indoor design is by the data acquisition control unit, the first memory control module, the second memory control module, the first fft processing unit, the second fft processing unit, the preprocessed data control module, FIFO storer and PCIE interface controller form, described data acquisition control unit connects respectively clock-pulse generator, analog to digital converter, the first memory control module, second memory control module and preprocessed data control module, described the first memory controller unit connects a described DDR storer, described the second memory controller unit connects described the 2nd DDR storer, described preprocessed data control module connects respectively the first fft processing unit, the second fft processing unit and FIFO storer, described FIFO storer connects the PCIE interface controller, and described PCIE interface controller connects the high-performance industrial computer.
3. one kind is used for the real-time data acquisition of fiber-optic vibration measuring system and the implementation method of signal conditioning equipment, comprises the steps:
The first step, clock-pulse generator produces the synchronizing signal with certain pulse width and repetition frequency;
Second step, when synchronizing signal produced, the optical-electric module emission pulse laser received simultaneously effective laser interference signal and converts thereof into effective voltage signal;
In the 3rd step, analog to digital converter converts voltage signal to digital signal;
In the 4th step, FPGA gathers the digital signal of analog to digital converter output, and finishes buffer memory (being that data deposit a DDR storer or the 2nd DDR storer in), data rearrangement row, FFT conversion, exports finally by the PCIE bus;
In the 5th step, the high-performance industrial computer receives the data that FPGA sends through the PCIE bus, carries out subsequent algorithm and processes and data analysis.
4. method according to claim 3 is characterized in that: described the 4th step employing table tennis data buffer storage and pretreated mode.
5. method according to claim 4, it is characterized in that: described table tennis data buffer storage and pretreated mode performing step comprise:
The 41st step:
(1) when FPGA receives synchronization pulse, the data acquisition control unit begins to gather one group of data, and by the first memory control module data is deposited in a DDR storer;
(2) number of times that synchronization pulse is produced is counted;
(3) when synchronization pulse generation number of times reached the threshold value of default, at this moment, a DDR storer had been stored a two-dimensional array, at this moment, synchronization pulse was produced the number of times zero clearing, changed for the 42nd step over to;
The 42nd step: the following function of executed in parallel:
(1) when FPGA receives synchronization pulse, the data acquisition control unit begins to gather one group of data, and by the second memory control module data is deposited in the 2nd DDR storer;
(2) two-dimensional array stored from a DDR storer of first memory control module is sent into the first fft processing unit to these by data that row take out in order by the sequential access certificate of row;
(3) first fft processing units begin every column data is carried out the FFT conversion, and its result enters the preprocessed data control module;
(4) the preprocessed data control module writes the FIFO storer to the data of the first fft processing unit output;
(5) when detecting the FIFO storer data are arranged, PCIE interface controller reading out data also uploads to the high-performance industrial computer by the PCIE bus;
(6) number of times that synchronization pulse is produced is counted;
When the number of times that (7) produces when synchronization pulse reached the threshold value of default, at this moment, the 2nd DDR storer had been stored a two-dimensional array; Because FPGA has efficient parallel processing capability and high performance pipeline technology, the two-dimensional array of storing in the one DDR storer this moment all be read and finish the FFT conversion, its result has been uploaded to the high-performance industrial computer; At this moment, the number of times zero clearing that synchronization pulse is produced; Changed for the 43rd step over to;
The 43rd step: the following function of executed in parallel:
(1) when FPGA receives synchronization pulse, the data acquisition control unit begins to gather one group of data, and by the first memory control module data is deposited in a DDR storer;
(2) two-dimensional array stored from the 2nd DDR storer of second memory control module is sent into the second fft processing unit to these by data that row take out in order by the sequential access certificate of row;
(3) second fft processing units begin every column data is carried out the FFT conversion, and its result enters the preprocessed data control module;
(4) the preprocessed data control module writes the FIFO storer to the data of the second fft processing unit output;
(5) when detecting the FIFO storer data are arranged, PCIE interface controller reading out data also uploads to the high-performance industrial computer by the PCIE bus;
(6) number of times that synchronization pulse is produced is counted;
When the number of times that (7) produces when synchronization pulse reached the threshold value of default, at this moment, a DDR storer had been stored a two-dimensional array; Because FPGA has efficient parallel processing capability and high performance pipeline technology, the two-dimensional array of storing in the 2nd DDR storer this moment all be read and finish the FFT conversion, its result has been uploaded to the high-performance industrial computer; At this moment, the number of times zero clearing that synchronization pulse is produced; Changed for the 42nd step over to;
The 44th step: repeat above-mentioned the 42nd step and the 43rd step, until system stops data acquisition.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109634880A (en) * | 2018-12-12 | 2019-04-16 | 广东浪潮大数据研究有限公司 | A kind of data acquisition equipment, data interaction equipment and data collection system |
| CN109839477A (en) * | 2017-11-24 | 2019-06-04 | 内蒙古光能科技有限公司 | A kind of method that CRDS gas concentration detector accelerates measurement |
| WO2021184741A1 (en) * | 2020-03-19 | 2021-09-23 | 上海御渡半导体科技有限公司 | Apparatus and method for increasing communication rate of ddr controlled by means of pcie |
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2012
- 2012-12-06 CN CN 201210516987 patent/CN102980648A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109839477A (en) * | 2017-11-24 | 2019-06-04 | 内蒙古光能科技有限公司 | A kind of method that CRDS gas concentration detector accelerates measurement |
| CN109634880A (en) * | 2018-12-12 | 2019-04-16 | 广东浪潮大数据研究有限公司 | A kind of data acquisition equipment, data interaction equipment and data collection system |
| WO2021184741A1 (en) * | 2020-03-19 | 2021-09-23 | 上海御渡半导体科技有限公司 | Apparatus and method for increasing communication rate of ddr controlled by means of pcie |
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Application publication date: 20130320 |