CN204143431U - The low delayed data of a kind of high speed gathers totalizer - Google Patents
The low delayed data of a kind of high speed gathers totalizer Download PDFInfo
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- CN204143431U CN204143431U CN201420628801.8U CN201420628801U CN204143431U CN 204143431 U CN204143431 U CN 204143431U CN 201420628801 U CN201420628801 U CN 201420628801U CN 204143431 U CN204143431 U CN 204143431U
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Abstract
The utility model discloses the low delayed data of a kind of high speed and gather totalizer, comprise high-speed data load module and extensive field programmable gate array module, it is characterized in that: described high-speed data load module comprises analog-to-digital conversion module, for simulating signal to be processed digital signal need be converted into; Described extensive field programmable gate array module is made up of register cell, accumulator element, data selection unit, dual port RAM unit, control module and cell fifo.The low delayed data of a kind of high speed that the utility model provides gathers totalizer, make use of the ability of extensive on-site programmable gate array internal rich in natural resources and its high-speed parallel process, processing speed quickly, high-speed data acquisition and the operation of mass data accumulation process function parallelization can be realized, synchronism output cumulative data, there is lower delay, DTS system response time can be improved, and be beneficial to the raising of spatial resolution index.
Description
Technical field
The utility model relates to the low delayed data of a kind of high speed and gathers totalizer, belongs to technical field of integrated circuits.
Background technology
In fiber optic sensing applications, especially in temperature-measuring system of distributed fibers (DTS system), owing to needing the Raman scattering signal of detection very faint, be submerged in completely in noise, system needs to adopt Weak Signal Detection to extract measured signal from noise.Be example in DTS system, in DTS system, the principal ingredient of noise is white noise, and it has the statistical property of zero-mean, can in utilizing the statistical property of noise to reach the object of noise reduction.Therefore, for improving signal to noise ratio (S/N ratio), signal transacting adopts the disposal route of image data being carried out digital averaging, by the N(of one-shot measurement as N=20000) point data is stored into successively in internal storage location, the N point data next time measured is added with the data of corresponding internal storage location, then puts back to former internal storage location, circulation M(is as M=10000 successively) secondary, then each internal storage location data are averaging, carry out temperature demodulation calculating, obtain each point actual temperature.DTS system is for ensureing that certain space resolution need in being greater than 100MHz sampling rate image data simultaneously, and therefore DTS system must realize high-speed data acquisition and mass data accumulation process function.
Because data in DTS system are average and temperature demodulation evaluation work difficulty is little, institute is in technical bottleneck mainly in high-speed data acquisition and mass data accumulation process, and namely DTS system must use high-speed data acquisition totalizer.Current DTS system has two kinds of high-speed data acquisition totalizers.The first first completes high-speed data acquisition function, and then complete mass data accumulation process function, namely first the data that high-speed data acquisition is got off are stored into Large Copacity internal memory, stop gathering after completing the collection of NxM point data, then carry out mass data to add up, complete after adding up, each point cumulative data can be exported, this mode is serial processing mode, and larger delay must be needed finally could to obtain valid data.Simultaneously the second carries out data accumulation process in high-speed data acquisition, devise more complicated structure and flow process for this reason, complete after adding up, each point cumulative data can be exported, though this mode is a kind of parallel processing manner, and also devises more complicated structure and flow process, but also there is expense extra time, as RAM initialization clearing, data delay alignment etc., some delays must be needed finally could to obtain valid data.The delay produced in upper two kinds of high-speed data acquisition totalizers will affect DTS system response time, and affect the raising of spatial resolution index.
Utility model content
Object: in order to overcome the deficiencies in the prior art, the utility model provides the low delayed data of a kind of high speed to gather totalizer.
Technical scheme: for solving the problems of the technologies described above, the technical solution adopted in the utility model is:
The low delayed data of a kind of high speed gathers totalizer, and comprise high-speed data load module and extensive field programmable gate array module, described high-speed data load module comprises analog-to-digital conversion module, for simulating signal to be processed being converted into digital signal; Described extensive field programmable gate array module is made up of register cell, accumulator element, data selection unit, dual port RAM unit, control module and cell fifo;
Described register cell comprises: the first register cell and the second register cell;
Described register cell is used for data cached; Described first register cell is connected with control module with described high-speed data load module, accumulator element, passes to accumulator element for the output data high-speed data load module; Described second register cell is connected with control module with data selection unit, dual port RAM unit, passes to dual port RAM unit for the output data data selection unit;
Described accumulator element is connected with dual port RAM unit with the first register cell, data selection unit, add up, and the output that will add up is sent in described data selection unit for the first register cell output data and dual port RAM unit are exported data;
Described data selection unit is connected with control module with accumulator element, the second register cell, cell fifo, for selecting the cumulative output of accumulator element or numerical value 0 stored in the second register cell, select the cumulative output of accumulator element or numerical value 0 stored in cell fifo;
Described dual port RAM unit is connected with control module with the second register cell, accumulator element, reads while write function for realizing data, and sense data is sent into described accumulator element and the second register cell data write in the corresponding units of dual port RAM;
Described control module is connected with cell fifo with the first register cell, data selection unit, the second register cell, dual port RAM unit, for providing synchronous read-write sequence to control to the first register cell, data selection unit, the second register cell, dual port RAM unit and cell fifo, providing to dual port RAM unit and reading address and write address;
Described cell fifo is connected with control module with data selection unit, for data selection unit being exported in data write FIFO.
The low delayed data of a kind of high speed gathers totalizer operation method, comprises the steps:
Step one: the output data of high-speed data load module, under control module controls, arrive accumulator element after the first register cell;
Step 2: simultaneously carry out with step one, the data that control module controls dual port RAM unit export arrival accumulator element;
Step 3: simultaneously carry out with step one, control module controls the cumulative output (namely go up a beat accumulation result) of accumulator element and numerical value 0 stored in the second register cell after data selection unit selection, the cumulative output (namely going up a beat accumulation result) of accumulator element and numerical value 0 after data selection unit selection stored in cell fifo;
Step 4: simultaneously carry out with step one, control module controls the second register cell data (i.e. a upper beat accumulation result) to write in the corresponding units of dual port RAM unit;
Step 5: simultaneously carry out with step one, after control module controls output, reads address and write address change, prepares next beat address;
Through once described step one to five, complete the storage of once the gathering an of point data, cumulative and accumulation result; The storage of once the gathering of N point data, cumulative and accumulation result is completed through N above-mentioned steps; Repeat said process M to gather all over M time of completing N point data, add up and the storage of accumulation result; After M starts all over process, each point cumulative data can by FIFO synchronism output.
Beneficial effect: the low delayed data of a kind of high speed that the utility model provides gathers totalizer, make use of the ability of extensive on-site programmable gate array internal rich in natural resources and its high-speed parallel process, processing speed quickly, high-speed data acquisition and the operation of mass data accumulation process function parallelization can be realized, synchronism output cumulative data, there is lower delay, DTS system response time can be improved, and be beneficial to the raising of spatial resolution index.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
As shown in Figure 1, the low delayed data of a kind of high speed gathers totalizer, comprise high-speed data load module 1 and extensive field programmable gate array module 2, described high-speed data load module 1 comprises analog-to-digital conversion module, for simulating signal to be processed being converted into digital signal; Described extensive field programmable gate array module 2 is made up of register cell, accumulator element 22, data selection unit 23, dual port RAM unit 25, control module 26 and cell fifo 27;
Described register cell comprises: the first register cell 21 and the second register cell 24;
Described register cell is used for data cached; Described first register cell 21 is connected with control module 26 with described high-speed data load module 1, accumulator element 22, passes to accumulator element 22 for the output data high-speed data load module 1; Described second register cell 24 is connected with control module 26 with data selection unit 23, dual port RAM unit 25, passes to dual port RAM unit 25 for the output data data selection unit 23;
Described accumulator element 22 is connected with dual port RAM unit 25 with the first register cell 21, data selection unit 23, export data add up for the first register cell 21 being exported data and dual port RAM unit 25, and will add up to export and send in described data selection unit 23;
Described data selection unit 23 is connected with control module 26 with accumulator element 22, second register cell 24, cell fifo 27, for selecting the cumulative output of accumulator element 22 or numerical value 0 stored in the second register cell 24, select the cumulative output of accumulator element 22 or numerical value 0 stored in cell fifo 27;
Described dual port RAM unit 25 is connected with control module 26 with the second register cell 24, accumulator element 22, read while write function for realizing data, sense data is sent into described accumulator element 23 and the second register cell 24 data is write in the corresponding units of dual port RAM;
Described control module 26 is connected with cell fifo 27 with the first register cell 24, data selection unit 23, second register cell 24, dual port RAM unit 25, for providing synchronous read-write sequence to control to the first register cell 21, data selection unit 23, second register cell 24, dual port RAM unit 25 and cell fifo 27, providing to dual port RAM unit 25 and reading address and write address;
Described cell fifo 27 is connected with control module 26 with data selection unit 23, for data selection unit 23 being exported in data write FIFO.
The low delayed data of a kind of high speed gathers totalizer operation method, comprises the steps:
Step one: the output data of high-speed data load module, under control module controls, arrive accumulator element after the first register cell;
Step 2: simultaneously carry out with step one, the data that control module controls dual port RAM unit export arrival accumulator element;
Step 3: simultaneously carry out with step one, control module controls the cumulative output (namely go up a beat accumulation result) of accumulator element and numerical value 0 stored in the second register cell after data selection unit selection, the cumulative output (namely going up a beat accumulation result) of accumulator element and numerical value 0 after data selection unit selection stored in cell fifo;
Step 4: simultaneously carry out with step one, control module controls the second register cell data (i.e. a upper beat accumulation result) to write in the corresponding units of dual port RAM unit;
Step 5: simultaneously carry out with step one, after control module controls output, reads address and write address change, prepares next beat address;
Through once described step one to five, complete the storage of once the gathering an of point data, cumulative and accumulation result; The storage of once the gathering of N point data, cumulative and accumulation result is completed through N above-mentioned steps; Repeat said process M to gather all over M time of completing N point data, add up and the storage of accumulation result; After M starts all over process, each point cumulative data can by FIFO synchronism output.
Only preferred implementation of the present utility model described in upper; be noted that for those skilled in the art; under the prerequisite not departing from the utility model principle; also can in making some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (1)
1. the low delayed data of high speed gathers totalizer, comprise high-speed data load module and extensive field programmable gate array module, it is characterized in that: described high-speed data load module comprises analog-to-digital conversion module, for simulating signal to be processed digital signal need be converted into; Described extensive field programmable gate array module is made up of register cell, accumulator element, data selection unit, dual port RAM unit, control module and cell fifo;
Described register cell comprises: the first register cell and the second register cell;
Described register cell is used for data cached; Described first register cell is connected with control module with described high-speed data load module, accumulator element, passes to accumulator element for the output data high-speed data load module; Described second register cell is connected with control module with data selection unit, dual port RAM unit, passes to dual port RAM unit for the output data data selection unit;
Described accumulator element is connected with dual port RAM unit with the first register cell, data selection unit, add up, and the output that will add up is sent in described data selection unit for the first register cell output data and dual port RAM unit are exported data;
Described data selection unit is connected with control module with accumulator element, the second register cell, cell fifo, for selecting the cumulative output of accumulator element or numerical value 0 stored in the second register cell, select the cumulative output of accumulator element or numerical value 0 stored in cell fifo;
Described dual port RAM unit is connected with control module with the second register cell, accumulator element, reads while write function for realizing data, and sense data is sent into described accumulator element and the second register cell data write in the corresponding units of dual port RAM;
Described control module is connected with cell fifo with the first register cell, data selection unit, the second register cell, dual port RAM unit, for providing synchronous read-write sequence to control to the first register cell, data selection unit, the second register cell, dual port RAM unit and cell fifo, providing to dual port RAM unit and reading address and write address;
Described cell fifo is connected with control module with data selection unit, for data selection unit being exported in data write FIFO.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104360831A (en) * | 2014-10-28 | 2015-02-18 | 南京河海南自水电自动化有限公司 | High-speed and low-latency data collection accumulator and operation method thereof |
| CN107124240A (en) * | 2017-04-11 | 2017-09-01 | 深圳航天科技创新研究院 | A kind of channel delay analogue means and method |
| CN107220023A (en) * | 2017-06-29 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | A kind of embedded configurable FIFO memory |
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2014
- 2014-10-28 CN CN201420628801.8U patent/CN204143431U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104360831A (en) * | 2014-10-28 | 2015-02-18 | 南京河海南自水电自动化有限公司 | High-speed and low-latency data collection accumulator and operation method thereof |
| CN107124240A (en) * | 2017-04-11 | 2017-09-01 | 深圳航天科技创新研究院 | A kind of channel delay analogue means and method |
| CN107220023A (en) * | 2017-06-29 | 2017-09-29 | 中国电子科技集团公司第五十八研究所 | A kind of embedded configurable FIFO memory |
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