CN104317752B - The extendible conditional of a kind of passage triggers high speed synchronous sample register system - Google Patents
The extendible conditional of a kind of passage triggers high speed synchronous sample register system Download PDFInfo
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Abstract
The invention discloses the extendible conditional of a kind of passage and trigger high speed synchronous sample register system, comprise clock module, acquisition module, memory module and mainboard controller, clock module, acquisition module, memory module by PCIE interface and mainboard controller interconnected, clock module can export accurate synchronizing clock signals and synchronous triggering signal, acquisition module is driven to carry out high speed synchronous sample to input simulating signal, the data collected are high speed writein memory module permanent storage under mainboard controller, wherein clock signal frequency, trigger pip source can be arranged, the decision signal incoming clock module realization condition formula that acquisition module exports triggers.Compared with prior art, advantages such as there is channel expansion, gather synchronous, conditional triggerings, various ways collection, secondary development facilitates, Human-computer Interactive Design is simple.
Description
Technical field
The present invention is specifically related to data acquisition logging system technical field, particularly relate to obtain at large scale array Large Copacity signal parallel to need that module is expanded under environment, effective acquisition useful data and gather synchronous data acquisition logging system.
Background technology
The high speed acquisition system worldwide researched and developed at present, major part adopts fpga chip to control A/D chip and realizes data acquisition, chooses chip, project organization etc. for particular demands.The collection that the acquisition system researched and developed mainly concentrates on some association area signal specific and the design be integrated on veneer.And there is specific function or be integrated in the acquisition system of veneer, as distributed POS IMU data acquisition system (DAS), muti-channel data acquisition system etc., different according to function, there is special structure, lack versatility.
Existing most of multi-channel high-speed synchronous acquisition register system all adopts single board design pattern, all acquisition channels by actual demand design on a circuit back panel, use single or multiple FPGA control algorithm unit to carry out Data Control, then send data to cell stores by standard interface.Such design versatility is poor, acquisition channel is difficult to expansion, gather control and Human-computer Interactive Design more complicated.Especially when needs are expanded on a large scale, as roads up to a hundred synchronous acquisition, regarded as output controlling difficulty can be larger, often need to redesign.On the other hand, if stored the carrying out of the signal data collected not in addition selection check, will obtain much useless signal, this can improve follow-up to storing the data difficulty of analyzing and processing and workload more greatly.
Summary of the invention
For overcoming the deficiencies in the prior art, the invention provides the extendible conditional of a kind of passage and trigger high speed synchronous sample register system, it mainly comprises clock module, acquisition module, memory module and mainboard controller, each module interface all adopts general international standard agreement, and quantity can arbitrary extension; And decision signal is added between Data acquisition and storage, the data conditional collected is triggered and stores.Compared with prior art, be first the lifting of extended capability, system can each module expansion in mainboard, also can integral extension, the in addition standardization of each interface between mainboard, thus the system Multi-channel extension of making is more prone to, and secondary development is also convenient; Secondly, between collection and storage, add conditional trigger pip, by carrying out statistical decision to received signal, not only with good conditionsily can give up invalid signals, and the sampling rate to signal specific such as periodic signals can be improved.
The present invention carries out synchronous acquisition record to multi-channel electronic signal, the collection of the multiple acquisition mode such as can carry out monostable triggering under the multiple trigger source such as keyboard, outer signal, GPS moment, conditional triggering controls, self-recoverage triggers, monostablely trigger, self-recoverage triggers again again, acquisition channel can be expanded on a large scale.The present invention mainly comprises clock module, acquisition module, memory module and mainboard controller etc., and each module interface all adopts universal standard agreement, can carry out the acquisition channel expansion in mainboard and between mainboard.The present invention is used for the electronic signal high speed acquisition record in modern radar detection, communication, sensor network, uranology observation, and especially hyperchannel receives, requires in the system of synchronous acquisition record.Under the multiple acquisition mode that conditional triggers, can obtain more efficient data, facilitate next step data reprocessing, the Large Copacity characteristics of signals research got for walking abreast in large scale array and proof of algorithm provide convenience.
The extendible conditional of a kind of passage triggers high speed synchronous sample register system, comprise clock module, acquisition module, memory module and mainboard controller, clock module, acquisition module, memory module by PCIE interface and mainboard controller interconnected, clock module can export accurate synchronizing clock signals and synchronous triggering signal, acquisition module is driven to carry out high speed synchronous sample to input simulating signal, the data collected are high speed writein memory module permanent storage under mainboard controller, wherein clock signal frequency, trigger pip source can be arranged, the decision signal incoming clock module realization condition formula that acquisition module exports triggers,
When system carries out acquisition channel expansion in mainboard, acquisition module, memory module expand according to the PCIE pocket numbers in mainboard controller, increase acquisition channel quantity; Simultaneously in mainboard controller, set up triggering selection controller, mainboard controller is interconnected by serial ports and triggering selection controller, decision signal input clock module after triggering selection controller is selected of multiple acquisition module, the triggering of realization condition formula;
When system to carry out between mainboard acquisition channel expansion, system sets up top layer mainboard controller and top layer clock module, and top layer mainboard controller is interconnected by serial ports and triggering selection controller, top layer mainboard controller pass through PCIE interface and top layer clock module interconnected; Mainboard controller together with clock module, acquisition module, memory module entirety copy expand to multiple; Each mainboard controller realizes cross interconnected by IB interface under IB switch; Top controller controls triggering selection controller and top layer clock module, triggering selection controller can be selected decision signal to trigger top layer clock module and export trigger pip, trigger each mainboard controller clock module and export next stage trigger pip, trigger each acquisition channel and carry out data storage.
Acquisition module uses fpga chip as control and arithmetic element, its peripheral hardware comprises high-speed AD chip, precision clock chip, Large Copacity SDRAM and Flash chip, one piece of fpga chip can peripheral hardware multi-channel A/D, polylith SDRAM, collection plate is integrated with external clock input simultaneously, external trigger input, decision signal export and PCIE interface.
Fpga chip comprises data uplink module and descending control module, also comprise A/D chip and the PCIE data interconnection module of its peripheral hardware, data uplink module in charge synchronous data sampling, data synchronization transmissions, packing and data buffer storage along separate routes, after data enter fpga chip, data preprocessing module in data uplink module carries out pre-service to the signal that each road gathers, pre-service comprises gain calibration, direct current is calibrated, forward sight buffer memory, statistical decision gauge is calculated, Digital Down Convert and data packing etc., in the effective situation of trigger pip, data are packed, then SDRAM buffer memory is entered by route test, data from SDRAM out after, with heat alarm, the data such as overflow alarm signal carry out frame packing, uploaded by PCIE interface.Descending control module comprises on-chip bus and Parasites Fauna, and descending control module adopts bus protocol on standard film, reasonable distribution control register group address, the steering order that significant response mainboard controller sends.
The data control logic structure of data preprocessing module.Mainly comprise AD data receiver, forward sight FIFO buffer memory, data calibration, DDC and data bit adjusting module.After image data enters FPGA, two-way is divided to process respectively: the calculation of statistical decision gauge is carried out on a road, enter statistical decision gauge and calculate logic module, the weighted sum that can arrange length, adjustable weights is carried out to image data, then the decision threshold arranged with large I compares, export decision signal and obtain decision signal output, the decision signal of output enters clock module by triggering selection controller, and then the collection of control data; Another road of the data collected enters forward sight FIFO, from forward sight FIFO out after through calibration, DDC, data bit adjustment after carry out data packing, data packing to carry out under same trigger pip.
Trigger collection source in FPGA can adopt keyboard, outer signal, GPS moment, conditional triggering etc.
Acquisition mode in FPGA can adopt monostable triggering, self-recoverage triggers, monostable triggering and self-recoverage again trigger again.
The present invention is channel expansion in Solving Multichannel high speed synchronous sample register system, gathers the problems such as synchronous, establishes a high-speed synchronous register system adopting general-purpose interface, modular extendable, conditional to trigger.This system exports accurate synchronizing clock signals by clock module and trigger pip controls acquisition module collection, and data write memory module by PCIE interface under mainboard controller.Under this framework, devise the fpga logic structure on acquisition module, achieve the multiple acquisition modes such as the multiple trigger source such as keyboard, outer signal, GPS moment, conditional triggering triggers lower monostable triggering, self-recoverage triggering, monostablely to trigger again, self-recoverage triggers again.
Clock module of the present invention exports accurate synchronizing clock signals and trigger pip controls acquisition module, makes each acquisition channel synchronous acquisition, each road image data stores synchronized.Clock module is integrated with GPS, can export trigger pip in the setting GPS moment, also can control to export trigger pip by keyboard or external input signal.Acquisition module is by ADC chip, clock chip, SDRAM, fpga chip etc., by simulating signal analog to digital conversion, packing, buffer memory, transmission, conditional can export decision signal simultaneously, shot clock module, realize the highly effective gathering to signal specific such as recurrent pulses, in FPGA, each function of design is controlled by bus.Memory module adopts raid array, by controlling polylith solid state hard disc, realizes the high speed storing of data.Mainboard controller is integrated with INFINIBAND (IB) high-speed data interconnecting interface, data sharing when expanding for entire system between system and control.During system works, external analog signal coupling input acquisition module, under the accurate synchronizing clock signals of clock module controls, acquisition module gathers data, and data are carried out to the sum operation with coefficient of certain length, by statistic with can produce decision signal shot clock plate after threshold value and export synchronous triggering signal.When trigger condition meets, clock module export synchronous triggering signal triggering collection module data are packed, buffer memory with upload, mainboard controller acquisition module is uploaded data write memory module, memory module to write data carry out permanent storage.
The present invention is mainly used in different field multi-channel high-speed data acquisition and recording and storage.Cascade and expansion can be carried out according to actual needs, different weights coefficient, statistical length and discrimination threshold are set, select the multiple trigger source such as keyboard, outer signal, GPS moment, conditional triggering and monostable triggering, self-recoverage to trigger, monostablely to trigger again, the different acquisition mode such as self-recoverage triggers again.Select suitable chip, the synchronous acquisition record of hyperchannel, 100,000,000 grades of sampling rates can be realized.
Compared with prior art, advantages such as there is channel expansion, gather synchronous, conditional triggerings, various ways collection, secondary development facilitates, Human-computer Interactive Design is simple.The invention has the beneficial effects as follows:
1. the lifting of extended capability, system can be expanded with module each in mainboard, also can with integral extension between mainboard;
2. the adding of data preprocessing module, not only with good conditionsily can give up invalid signals, and the collection of higher frequency can be carried out signal specific;
3. the separation of each processing module makes the secondary development of each module convenient.
Accompanying drawing explanation
Fig. 1 is overall system architecture figure of the present invention;
Fig. 2 is acquisition channel expansion structure figure in system board of the present invention.
Fig. 3 is acquisition channel expansion structure figure between present system mainboard
Fig. 4 is its acquisition module hardware structure diagram of the present invention
Fig. 5 is its fpga logic structural drawing of the present invention
Fig. 6 is data preprocessing module building-block of logic of the present invention
Fig. 7 is acquisition mode key diagram of the present invention
Embodiment
The present invention mainly comprises clock module, acquisition module, memory module and mainboard controller, and overall composition structure as shown in Figure 1.
As shown in Figure 1, clock module, acquisition module, memory module by PCIE interface and mainboard controller interconnected, clock module can export accurate synchronizing clock signals and synchronous triggering signal, acquisition module is driven to carry out high speed synchronous sample to input simulating signal, the data collected are high speed writein memory module permanent storage under mainboard controller, wherein clock signal frequency, trigger pip source can be arranged, and the decision signal incoming clock module realization condition formula that acquisition module exports triggers.
When system carries out acquisition channel expansion in mainboard, its structure as shown in Figure 2.
As shown in Figure 2, in mainboard during acquisition channel expansion, acquisition module, memory module can expand according to the PCIE pocket numbers in mainboard controller, increase acquisition channel quantity.Mainboard controller is set up triggering selection controller, and decision signal input clock module after triggering selection controller is selected of multiple acquisition module, realization condition formula triggers.
When system carries out acquisition channel expansion between mainboard, its structure as shown in Figure 3.
As shown in Figure 3, between mainboard acquisition channel expansion time, set up top layer mainboard controller, it be by serial ports and triggering selection controller is interconnected, by PCIE interface and top layer clock module interconnected; Mainboard controller copies expansion together with clock module, acquisition module, memory module entirety, and each mainboard controller realizes cross interconnected by IB interface under IB switch; Top controller controls triggering selection controller and top layer clock module, trigger selector can be selected decision signal to trigger top layer clock module and export trigger pip, trigger each mainboard controller clock module and export next stage trigger pip, trigger each acquisition channel and carry out data storage.
Its acquisition module of the present invention describes
Acquisition module uses fpga chip as control and arithmetic element, and peripheral hardware comprises high-speed AD chip, precision clock chip, Large Copacity SDRAM, Flash chip etc.One piece of fpga chip can peripheral hardware multi-channel A/D, polylith SDRAM, collection plate is integrated with the interfaces such as external clock input, external trigger input, decision signal output, PCIE simultaneously.Its structure as shown in Figure 4.
As shown in Figure 4, the synchronizing clock signals of outside input distributes to each road A/D chip by precision clock chip, control data collection, ensures the collection clock synchronous between each road of same module and between disparate modules; Trigger pip input fpga chip, control data transmission unloading, ensures the data sync storage between each road of same module and between disparate modules; Large Copacity SDRAM group carries out buffer memory to data, is data cachedly exported by PCIE interface, and the control command of host computer is also sent to fpga chip by PCIE interface; Flash storage hardware program, initiation parameter, calibration data etc.
The fpga logic modular design of fpga chip
Figure 5 shows that fpga logic structural drawing.In figure, fpga logic structure mainly comprises two large divisions's content, data uplink module and on-chip bus module, also has the A/D chip of peripheral hardware and PCIE data interconnection module etc. in addition.
Shown in Fig. 5, data uplink module solves the problem such as synchronous data sampling, data synchronization transmissions, along separate routes packing, data buffer storage, is data uplink logical organization in " data uplink module " dotted line frame in figure.After data enter fpga chip, data preprocessing module carries out pre-service to the signal that each road gathers, comprise gain calibration, direct current calibration, the calculation of forward sight buffer memory, statistical decision gauge, Digital Down Convert (DDC), data packing etc., in the effective situation of trigger pip, data are packed, then SDRAM buffer memory is entered by route test, data from SDRAM out after, carry out frame packing with data such as heat alarm, overflow alarm signals, uploaded by PCIE interface.Be descending steering logic structure in " descending control module " dotted line frame in figure, adopt bus protocol on standard film, reasonable distribution control register group address, the steering order that significant response mainboard controller sends.
Data prediction logic module
Figure 6 shows that the data control logic structure of data preprocessing module.Mainly comprise the modules such as AD data receiver, forward sight FIFO buffer memory, data calibration, DDC, data bit adjustment.
As shown in Figure 6, after image data enters fpga chip, a point two-way processes respectively: the calculation of statistical decision gauge is carried out on a road, obtains decision signal and exports; Another road enters forward sight FIFO, from forward sight FIFO out after through calibration, DDC, data bit adjustment after pack.Data packing will be carried out under same trigger pip.
When the signals such as paired pulses gather, if continuous acquisition storage can store much invalid data, will greatly increase the difficulty of follow-up data Treatment Analysis, for this problem, devise conditional Trigger Function.On the one hand, shown in Fig. 6, the data collected divide two-way, logic module that one tunnel enters " calculation of statistical decision gauge ", carry out the weighted sum that can arrange length, adjustable weights to image data, the decision threshold then arranged with large I compares, export decision signal, as shown in Figure 1, Figure 2, Figure 3 shows, the decision signal of output enters clock module by triggering selection controller, and then the collection of control data; On the other hand, because conditional triggers the time delay in loop, if stored after statistical decision triggers, useful signal before will losing, so another road of the data collected enters forward sight FIFO cache module, forward sight FIFO forward sight size, data calibration etc. all can be arranged.
Data acquisition stores burst types and describes
System can trigger by the multiple trigger source such as keyboard, outer signal, GPS moment, conditional triggering, multiple acquisition mode acquisition and recordings such as monostablely can triggering, self-recoverage triggers, monostablely to trigger again, self-recoverage triggers again.Four kinds of acquisition modes as shown in Figure 7.
Figure 7 shows that four kinds of acquisition mode key diagrams:
During monostable triggering, start to gather at trigger pip rising edge, gather after gathering " unitary sampling is counted " of setting and automatically stop;
Monostable when triggering again, start to gather at trigger pip rising edge, after gathering set point number, wait for setting " triggering minimum interval again ", then enter wait trigger state, repeat above-mentioned steps at next trigger pip rising edge temporarily, until force to stop;
When self-recoverage triggers, start periodically to gather at trigger pip rising edge, gather one section, stop one section, " unitary sampling is counted ", " self-recoverage cycle times " and " self-recoverage cycle " can be arranged, and gather and automatically stop after gathering " the self-recoverage cycle times " of setting.
When self-recoverage triggers again, start periodically to gather at trigger pip rising edge, gather one section, stop one section, " unitary sampling is counted ", " self-recoverage cycle times " and " self-recoverage cycle " can be arranged, after gathering " the self-recoverage cycle times " of setting, wait for that next trigger pip rising edge repeats above-mentioned steps temporarily, until force to stop.
In sum; although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; any those of ordinary skill in the art; without departing from the spirit and scope of the present invention; when doing various change and retouching, the scope that therefore protection scope of the present invention ought define depending on claims is as the criterion.
Claims (4)
1. the extendible conditional of passage triggers high speed synchronous sample register system, comprise clock module, acquisition module, memory module and mainboard controller, clock module, acquisition module, memory module by PCIE interface and mainboard controller interconnected, clock module can export accurate synchronizing clock signals and synchronous triggering signal, acquisition module is driven to carry out high speed synchronous sample to input simulating signal, the data collected are high speed writein memory module permanent storage under mainboard controller, wherein clock signal frequency, trigger pip source can be arranged, the decision signal incoming clock module realization condition formula that acquisition module exports triggers,
When system carries out acquisition channel expansion in mainboard, acquisition module, memory module expand according to the PCIE pocket numbers in mainboard controller, increase acquisition channel quantity; Simultaneously in mainboard controller, set up triggering selection controller, mainboard controller is interconnected by serial ports and triggering selection controller, decision signal input clock module after triggering selection controller is selected of multiple acquisition module, the triggering of realization condition formula;
When system to carry out between mainboard acquisition channel expansion, system sets up top layer mainboard controller and top layer clock module, and top layer mainboard controller is interconnected by serial ports and triggering selection controller, top layer mainboard controller pass through PCIE interface and top layer clock module interconnected; Mainboard controller together with clock module, acquisition module, memory module entirety copy expand to multiple; Each mainboard controller realizes cross interconnected by IB interface under IB switch; Top controller controls triggering selection controller and top layer clock module, triggering selection controller can be selected decision signal to trigger top layer clock module and export trigger pip, trigger each mainboard controller clock module and export next stage trigger pip, trigger each acquisition channel and carry out data storage;
Acquisition module uses fpga chip as control and arithmetic element, its peripheral hardware of acquisition module comprises high-speed AD chip, precision clock chip, Large Copacity SDRAM and Flash chip, one piece of fpga chip can peripheral hardware multi-channel A/D, polylith SDRAM, collection plate is integrated with external clock input, external trigger input, decision signal output and PCIE interface simultaneously, it is characterized in that
Fpga chip comprises data uplink module and descending control module, also comprise A/D chip and the PCIE data interconnection module of its peripheral hardware, data uplink module in charge synchronous data sampling, data synchronization transmissions, packing and data buffer storage along separate routes, after data enter fpga chip, data preprocessing module in data uplink module carries out pre-service to the signal that each road gathers, pre-service comprises gain calibration, direct current is calibrated, forward sight buffer memory, statistical decision gauge is calculated, Digital Down Convert and data packing, in the effective situation of trigger pip, data are packed, then SDRAM buffer memory is entered by route test, data from SDRAM out after, with heat alarm, these data of overflow alarm signal carry out frame packing together, uploaded by PCIE interface, descending control module comprises on-chip bus and Parasites Fauna, and descending control module adopts bus protocol on standard film, reasonable distribution control register group address, the steering order that significant response mainboard controller sends.
2. the extendible conditional of passage according to claim 1 triggers high speed synchronous sample register system, it is characterized in that, the data control logic structure of data preprocessing module comprises AD data receiver, forward sight FIFO buffer memory, data calibration, DDC and data bit adjusting module, after image data enters fpga chip, two-way is divided to process respectively: the calculation of statistical decision gauge is carried out on a road, enter statistical decision gauge and calculate logic module, carry out arranging length to image data, the weighted sum of adjustable weights, then the decision threshold arranged with large I compares, export decision signal and obtain decision signal output, the decision signal exported enters clock module by triggering selection controller, and then the collection of control data, another road of the data collected enters forward sight FIFO, from forward sight FIFO out after through calibration, DDC, data bit adjustment after carry out data packing, data packing to carry out under same trigger pip.
3. the extendible conditional of passage according to claim 2 triggers high speed synchronous sample register system, it is characterized in that, the trigger collection source in FPGA adopts keyboard, outer signal, GPS moment or/and conditional triggers.
4. the extendible conditional of passage according to claim 3 triggers high speed synchronous sample register system, it is characterized in that, the acquisition mode in fpga chip adopts monostable triggering, self-recoverage triggers, monostable triggering or self-recoverage again trigger again.
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| CN111679993B (en) * | 2020-05-29 | 2021-08-17 | 湖南苍树航天科技有限公司 | Multichannel parallel synchronous bus controller |
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