CN105676198A - Echo pulse delay generating device for pulse type radar test - Google Patents
Echo pulse delay generating device for pulse type radar test Download PDFInfo
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- CN105676198A CN105676198A CN201610196573.5A CN201610196573A CN105676198A CN 105676198 A CN105676198 A CN 105676198A CN 201610196573 A CN201610196573 A CN 201610196573A CN 105676198 A CN105676198 A CN 105676198A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
- G01S7/406—Means for monitoring or calibrating by simulation of echoes using internally generated reference signals, e.g. via delay line, via RF or IF signal injection or via integrated reference reflector or transponder
- G01S7/4065—Means for monitoring or calibrating by simulation of echoes using internally generated reference signals, e.g. via delay line, via RF or IF signal injection or via integrated reference reflector or transponder involving a delay line
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- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses an echo pulse delay generating device for a pulse type radar test. A multi-channel phase-shifting clock is creatively utilized to perform high-speed equivalent interpolation sampling on pulse signals; a multi-channel FIFO storage unit is utilized to uninterruptedly store the pulse signals; an interpolation counting method is utilized to realize high-precision delay control output of the inputted pulse signals under a low clock frequency, and therefore, the requirement of back-end test equipment for the delay precision of echo pulse signals can be satisfied; and if a basic clock signal frequency is fIN, a phase-locked loop is utilized to perform M frequency multiplication and N-channel phase shifting, and therefore, equivalent sampling speed can be increased to MNfIN, and the time resolution of the sampled and stored pulse data can be increased by MN times, and thus, the control precision of delay output can be increased to 1/MNfIN. Compared with a traditional pulse signal delay method, the device of the invention can carry out high-precision control output of pulse signal fixed delay and variable delay, so that flexible simulation of height or distance echo signals can be realized.
Description
Technical field
The invention belongs to signal processing technology field, more specifically say, relate to a kind of for pulse radarEcho impulse in height or range simulation test process postpones generation device.
Background technology
Radar is that one utilizes electromagnetic wave to carry out distance (highly) and target signature is surveyed and the equipment of measurement.The modulation signal of radar emission produces echo after target reflecting surface, by receive echo-signal timeFrequently feature is carried out analyzing and processing, thus obtain target reflecting surface with respect to the orientation of transmitter, distance andThe information such as associated change speed.
Radar is divided by its function, can be used for surveying the occasions such as high, early warning, search, warning, guidance; From workDo to divide in system, can be divided into primary radar and secondary radar; Emission signal frequency covers from metric wave alwaysMillimeter wave; Divide from the modulation type that transmits, radar can be divided into continuous wave formula and the large class of pulsed two.
For the radar of pulse (modulation) formula, its operation principle is by measuring transmitted pulse and echo impulseBetween transmission time difference, then according to electromagnetic wave spatial velocity, calculate relative distance and the order of targetThe information such as mark feature. Pulse radar, with respect to continuous wave formula radar, not only has better anti-interference,And aspect orientation and distance measurement, also there is larger advantage.
The computing formula of relative distance is:
D＝c·Δt/2(1)；
Wherein, D is the relative distance of radar and target, and c is the spread speed of electromagnetic wave in space, and Δ t sends outPenetrate signal moment t0With reception signal moment t1Time difference, i.e. Δ t=t1-t0。
Paired pulses formula radar is tested, and need to follow the tracks of the pulse signal of launching, and wants according to testAsk the echo impulse that produces fixed delay or variable delay, the echo impulse after postponing is connected to tested thunderReach receiving terminal, the setting value relatively postponing and the value of resolving of tested radar, thus judge tested radarWhether function and index be normal.
Because electromagnetic wave is at the transmission speed c=299792458m/s in space, therefore, under shorter distance, receiveThe delay of sending out pulse is very little. Traditional test mode adopts the fibre delay line of regular length, sound table to prolong mostlyThe devices such as slow line postpone to forward to the pulse signal (decay and detection, comparison and shaping) of transmitting, onlyCan simulate fixed range and postpone, testing procedure is loaded down with trivial details, and testing efficiency is low, and can not carry out variable-distanceFrom or the delay simulation in orientation. Another kind of test mode is that employing target is hung height or real machine is hung the mode flyingCarry out, although this mode is more pressed close to pulse radar real working condition, exist test platform to build inconvenience,The weak points such as test period is long, testing cost height. Therefore, how to realize comparatively fast, echo neatlyPulse daley simulation and control in outfield various functions and index test, have very in pulse radarImportant engineering using value.
Summary of the invention
The object of the invention is to overcome in existing pulse radar test process, echo impulse postpones to produce skillThe deficiency of art, provides a kind of echo impulse for pulse radar test to postpone generation device, with furtherImprove the delay precision of echo impulse.
For achieving the above object, the present invention postpones to produce dress for the echo impulse of pulse radar testPut, build based on FPGA, comprising:
Count delay module, for receiving setting length of delay, and carries out delay counter, when count value and settingAfter length of delay equates, open the enable signal of reading that produces FIFO memory;
It is characterized in that, also comprise:
Frequency multiplication and phase shift block, its use two-stage totally three PLL (phaselocked loop) is carried out reference clock signalFrequency frequency multiplication and phase shift are processed: the first order is a PLL, for reference clock signal is carried out frequency multiplication andFan-out, the Clock Multiplier Factor of setting is M, and two-way fan-out clock signal is set, clock signal frequency is MfIN，Phase difference is 180 degree, wherein, and fINFor the frequency of reference clock signal; The second level is two PLL, firstThe two-way clock signal of the PLL fan-out (output) of level is sent into respectively two PLL of the second level, arranges twoPLL exports respectively N/2 road clock signal, each PLL output Mei road clock signal phase shift 360/N successivelyDegree, adjacent two-way clock signal phase is poor is 360/N, when such two PLL export respectively N/2 roadClock signal combination is got up, and has obtained N road and has had the poor clock signal for 360/N of same phase;
FIFO (FirstInputFirstOutput, the FIFO) memory cell of N 1Bit bit wide, eachThe read-write clock of individual FIFO memory cell connects with the N road clock signal that frequency multiplication and phase shift block produce respectivelyConnect, the depth capacity S of FIFO memory is:
S＝2D/cTFIFO＝Δt/TFIFO；(2)
Wherein, D is relative distance, and unit is rice, TFIFOThe FIFO memory cell read-write clock cycle to be1/MfIN，cTFIFORepresent that electromagnetic wave is at TFIFOThe distance of transmission in time, Δ t is the delay that relative distance D is correspondingTime;
Data collection module, has N input, and connects with the output of N FIFO memory cell respectivelyConnect, for the data of N FIFO memory output being collected, obtain echo impulse and postpone output;
The relative distance D simulating as required by host computer, arranges corresponding time delay, and transmission is prolongedThe slow time, corresponding setting length of delay arrived count delay module; Count delay module receives and sets after length of delay,First empty N the data in cell fifo by asynchronous resetting control end, then wait for pulse signal input;Wherein, described pulse signal is: the highpowerpulse modulation signal of pulse radar transmitting terminal output is by solidDetermine the exomonental detection framework signal obtaining after attenuator, wave detector, then detection framework signal is passed throughComparator compares the signal obtaining after shaping and level conversion; Described pulse signal is connected respectively to NThe data input pin of FIFO memory cell and count delay module;
In the time that first pulse signal rising edge arrives, it is single that count delay module is opened N FIFO storage simultaneouslyWriting of unit enables to control, and the pulse signal of input is written at the rising edge of N road clock signal accordinglyIn FIFO memory cell;
When enable operation is write in unlatching, the counter in count delay module is started working; When counting down toSet time delay be that count value equals to set after length of delay, open N FIFO memory cell read enableWith data collection module output enable, now, the read-write of N FIFO memory cell enables, data are collected defeatedGo out to enable all to open; In this state, the pulse signal of input is being written to respectively N continuallyWhen individual FIFO memory cell, also according to the principle of FIFO continuously from N FIFO memory cellRead out, then output to data collection module and carry out OR operation, obtain echo impulse and postpone output,Radio-frequency signal source is passed through in this delay output again, produces final echo-signal and be sent to the receiving terminal of radar equipment,Thereby complete the delay simulation of height or distance.
The object of the present invention is achieved like this.
The present invention postpones generation device for the echo impulse of pulse radar test, is to have utilized FPGA deviceThe high integration of part, the feature such as high operate frequency and parallel processing capability are strong, creationary by multichannel phase shiftClock pulse signals is carried out the equivalent interpolation sampling of high speed, is undertaken by multichannel FIFO memory cell pulse signalsFree of discontinuities storage; The mode that count delay module is read storage Data Control, has solved pulse radar meritIn energy and index test process, to this demand of fixed and variable delay echo pulse signal simulation.
Meanwhile, adopt multichannel phase shifting clock and multichannel FIFO memory, utilize the method for interpolation counting lowerUnder clock frequency, realize the high accuracy of input pulse signal is postponed to control output, met back end test and establishedThe standby needs that echo pulse signal postponed to precision. If basic clock signal frequency is fIN, use phaselocked loop to enterRow M frequency multiplication and the phase shift of N road, equivalent sampling speed is brought up to MNfIN, samples storage pulse data timeBetween resolution ratio improve MN doubly. Utilize count delay module, need to postpone to read to be stored in FIFO according to testIn pulse data. Because counting and FIFO read-write clock frequency are equivalent to MNf tooIN, therefore postponeThe control accuracy of output is brought up to 1/MNfIN. Be compared to traditional pulse delay signal method, energy of the present inventionEnough carry out the high accuracy control output of pulse signal fixed delay and variable delay, thereby realize height or distanceThe flexible simulation of echo-signal. The present invention has that precision is high, volume is little, cost is low, control is flexible, convenientJointly build the feature of test platform and Auto-Test System with other measuring instrument.
The invention solves in existing pulse radar test process, echo impulse postpones the deficiency of generation technology,Utilize field programmable gate array (FPGA) logical device inner abundant interconnection resource, phaselocked loop (PLL)And memory cell, the radar pulse signal of input is gathered storage, postpones to forward, to realize interiorUnder field testing condition, paired pulses formula radar altitude or the simulation apart from echo-signal, carry out correlation function andThe thermometrically of index, meets equipment development, produces the needs that test and regular maintenance ensure.
Brief description of the drawings
Fig. 1 is that the concrete application that the present invention postpones generation device for the echo impulse of pulse radar test is shownIntention;
Fig. 2 is that the present invention postpones a kind of concrete enforcement of generation device for the echo impulse of pulse radar testMode theory diagram;
Fig. 3 be input pulse signal of the present invention, echo impulse inhibit signal and multichannel phase shift clock signal timeOrder relation schematic diagram.
Detailed description of the invention
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the artUnderstand better the present invention. Requiring particular attention is that, in the following description, when known function andPerhaps, when the detailed description of design can be desalinated main contents of the present invention, these are described in here and will be left in the basket.
Fig. 1 is that the concrete application that the present invention postpones generation device for the echo impulse of pulse radar test is shownIntention.
In the present embodiment, as shown in Figure 1, the highpowerpulse modulation letter of pulse radar transmitting terminal outputThe exomonental detection framework signal of number decaying, obtaining after wave detector detection by fixed attenuator, then willDetection framework signal compares the pulse signal P obtaining after shaping and level conversion by comparatorIN, pulseSignal PINBe input to echo impulse delay generation device and obtain echo impulse delay output, warp is again exported in this delayCross radio-frequency signal source, produce final echo-signal and be sent to the receiving terminal of radar equipment, thus complete height orThe delay simulation of distance.
Fig. 2 is that the present invention postpones a kind of concrete enforcement of generation device for the echo impulse of pulse radar testMode theory diagram.
In the present embodiment, as shown in Figure 2, the high accuracy external timing signal that is input to FPGA is benchmarkClock fINFirst the first order PLL that enters into frequency multiplication and the phase shift block 1 of FPGA, the first order is onePLL, sets this PLL and works in frequency multiplication pattern, and it is M times that Clock Multiplier Factor is set, the phase shift of fan-out half periodTwo-way homogenous frequency signal. Like this, be Mf by the clock signal frequency after this PLL process of frequency multiplicationIN, when two-wayClock phase difference is 180 degree. The two-way clock signal that first order PLL is exported is sent into respectively two of the second levelPLL, arranges two PLL and exports respectively N/2 road clock signal, i.e. the 1st PLL output the 0th, 1,N/2 road clock, the 2nd PLL exports N/2+1, N/2+2 ... N road clock. Adjacent two-way clockSignal phase difference is 360/N degree, has obtained like this N road clock signal, and the time delay of adjacent clock signal istd＝1/MNfIN, the sequential relationship of N road clock signal as shown in Figure 3.
In FPGA, design the FIFO memory cell 2 of N 1Bit bit wide, will after frequency multiplication and phase shift, obtainN road clock signal respectively as the read-write clock f of N FIFO memory cell 2M1～fMN. For fear ofFIFO memory cell writes to overflow and causes the pulse signal of storage to be lost, in specific implementation process, FIFO'sStorage depth S is conventionally according to the maximum of the transmitting-receiving maximum of time difference Δ t or the relative distance D of radar and targetValue, according to formula S=2D/cTFIFO＝Δt/TFIFOAfter calculating, set.
The pulse signal P obtaining after overdamping and detection and comparison shaping and level conversionINSend intoFPGA is connected to data input pin and the count delay module of N FIFO memory cell 2 simultaneously. CountingPostponement module 4 control N FIFO memory cell 2 read enable, write enable and asynchronous resetting (in order to makeDrawing is succinct, does not draw).
While starting to test, the relative distance D simulating as required by host computer, while arranging corresponding delayBetween, and send setting length of delay corresponding to time delay to count delay module 4; Count delay module 4 is receivedSet after length of delay, first by asynchronous resetting (not shown), the memory cell of N FIFO 2 is all clearEmpty. After first pulse signal rising edge arrives, count delay module 4 is opened N FIFO storage simultaneouslyWriting of unit 2 enables to control, and the pulse signal of input is written to corresponding at the rising edge of N road clock signalFIFO memory cell in. As shown in Figure 3, the read-write clock frequency of each road FIFO memory cellfMi＝MfIN, (i=0,1,2 ... N), because the rising edge of the even phase shifting clock in N road is at a MfINCycleInside be spacedly distributed, therefore, multipath clock signal time sharing sampling in this FPGA sheet, multiple memory cell is depositedThe process of storage is equivalent to fs＝MNfINFrequency carry out samples storage, in FPGA device by " with spaceChange the time " method realized the flexible simulation that echo impulse under high accuracy condition postpones. In addition, due to arteries and veinsRush signal edge and within a sampling period, obey and be uniformly distributed the time of advent, therefore, pulse signal rising edgeThe time error E of samplingrTime error E with trailing edge samplingfAlso be reduced to 1/MN.
When N FIFO memory cell 2 of input pulse signal rising edge triggering write enable operation, countingCounter in Postponement module is started working, when count down to the time delay of setting be count value equal set prolongLate after value, open N FIFO memory cell 2 read enable and data collection module output enable. Now,Leave in N the pulse signal in FIFO memory cell 2 under the effect of read-write clock by FIFOCall over, output to data collection module 3 and carry out logical "or" operation, data collection module 3 is realizedMultipath input data single channel merge output. Having counted rear N FIFO memory cell 2 reads while write alsoThe process of output, is continued until that host computer sends new setting length of delay again.
To sum up, the present invention passes through the storage of input pulse signal time sharing sampling, and count delay reads, and collects and closesAnd export this series of steps, realize required echo arteries and veins in pulse radar height or range simulation testThe generation that punching postpones.
In the present embodiment, the high precision reference clock frequency f of selectionIN=10MHz, according to selecting FPGA deviceThe programmable resource feature of part, sets first order PLL Clock Multiplier Factor M=25, sets two second level PLLPhase shift way N=8. Like this, 8 tunnel frequencies have just been obtained identical, the parallel clock signal that phase difference 45 is spent.In FPGA device, clock signal cabling is low delay copper wire, is not considering that PLL device self postponesIn the situation of signal transmission delay, the clock signal f of equivalences＝MNfIN=2000MHz. Therefore, wholeIn pulse daley processing procedure, be 1/f from signal input part to the temporal resolution of collecting outputs＝0.5ns，It is c/f that the theory of respective heights or distance postpones precisions=0.15m. In actual engineering application, consider letterOther interference and the error introduced in number transmission and processing procedure, postpone precision and can be less than 0.3m. Set 8Individual FIFO memory cell, storage depth S=65536, can store at most the pulse data of 32768ns. ProtectingStay in the situation of a part of design capacity, by formula S=2D/cTFIFO＝Δt/TFIFOCan draw the maximum that postpones simulationHeight or distance B >=9000m, the present invention can meet the requirement of pulse radar certainty of measurement and measurement category.
The present invention takes full advantage of the abundant all kinds of resources of contemporary advanced programmable gate array device inside and entersRow design, has realized the signal delay processing in pulse radar and similar principles electronic equipment test process.In test process, operating personnel can utilize FPGA device and this method and Other Instruments equipment jointly to buildTest platform, can arrange delay parameter by host computer. The present invention has that volume is little, cost is low,The advantage such as simple to operate, easy to use, can reduce testing cost, improves testing efficiency.
Although above the illustrative detailed description of the invention of the present invention is described, so that the artTechnical staff understand the present invention, but should be clear, the invention is not restricted to the scope of detailed description of the invention, rightThose skilled in the art, as long as various variations limit and determine in appended claimThe spirit and scope of the present invention in, these variations are apparent, all utilize sending out that the present invention conceivesBright creation is all at the row of protection.
Claims (2)
1. postpone a generation device for the echo impulse of pulse radar test, build based on FPGA,Comprise:
Count delay module, for receiving setting length of delay, and carries out delay counter, when count value and settingAfter length of delay equates, open the enable signal of reading that produces FIFO memory;
It is characterized in that, also comprise:
Frequency multiplication and phase shift block, its use two-stage totally three PLL (phaselocked loop) is carried out reference clock signalFrequency frequency multiplication and phase shift are processed: the first order is a PLL, for reference clock signal is carried out frequency multiplication andFan-out, the Clock Multiplier Factor of setting is M, and two-way fan-out clock signal is set, clock signal frequency is MfIN，Phase difference is 180 degree, wherein, and fINFor the frequency of reference clock signal; The second level is two PLL, firstThe two-way clock signal of the PLL fan-out (output) of level is sent into respectively two PLL of the second level, arranges twoPLL exports respectively N/2 road clock signal, each PLL output Mei road clock signal phase shift 360/N successivelyDegree, adjacent two-way clock signal phase is poor is 360/N, when such two PLL export respectively N/2 roadClock signal combination is got up, and has obtained N road and has had the poor clock signal for 360/N of same phase;
FIFO (FirstInputFirstOutput, the FIFO) memory cell of N 1Bit bit wide, eachThe read-write clock of individual FIFO memory cell connects with the N road clock signal that frequency multiplication and phase shift block produce respectivelyConnect, the depth capacity S of FIFO memory is:
S＝2D/cTFIFO＝Δt/TFIFO；
Wherein, D is relative distance, and unit is rice, TFIFOThe FIFO memory cell read-write clock cycle to be1/MfIN，cTFIFORepresent that electromagnetic wave is at TFIFOThe distance of transmission in time, Δ t is the delay that relative distance D is correspondingTime;
Data collection module, has N input, and connects with the output of N FIFO memory cell respectivelyConnect, for the data of N FIFO memory output are collected, obtain echo impulse and postpone output;
The relative distance D simulating as required by host computer, arranges corresponding time delay, and transmission is prolongedThe slow time, corresponding setting length of delay arrived count delay module; Count delay module receives and sets after length of delay,First empty N the data in cell fifo by asynchronous resetting control end, then wait for pulse signal input;Wherein, described pulse signal is: the highpowerpulse modulation signal of pulse radar transmitting terminal output is by solidDetermine the exomonental detection framework signal obtaining after attenuator, wave detector, then detection framework signal is passed throughComparator compares the signal obtaining after shaping and level conversion; Described pulse signal is connected respectively to NThe data input pin of FIFO memory cell and count delay module;
In the time that first pulse signal rising edge arrives, it is single that count delay module is opened N FIFO storage simultaneouslyWriting of unit enables to control, and the pulse signal of input is written at the rising edge of N road clock signal accordinglyIn FIFO memory cell;
When enable operation is write in unlatching, the counter in count delay module is started working; When counting down toSet time delay be that count value equals to set after length of delay, open N FIFO memory cell read enableWith data collection module output enable, now, the read-write of N FIFO memory cell enables, data are collected defeatedGo out to enable all to open; In this state, the pulse signal of input is being written to respectively N continuallyWhen individual FIFO memory cell, also according to the principle of FIFO continuously from N FIFO memory cellRead out, then output to data collection module and carry out OR operation, obtain echo impulse and postpone output,Radio-frequency signal source is passed through in this delay output again, produces final echo-signal and be sent to the receiving terminal of radar equipment,Thereby complete the delay simulation of height or distance.
2. echo impulse according to claim 1 postpones generation device, it is characterized in that, described high-precisionDegree reference clock frequency fIN=10MHz, according to the programmable resource feature of selecting FPGA device, sets firstLevel PLL Clock Multiplier Factor M=25, the phase shift way N=8 of two second level PLL of setting, obtains 8 tunnel frequenciesThe clock signal identical, phase difference 45 is spent.
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