CN104965197A - FPGA-based radar echo signal simulator - Google Patents
FPGA-based radar echo signal simulator Download PDFInfo
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- CN104965197A CN104965197A CN201510373685.9A CN201510373685A CN104965197A CN 104965197 A CN104965197 A CN 104965197A CN 201510373685 A CN201510373685 A CN 201510373685A CN 104965197 A CN104965197 A CN 104965197A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
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Abstract
The invention discloses an FPGA-based radar echo signal simulator. The simulator processes a received radar echo signal. A signal output by a radar transmitter comprises various information of a target, so as to simulate a radar signal. The simulator comprises a signal receiving module, a rated frequency calibration module, an A/D (D/A) conversion module, an FPGA-based information collection module, a clock control module and a noise and clutter module. The echo signal received by the signal receiving module is converted by the calibration module and the A/D module, and is sent into the signal information collection module for signal processing. The radar echo signal is simulated. Target, clutter and noise parameters can be manually set, which is convenient for simulation and debugging.
Description
Technical field
The invention belongs to radar simulation technical field of measurement and test, specifically a kind of collection radar emission signal, and carry out target information modulation, produce radar target signal, design realizes the method for radar echo simulator.
Background technology
In the design, research and production process of radar system, be a very important link to the detection of radar performance and index.The development trend of modern radar system becomes increasingly complex, so the debugging of and each subsystem overall to radar and detection become more and more difficult, if the mode adopting outfield to take a flight test, at substantial manpower and materials, and the R&D cycle also can be very long.Simultaneously outfield uncontrollable factor of taking a flight test is many, adds the difficulty of debugging.Radar signal simulator is the product that digital simulation technique combines with Radar Technology, and it produces radar echo signal by the method for simulation, under the condition do not possessed in actual radar system front end, to debug the rear class of radar system.Therefore radar echo simulation system is widely applied in Radar Design and detection field.
Producing in radar return vision signal: comparing typical method is mention in the prosperous master's thesis " radar signal simulator based on FPGA designs " of 2008 Beijing Polytechnics seedling: the equation of motion of known target, the expression formula about speed is obtained by the differential expression of the equation of motion, obtain radial velocity with this, then obtain the Doppler shift of target echo.The method computing more complicated, calculated amount is more, is not easy carry out hardware implementing and do not have amplitude to control.
Summary of the invention
The object of the present invention is to provide a kind of radar echo signal simulator based on FPGA.
The technical solution realizing the object of the invention is: a kind of radar echo signal simulator based on FPGA, comprises signal receiving module, rated frequency calibration module, A/D conversion module, D/A conversion module, information acquisition module, clock control module and noise based on FPGA and spur block, signal receiving module, A/D conversion module, information acquisition module, D/A conversion module are connected successively, rated frequency calibration module is connected with A/D conversion module, clock control module is connected with information acquisition module, rated frequency calibration module simultaneously, and noise and spur block are connected with information acquisition module, the echoed signal of signal receiving module receiving target radar, A/D conversion module carries out A/D conversion and sampling to this signal, extract effectively stable echoed signal, meanwhile produce a baseband frequency signal in outfield, through the calibration of rated frequency calibration module, obtain the signal that frequency is identical, with the echoed signal mixing extracted, signal entering signal information acquisition module after mixing, wherein by the distance obtaining echo target based on the range gate algorithm of FPGA and delay algorithm, velocity information, mixed frequency signal is superimposed with the noise and clutter waveform that are produced by noise and spur block again, produce complete analog echo signal, eventually pass D/A conversion module, export radar echo simulation signal.
Described rated frequency calibration module is connected successively by matched filter, ctrol control module module, VCO voltage-controlled oscillator, PLL phaselocked loop, AMP amplifier, BPF wave filter, antenna transmission module, and PLL phaselocked loop is connected to form as feedback and A/D conversion module; The echoed signal that signal receiving module receives is first through frequency mixer and the signal mixing fed back from PLL phaselocked loop, export the vision signal after mixing, this signal outputs to matched filter again after AD conversion module, matched filter Output rusults input ctrol control module, ctrol control module constantly adjusts voltage, export local signal after being input to VCO voltage-controlled oscillator and PLL phaselocked loop, and feed back to frequency mixer; When the peak value p that matched filter exports reaches maximum, obtain the local signal that the carrier frequency of the echoed signal received with signal receiving module is identical, finally this signal amplified and launched by antenna transmission module after filtering.
The implementation method of described rated frequency calibration module is as follows:
Step one: the signal mixing that the echoed signal that signal receiving module receives feeds back through frequency mixer and PLL phaselocked loop, produces vision signal;
Step 2: vision signal outputs to matched filter and carries out peakvalue's checking after AD converter, now ctrol control module initialization voltage v is, the voltage v of ctrol control module is made to be increased to v+ △ v, wherein △ v is the smaller the better, can be .v, if the peak value p that matched filter exports increases, then continue to make the voltage v of ctrol control module to increase △ v, otherwise, if the peak value p that matched filter exports reduces, the voltage v of ctrol control module is then made to reduce △ v, repeat aforesaid operations until the peak value p of matched filter reaches maximum, voltage is now outputted to VCO voltage-controlled oscillator and PLL phaselocked loop and exports local signal by ctrol control module,
Step 3: local signal exports from PLL phaselocked loop, utilizes amplifier and BPF wave filter to amplify and filtering this signal, is finally launched by antenna transmission module.
Matched filter described in described step 2 is formed by subpulse matched filter and the cascade of tap weight delay line summation network two parts, the size control VCO voltage-controlled oscillator module of the peak value p that ctrol control module exports according to matched filter and PLL phaselocked loop are to carry out frequency calibration, when local signal frequency does not have identical with the carrier frequency of the echoed signal received, the peak value p that matched filter exports is less than the peak value p exported when Complete Synchronization, now, ctrol control module initialization voltage v is, the voltage v of ctrol control module is made to be increased to v+ △ v, wherein △ v is the smaller the better, can be .v, if the peak value p that matched filter exports increases, then continue to make the voltage v of ctrol control module to increase △ v, otherwise, if the peak value p that matched filter exports reduces, the voltage v of ctrol control module is then made to reduce △ v, repeat aforesaid operations until the peak value p of matched filter reaches maximum, ctrol control module using voltage now as output, the voltage that VCO voltage-controlled oscillator and PLL phaselocked loop export according to ctrol control module exports local signal, now local signal frequency is identical with the carrier frequency of the echoed signal received, local signal exports from PLL phaselocked loop.
The implementation method of the described information acquisition module based on FPGA is as follows:
Step one: first carry out initialization, obtains range gate Δ R, by formula τ by formula Δ R=2C × Δ τ
0=R
0/ 2C obtains the initial delay time τ of target to radar
0; Wherein Δ τ is minimum interval, and C is the light velocity, R
0for known target is to the initial distance of radar; v
0for the initial radial velocity of target, α is the acceleration of target, wherein α can be, on the occasion of or for negative value;
Step 2: make time-parameters t=0 in range gate;
Step 3: by v
0, α, t substitute into
Step 4: judge
whether be more than or equal to Δ R, if
show that now target exceedes range gate Δ R, this seasonal v to the changing value of distance by radar
0=v
0+ α t, returns step 2, simultaneously by formula
obtain Doppler shift fd, wherein λ is wavelength, and frequency of utilization is that the sinusoidal signal of fd carries out phase alignment to radar emission signal, continues to perform step 5; Otherwise, make t=t+1, return step 3;
Step 5: the v tried to achieve in determining step four
0whether be greater than, if v
0> 0, shows that target is towards radar, then delay time T
0=τ
0-Δ τ, if v
0< 0, represents target and goes away from radar, then delay time T
0=τ
0+ Δ τ;
Step 6: use delay time T
0distance delay calibration is carried out to radar signal, thus obtains the signal after phase alignment and distance delay calibration;
Step 7: use the delay time T that step 5 is tried to achieve
0by formula
obtain the distance R of target to radar, use amplitude A mp ∝ 1/R
4relation amplitude control is carried out to the signal that step 6 obtains, obtain simulate radar return vision signal.
Described clock control module is implemented as follows:
Step one: produce a stable clock frequency with pulse signal generator, this frequency-adjustable saves;
Step 2: simultaneously supply frequency calibration module and signal message acquisition module by this clock frequency, makes them have identical echo time delay.
Noise needed for described noise and spur block produce and noise signal, first to it through digitized process, then adopt analyzable mathematical model to compare, in the ideal situation by them through row Fourier transform, finally superpose through row with mixed frequency signal, produce complete analogue echoes signal.
The present invention compared with prior art, its remarkable advantage: simulator of the present invention is structurally to apply a kind of new frequency calibration device with the difference of other simulators, simple and effectively can realize the frequency calibration of baseband signal, thus make the process of mixing more reliable, algorithmically have employed a kind of new range gate algorithm, be different from known formula in the past, differentiate calculates Distance geometry speed and acceleration, the algorithm that this simulator adopts is realized by FPGA, be small unit with range gate, conveniently realize on various engineering application.This method is devoted to simulate at the uniform velocity, even acceleration, radar return vision signal in even deceleration and the situation such as static.The present invention first establishes range gate Δ R by formula Δ R=2C × Δ τ, and t is increased to by t=t+1 and meets from 0
after condition, now target exceedes range gate Δ R, according to v to the changing value of distance by radar
0be greater than or less than 0 delay time T
0corresponding reduction or increase Δ τ, directly can obtain delay time T like this
0.With τ
0amplitude control is carried out by RCS algoritic module after trying to achieve target to the distance R of radar.By formula v
0=v
0+ α t draws radial velocity v
0, by v
0the Doppler shift of target echo can be obtained by cordic algorithm module.As can be seen here, this method is completely different from known typical method, and the method for the situation radar return vision signals such as the present invention simulates at the uniform velocity, even acceleration, even deceleration is more simple, and calculated amount is less; In addition the vision signal after mixing and A/D conversion of the direct receiving radar transmitting of the present invention, instead of simulated by DDS generation signal.In Clock management: general radar simulator distance time delay is accurate not, and the basic delay unit of the present invention, by the look-up tables'implementation of FPGA, can realize nanosecond accurate delay, and the size of range gate is significantly shortened, and makes distance time delay more accurate.
Accompanying drawing explanation
Fig. 1 is simulation of radar return signal device block diagram.
Fig. 2 is frequency calibration module.
Fig. 3 is signal message acquisition module.
Embodiment
From objective demand, economy, convenience, the dirigibility of radar echo signal simulation, the aspect such as control is comprehensive, degree of repeatability is high, study and debugged this radar echo signal simulator, make radar signal not be used in outfield at substantial energy to realize, this is a relay type radar echo signal simulator based on FPGA.First radar echo signal is received by antenna, with the complete baseband signal of calibration through row mixing, filtering high fdrequency component, then carry out A/D sampling and produce coherent video, signal, by the Processing Algorithm based on FPGA, is the radial velocity of basic parameter evaluating objects by range gate, Doppler shift etc., also can add the parameters such as noise to process, simultaneously by total clock control module respectively through cordic algorithm and RCS algorithm, analyze its phase place and amplitude information.Final signal transforms through D/A, after frequency mixer carries out upconversion process, creates the radiofrequency signal required by simulation, and such receiver directly can carry out reception and display-object information to this signal.
Below in conjunction with accompanying drawing, the present invention is described in further detail.
First rf echo signal is received by antenna, with the complete baseband signal of calibration through row mixing, filtering high fdrequency component, then carry out A/D sampling and produce coherent video, signal, by the Processing Algorithm based on FPGA, is the radial velocity of basic parameter evaluating objects by range gate, Doppler shift etc., also add the parameter such as noise by noise module to process, simultaneously by total control module respectively through cordic algorithm and BCS algorithm, analyze its phase place and amplitude information.Final signal transforms through D/A, after frequency mixer carries out upconversion process, creates the radiofrequency signal required by simulation, and such receiver directly can carry out reception and display-object information to this signal.
On device framework as shown in Figure 1: antenna transmission module transmits, through the reference signal of double frequency calibration module in the capable mixing of frequency mixer back warp, then digital signal is become through A/D sampling module, then through signal transacting signal message acquisition module, extract the information such as the Distance geometry speed of signal, all clocks are provided by clock control module unification and control reaches accurately effectively, and eventually passing D/A module converter is analog signal output.
Step one: the signal received is by a frequency mixer mixing, given baseband signal is through frequency calibration, containing the phaselocked loop producing baseband signal in calibration module, and the VCO constantly changing frequency is voltage-controlled wholely swings device, make both arrive in by matched filter in continuous change process maximum, then effectively accomplish frequency calibration.
Step 2: the vision signal that frequency mixer exports changes through A/D, turned to Coded Signals so that follow-up analysis and debugging, pass through the range gate signal message acquisition module based on FPGA again, this signal message acquisition module effectively can be analyzed and superpose through row Doppler, produce carrying of target useful information, and the radial velocity of target can be obtained by signal message acquisition module, then can be controlled and adjusting range and phase place by RCS algorithm.
Step 3: signal is out added to noise module from signal message acquisition module, according to the requirement of simulating signal echo, selects different clutter type and noise to it through row superposition.According to radar varying environment, select dissimilar clutter, or can white Gaussian noise be given as when experimental analysis, carry out some correspondences requirement test.
Step 4: from noise and spur block signal out, through D/A conversion module, produce the original state of signal that finally will export, all information that this signal imitation radar emission echo comprises, and can apply with many-sided debugging with in emulating.
Claims (7)
1. based on a radar echo signal simulator of FPGA, it is characterized in that: comprise signal receiving module (1), rated frequency calibration module (2), A/D conversion module (3), D/A conversion module (14), information acquisition module (4), clock control module (5) and noise based on FPGA and spur block (6), signal receiving module, A/D conversion module (3), information acquisition module (4), D/A conversion module (14) are connected successively, rated frequency calibration module is connected with A/D conversion module (3), clock control module (5) is connected with information acquisition module (4), rated frequency calibration module (2) simultaneously, and noise and spur block (6) are connected with information acquisition module (4), the echoed signal of signal receiving module (1) receiving target radar, A/D conversion module (3) carries out A/D conversion and sampling to this signal, extract effectively stable echoed signal, meanwhile produce a baseband frequency signal in outfield, through the calibration of rated frequency calibration module (2), obtain the signal that frequency is identical, with the echoed signal mixing extracted, signal entering signal information acquisition module (4) after mixing, wherein by the distance obtaining echo target based on the range gate algorithm of FPGA and delay algorithm, velocity information, mixed frequency signal is superimposed with the noise and clutter waveform that are produced by noise and spur block (6) again, produce complete analog echo signal, eventually pass D/A conversion module (14), export radar echo simulation signal.
2. the radar echo signal simulator based on FPGA according to claim 1, it is characterized in that: described rated frequency calibration module (2) is connected successively by matched filter (7), ctrol control module module (8), VCO voltage-controlled oscillator (9), PLL phaselocked loop (10), AMP amplifier (11), BPF wave filter (12), antenna transmission module (13), PLL phaselocked loop (10) is connected to form as feedback and A/D conversion module (3); The echoed signal that signal receiving module (1) receives is first through frequency mixer and the signal mixing fed back from PLL phaselocked loop (10), export the vision signal after mixing, this signal outputs to matched filter (7) again after AD conversion module (3), matched filter (7) Output rusults input ctrol control module (8), ctrol control module (8) constantly adjusts voltage, be input to VCO voltage-controlled oscillator (9) and PLL phaselocked loop (10) exports local signal afterwards, and feed back to frequency mixer; When the peak value p that matched filter (7) exports reaches maximum, obtain the local signal identical with the carrier frequency of the echoed signal that signal receiving module (1) receives, finally this signal amplified and launched by antenna transmission module (13) after filtering.
3. the radar echo signal simulator based on FPGA according to claim 2, is characterized in that: the implementation method of described rated frequency calibration module (2) is as follows:
Step one: the signal mixing that the echoed signal that signal receiving module (1) receives feeds back through frequency mixer and PLL phaselocked loop (10), produces vision signal;
Step 2: vision signal outputs to matched filter (7) and carries out peakvalue's checking after AD converter (3), now ctrol control module (8) initialization voltage v0, the voltage v of ctrol control module (8) is made to be increased to v0+ △ v, if the peak value p that matched filter (7) exports increases, then continue to make the voltage v of ctrol control module (8) to increase △ v, otherwise, if the peak value p that matched filter (7) exports reduces, the voltage v of ctrol control module (8) is then made to reduce △ v, repeat aforesaid operations until the peak value p of matched filter (7) reaches maximum, voltage is now outputted to VCO voltage-controlled oscillator (9) and PLL phaselocked loop (10) and exports local signal by ctrol control module (8),
Step 3: local signal exports from PLL phaselocked loop (10), utilizes amplifier and BPF wave filter (12) to amplify and filtering this signal, is finally launched by antenna transmission module (13).
4. the radar echo signal simulator based on FPGA according to claim 3, it is characterized in that: the matched filter (7) described in described step 2 is formed by subpulse matched filter and the cascade of tap weight delay line summation network two parts, size control VCO voltage-controlled oscillator module (9) of the peak value p that ctrol control module (8) exports according to matched filter (7) and PLL phaselocked loop (10) are to carry out frequency calibration, when local signal frequency does not have identical with the carrier frequency of the echoed signal received, the peak value p that matched filter (7) exports is less than the peak value p exported when Complete Synchronization, now, ctrol control module (8) initialization voltage v0, the voltage v of ctrol control module (8) is made to be increased to v0+ △ v, if the peak value p that matched filter (7) exports increases, then continue to make the voltage v of ctrol control module (8) to increase △ v, otherwise, if the peak value p that matched filter (7) exports reduces, the voltage v of ctrol control module (8) is then made to reduce △ v, repeat aforesaid operations until the peak value p of matched filter (7) reaches maximum, ctrol control module (8) using voltage now as output, the voltage that VCO voltage-controlled oscillator (9) and PLL phaselocked loop (10) export according to ctrol control module (8) exports local signal, now local signal frequency is identical with the carrier frequency of the echoed signal received, local signal exports from PLL phaselocked loop (10).
5. the radar echo signal simulator based on FPGA according to claim 1, is characterized in that: the implementation method of the described information acquisition module based on FPGA (4) is as follows:
Step one: first carry out initialization, obtains range gate Δ R, by formula τ by formula Δ R=2C × Δ τ
0=R
0/ 2C obtains the initial delay time τ of target to radar
0; Wherein Δ τ is minimum interval, and C is the light velocity, R
0for known target is to the initial distance of radar; v
0for the initial radial velocity of target, α is the acceleration of target, wherein α can be 0, on the occasion of or be negative value;
Step 2: make time-parameters t=0 in range gate;
Step 3: by v
0, α, t substitute into
Step 4: judge
whether be more than or equal to Δ R, if
show that now target exceedes range gate Δ R, this seasonal v to the changing value of distance by radar
0=v
0+ at, returns step 2, simultaneously by formula
obtain Doppler shift fd, wherein λ is wavelength, and frequency of utilization is that the sinusoidal signal of fd carries out phase alignment to radar emission signal, continues to perform step 5; Otherwise, make t=t+1, return step 3;
Step 5: the v tried to achieve in determining step four
0whether be greater than 0, if v
0> 0, shows that target is towards radar, then delay time T
0=τ
0-Δ τ, if v
0< 0, represents target and goes away from radar, then delay time T
0=τ
0+ Δ τ;
Step 6: use delay time T
0distance delay calibration is carried out to radar signal, thus obtains the signal after phase alignment and distance delay calibration;
Step 7: use the delay time T that step 5 is tried to achieve
0by formula
obtain the distance R of target to radar, use amplitude A mp ∝ 1/R
4relation amplitude control is carried out to the signal that step 6 obtains, obtain simulate radar return vision signal.
6. the radar echo signal simulator based on FPGA according to claim 1, is characterized in that: described clock control module (5) is implemented as follows:
Step one: produce a stable clock frequency with pulse signal generator, this frequency-adjustable saves;
Step 2: simultaneously supply frequency calibration module and signal message acquisition module by this clock frequency, makes them have identical echo time delay.
7. according to the radar echo signal simulator based on FPGA described in claim 1, it is characterized in that: the noise needed for described noise and spur block (6) produce and noise signal, first to it through digitized process, then analyzable mathematical model is adopted to compare, in the ideal situation by them through row Fourier transform, finally superpose through row with mixed frequency signal, produce complete analogue echoes signal.
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