CN108647173A - A kind of synchronous start pulse signal regenerating unit and its operation method - Google Patents
A kind of synchronous start pulse signal regenerating unit and its operation method Download PDFInfo
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- CN108647173A CN108647173A CN201810864990.1A CN201810864990A CN108647173A CN 108647173 A CN108647173 A CN 108647173A CN 201810864990 A CN201810864990 A CN 201810864990A CN 108647173 A CN108647173 A CN 108647173A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The present invention is a kind of synchronous start pulse signal regenerating unit and its operation method, and the present apparatus includes reference clock generation module, time interval measurement module, input time delay adjustment module, output delay adjustment module and FPGA module.Clock generating module tracks on the basis of its operation method, lock input clock signal, generate clock signal of system, the time difference of time interval measurement module measuring basis clock signal and external sync trigger signal, computation delay controlled quentity controlled variable, FPGA module adjusts the delay value of input time delay adjustment module according to delays time to control amount, the present invention will synchronize start pulse signal regeneration, output multi-channel synchronizes start pulse signal, its repetition rate, pulsewidth, be delayed Independent adjustable, ensure that the phase difference between the synchronization start pulse signal exported after the power is turned on and input pulse signal is less than 200ps every time, improve delay adjustment resolution ratio, reduce the time jitter exported between start pulse signal synchronous with input.
Description
Technical field
The present invention relates to synchronous trigger pulse technology, specially a kind of synchronous start pulse signal regenerating unit and its operation
Method.
Background technology
In the system that high-speed photography system, high-speed data acquisition, Medical Devices and energy etc. need accurate timing control,
Synchronization system is all to maintain the vital link of its normal operation.Some even require synchronization system must have it is low triggering tremble
Dynamic (being less than 500ps), pulsewidth, amount of delay adjustable range are wide, and amount of delay adjusts the resolution ratio that must have picosecond.It is synchronous
Building block of the start pulse signal regenerating unit as synchronization system, performance quality directly affect the fortune of these large scale systems
Line efficiency and running precision.The start pulse signal regeneration realized at present usually using counter process.But even if using
The high-end counter of 100MHz, resolution ratio only up to reach 10ns.And since input start pulse signal and clock are believed
It number is difficult to be aligned, can have a δ t (0 between the start pulse signal and input start pulse signal of output<δt<When 10ns)
Jitter.Therefore existing start pulse signal regenerating unit cannot be satisfied high-accuracy sequential control system operational efficiency and precision
It is required that being badly in need of a kind of new technical solution to effectively improve the resolution ratio of start pulse signal, reduce time jitter.
Invention content
The object of the present invention is to provide a kind of synchronous start pulse signal regenerating units comprising reference clock generates mould
Block, time interval measurement module, input time delay adjustment module, output delay adjustment module and FPGA module.
It is a further object of the present invention to provide a kind of operation method of synchronous start pulse signal regenerating unit, reference clocks
Generation module tracking, locking external input clock signal, and clock signal of system is generated, time interval measurement module measuring basis
Time difference of the rising edge of rising edge clock signal and external sync trigger signal and computation delay controlled quentity controlled variable, FPGA module according to
Delays time to control amount adjusts the delay value of input time delay adjustment module, reduces the time jitter of device output signal, and output delay is adjusted
Save the resolution ratio that module improves device output signal.The present invention has certain fixed frequency synchronous with certain pulsewidth by input
Start pulse signal carries out signal regeneration, and output multi-channel synchronizes start pulse signal, and each road synchronizes the repetition of start pulse signal
Frequency f, pulsewidth p, delay d Independent adjustables, and the randomness of phase difference between system clock and outer triggering signal when powering on is eliminated,
Ensure that the synchronization start pulse signal exported after the power is turned on every time is less than with the phase difference between the external trigger pulse signal of input
200ps, improves delay adjustment resolution ratio, and reduction output synchronizes between start pulse signal start pulse signal synchronous with input
Time jitter.
A kind of synchronous start pulse signal regenerating unit provided by the invention, including reference clock generation module and FPGA moulds
Block, also time interval measurement module, input time delay adjustment module and output delay adjustment module.
External timing signal is input to reference clock generation module, and the output of reference clock generation module is connected to input and prolongs
When adjustment module, the output of input time delay adjustment module is connected to FPGA general purpose I/O feet, and the synchronous triggering signal of input is connected to
FPGA module general purpose I/O foot, time interval measurement module are also connected with the general purpose I/O foot of FPGA；In addition the synchronization of FPGA module
Serial line interface (SPI interface) is respectively connected to time interval measurement module, input time delay adjustment module and output delay adjustment mould
Block, to realize the control to these modules.The Multi-path synchronous start pulse signal of FPGA module output is through exporting delay adjustment mould
It is the Multi-path synchronous start pulse signal of present apparatus output after the adjusting of block.
The external timing signal is the clock frequency signal of 2kHz~710MHz.
The reference clock generation module tracks, locks externally input clock signal and generate clock signal of system,
Its clock signal of system inputs connected input time delay adjustment module；
The delay adjustment resolution ratio of the input time delay adjustment module is picosecond, and regulating system clock signal obtains base
The clock signal input FPGA module；
The time interval measurement of the time interval measurement module is nanosecond, and measurement accuracy is higher than 100 picoseconds；
The delay adjustment resolution ratio of the output delay adjustment module is hundred picoseconds；
The working frequency of the FPGA module is equal to or higher than 100MHz, and contained logic unit is equal to or more than 150000
It is a, and containing clock counter, integrated form pci bus (PCI Express) module, memory and integrated storage control.It is described
Clock counter is 32,100MHz high-frequency clock counters.
It is further connected with Capacitor apart circuit after the output delay adjustment module, the synchronization trigger pulse to improve output is believed
Number reliability, diamagnetic interference performance and transient state anti-interference ability, Multi-path synchronous trigger signal is defeated after Capacitor apart circuit
Go out.
A kind of operation method of synchronous start pulse signal regenerating unit of the present invention is as follows：
Step I, initialization
Synchronous start pulse signal regenerating unit is defined to obtain initial value using the preceding parametric variable to FPGA module, and
It is stored on the internal storage of FPGA module.The parametric variable includes the repetition rate of each road synchronous triggering signal of output
F, pulsewidth p and delay d, the time delayed difference value D0 between synchronous triggering signal rising edge and clock signal of system rising edge and input
Delay adjustment module delay value T0.The delay d is the synchronization start pulse signal trigger pulse letter synchronous with input of output
Delay between number.
In the power-up initializing used for the first time, each road that FPGA module reads output from internal storage synchronizes the present apparatus
The initial value of repetition rate f, the pulsewidth p of trigger signal and the d that is delayed, synchronous triggering signal rising edge rise with clock signal of system
Time delayed difference value D0 and input time delay adjustment module delay value T0, FPGA module between load these parameter variable values.
The FPGA module parameter variable values defined for the first time are repetition rate f=0.1Hz~10MHz, pulsewidth p=10DelayDelay inequality between synchronous triggering signal rising edge and clock signal of system rising edge
D0=0ns~10ns；Input time delay adjustment module delay value T0=3.2ns~11.6ns.
If having modified certain in present apparatus operational process all the way or some or multiple parameters of Multi-path synchronous trigger signal
The value of variable, FPGA module replace the last road preserved in memory with modified parameter value and correspond to parameter value, and
It is stored in FPGA internal storages；Unmodified other parameters variable keeps the value preserved memory the last time.This
For device in the power-up initializing subsequently used, FPGA module will call the parameter variable values currently preserved in memory.
Step II, update input time delay adjustment module delay value T0
External clock signal input reference clock generation module, the tracking of reference clock generation module, locking external input
Clock signal, and the clock signal of system of 2kHz~945MHz is generated, which passes through input time delay adjustment module
After adjusting, input FPGA module is as reference clock signal.
At the same time external synchronization start pulse signal also inputs FPGA module.
FPGA module input time interval measurement together with reference clock signal by external sync start pulse signal
Module, time of the time interval measurement module to external sync start pulse signal rising edge and reference clock signal rising edge
Poor △ D0 carry out 100~200 measurements, and it is D1, delays time to control amount △ D=to take the arithmetic mean of instantaneous value of multiple time interval measurement value
|D1-D0|-200；
As Δ D≤0, the shake between the synchronization start pulse signal start pulse signal synchronous with input of output exists
Ideally, the delay value T0 in the memory of FPGA module is remained unchanged；Current T0 is sent into input and prolonged by FPGA module
When adjustment module, as its delay value；Enter step III；
As △ D>When 0, current delay value T is calculated, the delay value T0 in the memory of FPGA module is updated with T, it is specific to count
It calculates as follows：
If D1<D0, then T=T0+ △ t；
If D1>D0, then T=T0- △ t；
The computational methods of wherein △ t are as follows：
Enable Δ tt=Δs D%10
Variable in formula before " % " expression " % " removes the numerical value gained remainder after " % ",
If Δ tt >=5, △ t=((△ D/10)+1) × 10；
If Δ tt ＜ 5, △ t=(△ D/10) × 10；
"/" indicates that the variable before "/" removes the numerical value acquired results round numbers after "/" in formula.
△ D0 obtained by time interval measurement module are sent into FPGA module, and FPGA module is according to time interval measurement module institute
The △ D0 measured calculate input time delay adjustment module and need the amount of delay △ t adjusted, calculate current delay value T, are updated storage with T
Delay value T0 in device, i.e. T0=T, current T0 is sent into input time delay adjustment module by FPGA module, as its delay value.
Step III, the parameter for adjusting the multichannel start pulse signal exported
FPGA module is according to the parameter value output multi-channel of the repetition rate f, the pulsewidth p that are currently preserved in memory and the d that is delayed
Synchronous start pulse signal to output delay adjustment module, the Multi-path synchronous of the output after output delay adjustment module is adjusted touches
Send out the output that pulse signal is this regenerating unit.
When equipment therefor is further connected with Capacitor apart circuit, the Multi-path synchronous of the output after output delay adjustment module is adjusted
Trigger signal exports after Capacitor apart circuit, is the output of this regenerating unit.
The parameter value per repetition rate f, the pulsewidth p for synchronizing start pulse signal all the way and the d that is delayed of output was being run
Cheng Zhongjun can individually be adjusted according to use demand.
Each road of present apparatus output synchronizes the repetition rate value f (units of start pulse signal：Hz it is) that synchronizing for input is tactile
Send out the integer divide value of pulse repetition frequency.
The pulsewidth p of the synchronization start pulse signal of present apparatus output is ranging from:Pulsewidth p is adjusted
Resolution ratio is 10ns, and the pulsewidth p of the synchronization start pulse signal of output is the integral multiple of 10ns.The synchronization trigger pulse of setting is believed
Feel the pulse wide psetWith the synchronous triggering signal pulsewidth p of outputoutRelationship is as follows：
Enable △ p=pset%10：
If △ p >=5, Pout=((pset/10)+1)×10；
If △ p<5, then Pout=(pset/10)×10。
The delay d of the synchronization start pulse signal of present apparatus output is ranging from：Delay is adjusted
Section resolution ratio is 250ps, and the delay for exporting synchronous start pulse signal is the integral multiple of 250ps.The synchronous triggering signal of setting
Be delayed dsetWith the synchronous triggering signal delay d of outputoutRelationship is as follows：
Enable △ d=dset%250：
If △ d >=125, dout=((dset/250)+1)×250；
If △ d<125, then dout=(dset/250)×250。
The integral multiple part of the 10ns of the synchronous start pulse signal of present apparatus output is adjusted by the counter in FPGA module,
The rest part of the synchronous start pulse signal of output is adjusted by output delay adjustment module.
Step IV, lasting output and re-adjustments
FPGA module output multi-channel synchronizes start pulse signal, is exported for the present apparatus after exporting delay adjustment module.
Capacitor apart electricity is further connected with after the output delay adjustment module of the synchronous start pulse signal regenerating unit
The Multi-path synchronous trigger signal on road, the output after output delay adjustment module is adjusted exports after Capacitor apart circuit, is
The output of this regenerating unit.
Return to step II repeats step II, III and IV, until device is out of service.
Compared with prior art, the beneficial effect of a kind of synchronous start pulse signal regenerating unit of the present invention and its operation method
Fruit is：1, the clock counter in the FPGA module of the present apparatus is 32,100MH high-frequency clock counters, and synchronizing for output is tactile
The pulsewidth of pulse signal, the adjustable range maximum of delay parameter are sent out up to 42 seconds；2, the input time delay adjustment module of the present apparatus
Delay adjustment resolution ratio is picosecond, and the delay adjustment resolution ratio of output delay adjustment module is hundred picoseconds, and time interval is surveyed
The time interval measurement for measuring module is nanosecond, and measurement accuracy is higher than 100 picoseconds, and time interval measurement of the invention is prolonged with input
When adjust, eliminate the randomness of phase difference between system clock and outer triggering signal when powering on, it is ensured that export after the power is turned on every time
Synchronous start pulse signal is less than 200ps with the phase difference between the external trigger pulse signal of input；3, reference clock module with
Track, the externally input clock signal of locking simultaneously generate clock signal of system, and time interval measurement module measures externally input touch
The time difference of the rising edge and clock signal of system rising edge of pulse signal is sent out, and is adjusted from motion tracking, by the synchronous triggering of output
Time jitter between pulse signal start pulse signal synchronous with input is reduced to by the random time shake of δ t less than 500ps；
4, the clock counter in FPGA module carries out coarse delay, and output delay adjustment module carries out accurate adjustment, and the two combination will trigger
Pulse signal delay adjustment resolution ratio is increased to 250ps by 10ns；5, per all the way in the Multi-path synchronous start pulse signal exported
The pulsewidth and delay parameter of signal are independently adjustable；6, the synchronization start pulse signal of the fixed frequency inputted can through apparatus of the present invention
Export the synchronization start pulse signal of the multi-frequency of integral frequency divisioil；7, using Capacitor apart technology, output pulse signal is improved
Reliability, diamagnetic interference performance and transient state anti-interference ability.
Description of the drawings
Fig. 1 is this synchronization start pulse signal regenerating unit example structure schematic diagram；
Fig. 2 is that low jitter of the present invention synchronizes start pulse signal regenerating unit control flow schematic diagram.
Specific implementation mode
The following describes the present invention in detail with reference to the accompanying drawings and specific embodiments.
Synchronous start pulse signal regenerating unit embodiment
The overall structure block diagram of this synchronization start pulse signal regenerating unit embodiment is as shown in Figure 1, include reference clock
Generation module, time interval measurement module, input time delay adjustment module, output delay adjustment module and FPGA module.
External timing signal is input to reference clock generation module, and the output of reference clock generation module is connected to input and prolongs
When adjustment module, the output of input time delay adjustment module is connected to FPGA general purpose I/O feet, the synchronization start pulse signal S of inputin
It is connected to FPGA module general purpose I/O foot, time interval measurement module is also connected with the general purpose I/O foot of FPGA；In addition FPGA module
Synchronous serial interface (SPI interface) be respectively connected to time interval measurement module, input time delay adjustment module and output delay
Adjustment module, to realize the control to these modules.The Multi-path synchronous start pulse signal of FPGA module output is delayed through output
It is the Multi-path synchronous start pulse signal of present apparatus output after the adjusting of adjustment module.
The external timing signal of this example is the clock frequency signal of 10MHz.
When the reference clock generation module of this example tracks, locks externally input clock signal and generate the system of 100MHz
Clock signal, the clock signal of system input connected input time delay adjustment module；
The delay adjustment resolution ratio of the input time delay adjustment module of this example is 10ps, and regulating system clock signal obtains benchmark
FPGA module described in clock signal input；
The time interval measurement of the time interval measurement module of this example is nanosecond, and measurement accuracy is higher than 100 picoseconds；
The delay adjustment resolution ratio of the output delay adjustment module of this example is 250ps；
The working frequency of the FPGA module of this example is 100MHz, contains logic unit 150000, and containing clock counter, collection
Accepted way of doing sth pci bus (PCI Express) module, memory and integrated storage control.The clock counter be 32,
100MHz high-frequency clock counters.
Capacitor apart circuit is further connected with after this example output delay adjustment module, 20 tunnels synchronize start pulse signal by electricity
Hold the S exported after isolation circuitout1To Sout20It is exported for the present apparatus.
The operation method embodiment of synchronous start pulse signal regenerating unit
The operation method embodiment of this synchronization start pulse signal regenerating unit is in above-mentioned synchronization start pulse signal
The method run on regenerating unit, flow is as shown in Fig. 2, be as follows：
Step I, initialization
Synchronous start pulse signal regenerating unit is defined and is stored in using the preceding parametric variable to FPGA module
On the internal storage of FPGA module.The parametric variable initial value that this example defines for the first time is as follows：Each road of output synchronizes triggering letter
Number repetition rate f=1000Hz, pulsewidth p=2us and delay d=50ns, synchronous triggering signal rising edge and system clock believe
Time delayed difference value D0=2800ns between number rising edge and input time delay adjustment module delay value T0=9ns.This example delay d be
The synchronization start pulse signal start pulse signal S synchronous with input of outputinBetween delay.
In the power-up initializing used for the first time, each road that FPGA module reads output from internal storage synchronizes the present apparatus
The initial value of repetition rate f, the pulsewidth p of trigger signal and the d that is delayed, synchronous triggering signal rising edge rise with clock signal of system
Time delayed difference value D0 and input time delay adjustment module delay value T0, FPGA module between load these parameter variable values.
If having modified certain in present apparatus operational process all the way or some or multiple parameters of Multi-path synchronous trigger signal
The value of variable, FPGA module replace the last road preserved in memory with modified parameter value and correspond to parameter value, and
It is stored in FPGA internal storages；Unmodified other parameters variable keeps the value preserved memory the last time.This
For device in the power-up initializing subsequently used, FPGA module will call the parameter variable values currently preserved in memory.
Step II, update input time delay adjustment module delay value T0
External clock signal input reference clock generation module, the tracking of reference clock generation module, locking external input
Clock signal, and generate the clock signal of system of 100MHz, the clock signal of system after the adjusting of input time delay adjustment module,
FPGA module is inputted as reference clock signal.
At the same time external synchronization start pulse signal also inputs FPGA module.The synchronous triggering signal S of this example inputin
Frequency is 1000Hz, pulsewidth 100ns.
FPGA module input time interval measurement module together with reference clock signal by external sync start pulse signal,
Time difference △ of the time interval measurement module to external sync start pulse signal rising edge and reference clock signal rising edge
D0 carries out 200 measurements, and it is D1, delays time to control amount △ D=to take the arithmetic mean of instantaneous value of multiple time interval measurement value | D1-D0 |-
200；
As Δ D≤0, the shake between the synchronization start pulse signal start pulse signal synchronous with input of output exists
Ideally, the delay value T0 in the memory of FPGA module is remained unchanged；Current T0 is sent into input and prolonged by FPGA module
When adjustment module, as its delay value；Enter step III；
As △ D>When 0, current delay value T is calculated, the delay value T0 in the memory of FPGA module is updated with T, it is specific to count
It calculates as follows：
If D1<D0, then T=T0+ △ t；
If D1>D0, then T=T0- △ t；
Wherein △ t are that a position of Δ D is rounded up to the value after ten, and computational methods are as follows：
Enable Δ tt=Δs D%10
Variable in formula before " % " expression " % " removes the numerical value gained remainder after " % ",
If Δ tt >=5, △ t=((△ D/10)+1) × 10；
If Δ tt ＜ 5, △ t=(△ D/10) × 10；
"/" indicates that the variable before "/" removes the numerical value acquired results round numbers after "/" in formula.
△ D0 obtained by time interval measurement module are sent into FPGA module, and FPGA module is according to time interval measurement module institute
The △ D0 measured calculate input time delay adjustment module and need the amount of delay △ t adjusted, calculate current delay value T, are updated storage with T
Delay value T0 in device, i.e. T0=T, current T0 is sent into input time delay adjustment module by FPGA module, as its delay value.
Step III, the parameter for adjusting the multichannel start pulse signal exported
FPGA module is according to the parameter value output multi-channel of the repetition rate f, the pulsewidth p that are currently preserved in memory and the d that is delayed
Synchronous start pulse signal to output delay adjustment module, the Multi-path synchronous of the output after output delay adjustment module is adjusted touches
Hair pulse signal enters Capacitor apart circuit, and the output of Capacitor apart circuit is the output of this regenerating unit.
The parameter value per repetition rate f, the pulsewidth p for synchronizing start pulse signal all the way and the d that is delayed of output was being run
Cheng Zhongjun can individually be adjusted according to use demand.
It is that synchronizing for input is tactile that each road of present apparatus output, which synchronizes repetition rate value f of the start pulse signal as unit of Hz,
Send out the integer divide value of pulse repetition frequency.
The pulsewidth p of the synchronization start pulse signal of present apparatus output is ranging from:Pulsewidth p is adjusted
Resolution ratio is 10ns, and the pulsewidth p of the synchronization start pulse signal of output is the integral multiple of 10ns.The synchronization trigger pulse of setting is believed
Feel the pulse wide psetWith the synchronous triggering signal pulsewidth p of outputoutRelationship is as follows：
Enable △ p=pset%10：
If △ p >=5, Pout=((pset/10)+1)×10；
If △ p<5, then Pout=(pset/10)×10。
The delay d of the synchronization start pulse signal of present apparatus output is ranging from：Delay is adjusted
Section resolution ratio is 250ps, and the delay for exporting synchronous start pulse signal is the integral multiple of 250ps.The synchronous triggering signal of setting
Be delayed dsetWith the synchronous triggering signal delay d of outputoutRelationship is as follows：
Enable △ d=dset%250：
If △ d >=125, dout=((dset/250)+1)×250；
If △ d<125, then dout=(dset/250)×250。
The integral multiple part of the 10ns of the synchronous start pulse signal of present apparatus output is adjusted by the counter in FPGA module,
The rest part of the synchronous start pulse signal of output is adjusted by output delay adjustment module.
Step IV, lasting output and re-adjustments
FPGA module exports 20 tunnels and synchronizes start pulse signal, is after output delay adjustment module and Capacitor apart circuit
The present apparatus exports Sout1To Sout20。
Return to step II repeats step II, III and IV, until device is out of service.
Comparative example uses the high-end counter of 100MHz, is 1000Hz to identical frequency, the input of pulsewidth 100ns triggers
Pulse signal regenerates, and the time jitter between the synchronization start pulse signal start pulse signal synchronous with input of output is
The random value of 0~10ns, resolution ratio highest only reach 10ns.
20 tunnel of the present embodiment reality output synchronizes start pulse signal, is transported after repeatedly shutting down and re-powering initialization again
Row, and continuous work 8 hours, between the synchronization start pulse signal start pulse signal synchronous with input of the output of measurement
Time jitter is less than 500ps, and delay adjustment resolution ratio is increased to 250ps.
By the present embodiment as it can be seen that the operation method of the synchronization start pulse signal regenerating unit of the present invention significantly reduces
Time jitter between the synchronization start pulse signal start pulse signal synchronous with input of output improves delay adjustment point
Resolution.
Above-described embodiment is only further described the purpose of the present invention, technical solution and advantageous effect specific
A example, present invention is not limited to this.All any modifications made within the scope of disclosure of the invention, change equivalent replacement
Into etc., it is all included in the scope of protection of the present invention.
Claims (7)
1. a kind of synchronous start pulse signal regenerating unit, including reference clock generation module and FPGA module, it is characterised in that：
Further include time interval measurement module, input time delay adjustment module and output delay adjustment module；
External timing signal is input to reference clock generation module, and the output of reference clock generation module is connected to input time delay tune
Module is saved, the output of input time delay adjustment module is connected to FPGA general purpose I/O feet, and the synchronous triggering signal of input is connected to FPGA
Module general purpose I/O foot, time interval measurement module are also connected with the general purpose I/O foot of FPGA；In addition the synchronous serial of FPGA module
Interface is respectively connected to time interval measurement module, input time delay adjustment module and output delay adjustment module；FPGA module is defeated
The Multi-path synchronous start pulse signal gone out is the Multi-path synchronous triggering of present apparatus output after exporting the adjusting of delay adjustment module
Pulse signal；
The external timing signal is the clock frequency signal of 2kHz~710MHz；The reference clock generation module with
Track, the externally input clock signal of locking simultaneously generate clock signal of system, and clock signal of system inputs connected input and prolongs
When adjustment module；
The delay adjustment resolution ratio of the input time delay adjustment module is picosecond, when regulating system clock signal obtains benchmark
The clock signal input FPGA module；
The time interval measurement of the time interval measurement module is nanosecond, and measurement accuracy is higher than 100 picoseconds；
The delay adjustment resolution ratio of the output delay adjustment module is hundred picoseconds.
2. synchronous start pulse signal regenerating unit according to claim 1, it is characterised in that：
The working frequency of the FPGA module is equal to or higher than 100MHz, and contained logic unit is equal to or more than 150000,
And contain clock counter, integrated form pci bus module, memory and integrated storage control；The clock counter be 32,
100MHz high-frequency clock counters.
3. synchronous start pulse signal regenerating unit according to claim 1, it is characterised in that：
Capacitor apart circuit is further connected with after the output delay adjustment module, Multi-path synchronous trigger signal is by Capacitor apart electricity
It is exported behind road.
4. the operation method of synchronous start pulse signal regenerating unit according to claim 1 or 2, it is characterised in that specific
Steps are as follows：
Step I, initialization
Synchronous start pulse signal regenerating unit is defined to obtain initial value using the preceding parametric variable to FPGA module, and preserves
On the internal storage of FPGA module；The parametric variable includes repetition rate f, the arteries and veins of each road synchronous triggering signal of output
Wide p and delay d, the time delayed difference value D0 between synchronous triggering signal rising edge and clock signal of system rising edge and input time delay
Adjustment module delay value T0；The delay d be output synchronization start pulse signal start pulse signal synchronous with input it
Between delay；
For the present apparatus in the power-up initializing used for the first time, each road that FPGA module reads output from internal storage synchronizes triggering
The initial value of repetition rate f, the pulsewidth p of signal and the d that is delayed, synchronous triggering signal rising edge and clock signal of system rising edge it
Between time delayed difference value D0 and input time delay adjustment module delay value T0, FPGA module load these parameter variable values；
If having modified certain in present apparatus operational process all the way or some or multiple parameters variable of Multi-path synchronous trigger signal
Value, FPGA module replaces the last road preserved in memory with modified parameter value and corresponds to parameter value, and by its
It is stored in FPGA internal storages；Unmodified other parameters variable keeps the value preserved memory the last time；The present apparatus
In the power-up initializing subsequently used, FPGA module will call the parameter variable values currently preserved in memory；
Step II, update input time delay adjustment module delay value T0
External clock signal input reference clock generation module, the tracking of reference clock generation module, locking external input clock
Signal, and the clock signal of system of 2kHz~945MHz is generated, which is adjusted by input time delay adjustment module
Afterwards, input FPGA module is as reference clock signal；
At the same time external synchronization start pulse signal also inputs FPGA module；
FPGA module input time interval measurement module together with reference clock signal by external sync start pulse signal,
Time difference △ of the time interval measurement module to external sync start pulse signal rising edge and reference clock signal rising edge
D0 carries out 100~200 measurements, and it is D1, delays time to control amount △ D=to take the arithmetic mean of instantaneous value of multiple time interval measurement value | D1-
D0|-200；
As Δ D≤0, the shake between the synchronization start pulse signal start pulse signal synchronous with input of output is in ideal
Under state, the delay value T0 in the memory of FPGA module is remained unchanged；Current T0 is sent into input time delay tune by FPGA module
Module is saved, as its delay value；Enter step III；
As △ D>When 0, current delay value T is calculated, the delay value T0 in the memory of FPGA module is updated with T, it is specific to calculate such as
Under：
If D1<D0, then T=T0+ △ t；
If D1>D0, then T=T0- △ t；
The computational methods of wherein △ t are as follows：
Enable Δ tt=Δs D%10
Variable in formula before " % " expression " % " removes the numerical value gained remainder after " % ",
If Δ tt >=5, △ t=((△ D/10)+1) × 10；
If Δ tt ＜ 5, △ t=(△ D/10) × 10；
"/" indicates that the variable before "/" removes the numerical value acquired results round numbers after "/" in formula；
△ D0 obtained by time interval measurement module are sent into FPGA module, and FPGA module is according to measured by time interval measurement module
△ D0 calculate input time delay adjustment module and need the amount of delay △ t adjusted, calculate current delay value T, updated storage in device with T
Delay value T0, i.e. T0=T, current T0 is sent into input time delay adjustment module by FPGA module, as its delay value；
Step III, the parameter for adjusting the multichannel start pulse signal exported
FPGA module is synchronous with the delay parameter value output multi-channel of d according to repetition rate f, the pulsewidth p currently preserved in memory
Start pulse signal to output delay adjustment module, the Multi-path synchronous of the output after output delay adjustment module is adjusted triggers arteries and veins
Rush the output that signal is this regenerating unit；
The parameter value per repetition rate f, the pulsewidth p and delay d that synchronize start pulse signal all the way of output is in the process of running
It is individually adjusted according to use demand；
Step IV, lasting output and re-adjustments
FPGA module output multi-channel synchronizes start pulse signal, is exported for the present apparatus after exporting delay adjustment module；
Return to step II repeats step II, III and IV, until device is out of service.
5. the operation method of synchronous start pulse signal regenerating unit according to claim 4, it is characterised in that：
The FPGA module parameter variable values that step I defines for the first time are repetition rate f=0.1Hz~10MHz, pulsewidthDelayBetween synchronous triggering signal rising edge and clock signal of system rising edge
Delay inequality D0=0ns~10ns；Input time delay adjustment module delay value T0=3.2ns~11.6ns.
6. the operation method of synchronous start pulse signal regenerating unit according to claim 4, it is characterised in that：
The repetition rate value f as unit of Hz that each road that the present apparatus exports in step III synchronizes start pulse signal is input
The integer divide value of synchronous start pulse signal repetition rate；
The pulsewidth p of the synchronization start pulse signal of present apparatus output is ranging from:Pulsewidth p, which is adjusted, to be differentiated
Rate is 10ns, and the pulsewidth p of the synchronization start pulse signal of output is the integral multiple of 10ns；The synchronization start pulse signal arteries and veins of setting
Wide psetWith the synchronous triggering signal pulsewidth p of outputoutRelationship is as follows：
Enable △ p=pset%10：
If △ p >=5, Pout=((pset/10)+1)×10；
If △ p<5, then Pout=(pset/10)×10；
The delay d of the synchronization start pulse signal of present apparatus output is ranging from：Delay adjustment is differentiated
Rate is 250ps, and the delay for exporting synchronous start pulse signal is the integral multiple of 250ps；The synchronous triggering signal delay d of settingset
With the synchronous triggering signal delay d of outputoutRelationship is as follows：
Enable △ d=dset%250：
If △ d >=125, dout=((dset/250)+1)×250；
If △ d<125, then dout=(dset/250)×250；
The integral multiple part of the 10ns of the synchronous start pulse signal of present apparatus output is adjusted by the counter in FPGA module, output
The rest part of synchronous start pulse signal is adjusted by output delay adjustment module.
7. the operation method of synchronous start pulse signal regenerating unit according to claim 4, it is characterised in that：
It is further connected with Capacitor apart circuit after the output delay adjustment module of the synchronous start pulse signal regenerating unit, through defeated
The Multi-path synchronous trigger signal for going out the output after delay adjustment module is adjusted exports after Capacitor apart circuit, is filled for this regeneration
The output set.
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