CN203870506U - Low frequency clock signal synchronous circuit for multiple redundant computer systems - Google Patents
Low frequency clock signal synchronous circuit for multiple redundant computer systems Download PDFInfo
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Abstract
A low frequency clock signal synchronous circuit for multiple redundant computer systems comprises an external low frequency clock synchronization and local low frequency clock synchronization delay circuit, a majority voting circuit, a signal rising edge detection circuit, a phase deviation judgment and loadable phase counter circuit and a post-local-phase-correction low frequency clock generating circuit. A loadable counter with a counting range of [0,N-1] is adopted, and N frequency division signals of a local work clock are obtained and provided for other redundant computer systems for use. Any computer circuit of each redundant computer system carries out delay and synchronous processing on the frequency division signals and frequency division signals provided by other computer circuits, and then majority voting is conducted. At the moment that rising edges of the signals are extracted after voting is performed, signal synchronization and voting inductive clock delay influences are taken into consideration, the value of the loadable phase counter of local frequency division signals needs to be reset, feedback control of work clock signals of the redundant computer systems is achieved, and therefore synchronization of clock signals is achieved.
Description
Technical field
The utility model relates to a kind of signal synchronization circuit.
Background technology
In Aero-Space, nuclear power control and track traffic etc., control electronics reliability be there is the application scenario of high requirement, often adopt many redundancy computer system designs.Redundant fashion mainly contains triplication redundancy and quadruple modular redundant etc.For many redundancy computer systems, its voting circuit is carried out majority voting to the output of each computer system, can guarantee to have a road or a few computers processing unit generation abnormal failure in system time, and work and output that computer system still can be correct.
In many redundancy computer systems, how to realize each computer system and export to signal synchronous of voting circuit, be the key of the normal work of voting circuit.At present, realize the synchronous method of many redundancy computer systems and be mainly divided into hardware clock synchronously and the synchronous two kinds of approach of software protocol.Wherein, hardware clock synchronously can be subdivided into again common clock and reciprocal feedback independent clock two classes.
In the synchronization policy of use common clock, many redundancy computer systems use public clock signal to drive each computer circuits, realize simply, but this mode exist Single Point of Faliure, has reduced the reliability of redundant system.Therefore, use the synchronization policy of common clock conventionally will not adopt.
In the synchronization policy of the reciprocal feedback independent clock of use, in many redundancy computer systems, each computer circuits use independently clock source to drive, and each computer circuits, using the clock signal of other computer circuits of redundant system as feedback, are dynamically adjusted local clock signal.Owing to adopting independent clock, its reliability is used the reliability of the redundant system of common clock to want high.
At present, clock synchronous scheme based on reciprocal feedback independent clock is in the time of design, in many redundancy computer systems, each computer circuits adopt local frequency dividing circuit to produce separately independently sub-frequency clock signal, the sub-frequency clock signal that the sub-frequency clock signal that each computer circuits produce this plate and other computer circuits of redundancy computer system provide carries out majority voting, after voting, the rising edge moment of signal resets to the local frequency dividing circuit of each computer circuits, thereby realize the consistent of the local frequency dividing circuit count value of each computer circuits and synchronize variation, and then reach the object of the clock signal synchronization that each computer circuits frequency dividing circuit produces.The deficiency of this clock synchronizing method is, after voting, the rising edge moment of signal is carried out forced resetting to the local frequency dividing circuit of each computer circuits, do not consider the phase deviation of the local work clock of each computer circuits, the signal delay inconsistency that asynchronous clock signal synchronizing process is brought, the impact of the factors such as the device transmission delay of sub-frequency clock signal and the inconsistency of circuit transmission delay, causes the frequency accuracy of the synchronous clock signal producing to reduce.
Utility model content
The technical matters that the utility model solves is: overcome the deficiencies in the prior art, a kind of synchronizing circuit of many redundancy computer systems low-frequency clock signal is provided, can realize detection and the correction of the low-frequency clock signal larger to redundant system medium frequency deviation, retain the working attributes of the low-frequency clock signal that redundant system medium frequency deviation is less simultaneously, thereby ensure precision and the consistance of synchronizing clock signals.
Technical solution of the present utility model is: a kind of many redundancy computer systems low-frequency clock signal synchronizing circuit, after comprising external low frequency clock synchronous and local low-frequency clock delay circuit, majority voter, signal rising edge testing circuit, phase deviation judgement and can loading phase counter circuit, local phase correction, low-frequency clock produces circuit, wherein:
External low frequency clock synchronous and local low-frequency clock delay circuit: comprise at least 2T register, respectively each road of the T road clock signal receiving is all carried out exporting after the same delay of two-stage at least, in the signal of T road, T-1 road is the clock signal of outside T-1 redundancy computer system, the clock signal that a road is this computer system;
Majority voter: level synchronous to outside low-frequency clock and the T road clock signal that local low-frequency clock delay circuit is exported carries out majority voting, and the same level state that quantity is exceeded to T/2 is exported as voting result;
Signal rising edge testing circuit: comprise the first register, with door, not gate, described in the first register pair, voting result carries out sending into not gate after level cache, the output of not gate and described voting result are together sent into and door, export the rising edge signal of described voting result with door;
Phase deviation is adjudicated and can be loaded phase counter circuit: comprise that a counting region is [0, N-1] phase counter, alternative multiplexer F1, the loading end of phase counter is input as the output of signal rising edge testing circuit, and the data input pin of phase counter connects the output of alternative multiplexer F1; When the current count value CNT of phase counter is during in [N/2+A-P, N/2+A+P] scope, alternative multiplexer F1 exports CNT+1, otherwise alternative multiplexer F1 output N/2+6; Wherein the size of A equal described T road signal any road included register quantity sum in the register quantity of process and signal rising edge testing circuit, N is the frequency ratio of work clock and the low-frequency clock of computer system, and P is the phase deviation permissibility factor;
After local phase correction, low-frequency clock produces circuit: comprise the second register and alternative multiplexer F2, the selection of alternative multiplexer F2 is controlled by the output of described phase counter, in the time that the output of described phase counter is more than or equal to N/2, alternative multiplexer F2 exports high level, otherwise alternative multiplexer F2 output low level, the output of alternative multiplexer F2 is exported as the clock signal of this computer system after synchronous after the second register is deposited.
Described signal rising edge testing circuit, except the first register, also comprises at least one-level register, after the output of described at least one-level register pair majority voter postpones, delivers to the first register and an input end with door.
The utility model advantage is compared with prior art: the utility model circuit is forming local the loaded counter of counting region for [0, N-1] that adopt of many redundancy computer systems Ge road computer circuits, realizes the Fractional-N frequency signal of local work clock.The arbitrary computer circuits of redundancy computer system produce fractional frequency signal to this locality to carry out respectively, after time delay and synchronous processing, carrying out majority voting with the fractional frequency signal that other computer circuits provide.In the rising edge moment of extracting signal after voting, consider the synchronous impact with deciding by vote the clock delay factor of introducing of signal, the loaded phase counter value that this locality is produced to fractional frequency signal is carried out necessary replacement, thereby realize the FEEDBACK CONTROL of redundancy computer system work clock signal, and then realize the object of clock signal synchronization.The utility model, by introducing many redundancy computer systems frequency deviation of clock permissibility factor, is realized the larger clock of redundant system medium frequency deviation is detected and calibration function.In addition, the utility model circuit has considered to be undertaken by the low frequency signal that other computer circuits of redundant system are provided the impact of the proper phase deviation that synchronous operation causes, and eliminated, in improve digital circuit functional reliability, retain original frequency and the phase attributes of the local low-frequency clock signal that frequency departure is less.
Brief description of the drawings
Fig. 1 is the theory of constitution figure of the utility model signal synchronization circuit;
Fig. 2 is the schematic diagram of the synchronous and local low-frequency clock signal delay circuit of the utility model signal synchronization circuit peripheral low-frequency clock signal;
Fig. 3 is the schematic diagram of majority voter in the utility model signal synchronization circuit;
Fig. 4 is the schematic diagram of signal rising edge testing circuit in the utility model signal synchronization circuit;
Fig. 5 is phase deviation judgement and the schematic diagram that can load phase counter circuit in the utility model signal synchronization circuit;
Fig. 6 be in the utility model signal synchronization circuit after local phase correction low-frequency clock produce the schematic diagram of circuit.
Embodiment
As shown in Figure 1, be the composition structural drawing of many redundancy computer systems low-frequency clock signal synchronizing circuit of the present utility model.After this main circuit will and can load phase counter circuit, local phase correction by external low frequency clock synchronous and local low-frequency clock delay circuit, majority voter, signal rising edge testing circuit, phase deviation judgement, low-frequency clock produces the electric circuit constitute.
External low frequency clock synchronous and local low-frequency clock delay circuit are realized the clock signal that outside redundant computer circuit board is provided and are carried out three grades synchronously, and the clock signal of this computer circuit board is carried out to three grades and deposit, thereby the delayed impact synchronously bringing is carried out in compensation to outside redundant computer circuit board low-frequency clock signal, realize the time-delay consistency of local frequency-dividing clock and outside redundant computation mounted circuit board frequency-dividing clock.
The level state of the local clock signal of majority voter to the external timing signal after synchronous and after depositing carries out majority voting.
The rising edge moment of signal rising edge testing circuit for extracting majority voter output signal.
Phase deviation is adjudicated and can be loaded the rising edge moment of phase counter circuit in voting circuit output signal, according to frequency departure scope court verdict, resets to loading counter.
After local phase correction, low-frequency clock produces circuit according to the currency that can load counter, relatively the local clock signal after output calibration.
The structure of external low frequency clock synchronous and local low-frequency clock delay circuit as shown in Figure 2, completes the low-frequency clock signal that in many redundant systems, other computer circuits provide is carried out to synchronous operation.Therewith herewith, the low-frequency clock signal that this locality is produced is deposited processing, can play the inconsistent effect of phase delay of low-frequency clock signal of other computer circuits after eliminating before majority voting local low-frequency clock and synchronizeing.According to the principle of asynchronous signal being carried out at least 2 beating-in step processing, can adjust accordingly 3 beating-in step circuits shown in Fig. 2.
The structure of majority voter as shown in Figure 3.The low-frequency clock signal after depositing (being 3 bats in this example) that (being 3 bats in this example) signal after majority voter postpones local low-frequency clock signal and other computer circuits of redundancy computer system provide carries out majority voting, and low-frequency clock signal clk_vote after output voting.The level state of whole low-frequency clock signals of majority voter statistics input, when the level state value quantity that is the input low-frequency clock signal of logic ' 0 ' exceedes a half of low-frequency clock signal sum, clk_vote output logic ' 0 ', otherwise output logic ' 1 '.
The structure of signal rising edge testing circuit as shown in Figure 4.In figure, register 10 is realized the one-level of majority voter output signal clk_vote is deposited, after producing majority voting, low-frequency clock postpones 1 bat signal clk_vote_dly1, and signal clk_vote_dly1 low-frequency clock after register 11 produces majority voting postpones 2 and claps signal clk_vote_dly2.Signal clk_vote_dly2 is through non-output behind the door, and together sends into signal clk_vote_dly1 the rising edge signal clk_vote_ris_edge that produces low-frequency clock after majority voting with door.If based on the consideration that reduces circuit and realize expense, register 10 can omit.
Phase deviation judgement and the structure that can load phase counter circuit are as shown in Figure 5.Wherein, the counting region that can load phase counter is [0, N-1], and in the time that load signal is invalid, phase counter is carried out and added 1 operation, realizes N times of frequency division object of local clock.After the local phase correction shown in Fig. 6, low-frequency clock produces in circuit, in the time that phase counter output CNT>=N/2 sets up, select the D1 end of alternative multiplexer 2, current phase counter value is relatively exported cnt_comp output logic ' 1 ', otherwise, cnt_comp output logic ' 0 '.That is to say, when CNT is during in [0, N/2-1] scope, cnt_comp output ' 0 ', when CNT is during in [N/2, N-1] scope, cnt_comp output ' 1 ', realizes the object that cnt_comp signal dutyfactor is 1:1.Register 12 is for depositing the cnt_comp signal being produced by combinational logic, and exports local low-frequency clock signal local_clk, plays the object of eliminating burr.
Adjudicate and can load in phase counter circuit in the phase deviation shown in Fig. 5, after majority voting, low-frequency clock rising edge signal clk_vote_ris_edge is as the load signal that can load phase counter.In the time that load signal is effective, if phase counter currency CNT is at [N/2+5-P, N/2+5+P] (N/2+5 is the desired value of local phase counter when low-frequency clock rising edge signal is effective after voting when scope, constant 5 is corresponding to the delay beat sum of signal synchronization circuit and signal rising edge testing circuit, wherein, signal synchronization circuit postpones triple time, and signal rising edge testing circuit postpones one to be clapped, and after local phase correction, low-frequency clock generation circuit delay one is clapped; P is the phase deviation permissibility factor, the work clock cycle of the each circuit of many redundancy computer systems and the product of 2P, should be less than redundant system the maximum of low-frequency clock signal phase place is allowed to phase deviation, and be greater than the deviation of external low frequency clock signal transmission delay and local low-frequency clock signal transmission delay), the sel port driver logic of alternative multiplexer 1 is ' 1 ', now, alternative multiplexer 1 output port Q is driven by its input port D1, the data loaded value of phase counter is CNT+1, does not carry out phase place and forces to adjust operation; Otherwise, if phase counter currency CNT is not in [N/2+5-P, N/2+5+P] when scope, the data loaded value of phase counter is that N/2+6(postpones on the basis of 5 clock period at signal synchronization circuit and signal rising edge testing circuit, phase place load operation postpones a clock period, therefore, data loaded value should be N/2+6).
The content not being described in detail in the utility model instructions belongs to those skilled in the art's known technology.
Claims (2)
1. the synchronizing circuit of redundancy computer system low-frequency clock signal more than a kind, it is characterized in that: after comprising external low frequency clock synchronous and local low-frequency clock delay circuit, majority voter, signal rising edge testing circuit, phase deviation judgement and can loading phase counter circuit, local phase correction, low-frequency clock produces circuit, wherein:
External low frequency clock synchronous and local low-frequency clock delay circuit: comprise at least 2T register, respectively each road of the T road clock signal receiving is all carried out exporting after the same delay of two-stage at least, in the signal of T road, T-1 road is the clock signal of outside T-1 redundancy computer system, the clock signal that a road is this computer system;
Majority voter: level synchronous to outside low-frequency clock and the T road clock signal that local low-frequency clock delay circuit is exported carries out majority voting, and the same level state that quantity is exceeded to T/2 is exported as voting result;
Signal rising edge testing circuit: comprise the first register, with door, not gate, described in the first register pair, voting result carries out sending into not gate after level cache, the output of not gate and described voting result are together sent into and door, export the rising edge signal of described voting result with door;
Phase deviation is adjudicated and can be loaded phase counter circuit: comprise that a counting region is [0, N-1] phase counter, alternative multiplexer F1, the loading end of phase counter is input as the output of signal rising edge testing circuit, and the data input pin of phase counter connects the output of alternative multiplexer F1; When the current count value CNT of phase counter is during in [N/2+A-P, N/2+A+P] scope, alternative multiplexer F1 exports CNT+1, otherwise alternative multiplexer F1 output N/2+6; Wherein the size of A equal described T road signal any road included register quantity sum in the register quantity of process and signal rising edge testing circuit, N is the frequency ratio of work clock and the low-frequency clock of computer system, and P is the phase deviation permissibility factor;
After local phase correction, low-frequency clock produces circuit: comprise the second register and alternative multiplexer F2, the selection of alternative multiplexer F2 is controlled by the output of described phase counter, in the time that the output of described phase counter is more than or equal to N/2, alternative multiplexer F2 exports high level, otherwise alternative multiplexer F2 output low level, the output of alternative multiplexer F2 is exported as the clock signal of this computer system after synchronous after the second register is deposited.
2. many redundancy computer systems of one low-frequency clock signal synchronizing circuit according to claim 1, it is characterized in that: described signal rising edge testing circuit is except the first register, also comprise at least one-level register, after the output of described at least one-level register pair majority voter postpones, deliver to the first register and an input end with door.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110023854A (en) * | 2016-12-03 | 2019-07-16 | Wago管理有限责任公司 | The control of redundant processing unit |
| CN110166046A (en) * | 2019-05-20 | 2019-08-23 | 电子科技大学 | Sequential equivalent system based on phase delay |
| CN111650992A (en) * | 2020-06-03 | 2020-09-11 | 中国民航大学 | Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit |
| CN116339608A (en) * | 2023-05-29 | 2023-06-27 | 珠海妙存科技有限公司 | Data sampling method, system, chip, device and storage medium |
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2014
- 2014-04-08 CN CN201420167429.5U patent/CN203870506U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110023854A (en) * | 2016-12-03 | 2019-07-16 | Wago管理有限责任公司 | The control of redundant processing unit |
| CN110023854B (en) * | 2016-12-03 | 2022-04-01 | Wago管理有限责任公司 | Control of redundant processing units |
| CN110166046A (en) * | 2019-05-20 | 2019-08-23 | 电子科技大学 | Sequential equivalent system based on phase delay |
| CN111650992A (en) * | 2020-06-03 | 2020-09-11 | 中国民航大学 | Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit |
| CN111650992B (en) * | 2020-06-03 | 2023-03-14 | 中国民航大学 | Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit |
| CN116339608A (en) * | 2023-05-29 | 2023-06-27 | 珠海妙存科技有限公司 | Data sampling method, system, chip, device and storage medium |
| CN116339608B (en) * | 2023-05-29 | 2023-08-11 | 珠海妙存科技有限公司 | Data sampling method, system, chip, device and storage medium |
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