CN111650992B - Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit - Google Patents
Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit Download PDFInfo
- Publication number
- CN111650992B CN111650992B CN202010493325.3A CN202010493325A CN111650992B CN 111650992 B CN111650992 B CN 111650992B CN 202010493325 A CN202010493325 A CN 202010493325A CN 111650992 B CN111650992 B CN 111650992B
- Authority
- CN
- China
- Prior art keywords
- data
- enable
- enabling
- clock
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Hardware Redundancy (AREA)
Abstract
A multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy. The system comprises a data/enable signal extension state machine, an enable level synchronizer, an enable judgment unit, a data selection output unit and an enable beat unit; wherein: the data output end of the data/enable signal extension state machine is connected with the data selection output unit, and the enable output end of the data/enable signal extension state machine is connected with the enable level synchronizer; the enabling level synchronizer is connected with the enabling judgment unit; the enabling judgment unit is connected with the data selection output unit and the enabling beating connection. The invention solves the problem that the voter can not output correct data due to a certain path of upset of a clock domain crossing synchronous circuit in the triple modular redundancy design, so that the triple modular redundancy circuit loses the single event upset resistance, and can still normally work under the condition that metastable state and a certain redundant circuit single event upset occur simultaneously when being applied to the triple modular redundancy circuit.
Description
Technical Field
The invention belongs to the technical field of electronic equipment, is suitable for digital logic circuit design, and particularly relates to a multi-bit data clock domain crossing synchronization circuit suitable for a triple modular redundancy circuit.
Background
With the increase of the electronic hardware design scale and the appearance of System On Chip (SOC), clock domain crossing signal circuits in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) designs have increased correspondingly, so that the probability of metastability caused by clock domain crossing in the circuits has also increased, and therefore, a clock domain crossing synchronizer is required to achieve a low metastability transfer probability. However, if the existing clock domain crossing synchronizer is directly applied to the triple-modular redundancy circuit, because the actual layout and wiring conditions hardly make the delays of the corresponding connecting lines of the three redundancy circuits completely consistent, the complete synchronous change of three values transmitted to a target clock domain cannot be ensured, and when a certain path is overturned, the voter cannot effectively judge and output a correct value, so that the triple-modular redundancy circuit loses the single event upset resistance.
The triple modular redundancy circuit is a circuit which copies the same functional module three times, and then uses a voting circuit to make majority selection decision at the output end, and the structure is shown in fig. 2.
The first, second, and third redundant modules shown in fig. 2 perform the same logical functions. The outputs of the redundant blocks are commonly connected to a voting circuit. The voting circuit may also perform triple redundancy, and the triple-modular redundancy circuit of fig. 2 also performs triple redundancy on the voting circuit, that is, vote 1, vote 2, and vote 3. The voting circuit implements a majority voter function, as shown in fig. 3, F = AB + AC + BC (where F is the output and a, B, C are the inputs); if the voting circuit outputs multi-bit data, each bit (nth bit) of the data bit implements the function of F [ n ] = a [ n ] B [ n ] + a [ n ] C [ n ] + B [ n ] C [ n ].
When the triple-modular redundancy circuit shown in fig. 2 is used, the same inputs q1, q2 and q3 are respectively input to the data input ends of the first redundancy module, the second redundancy module and the third redundancy module, and the initial states of the three redundancy modules are ensured to be consistent. If the redundancy design is a synchronous clock domain design (without a cross-clock path), the same outputs a, B and C can be obtained simultaneously under the condition that each redundancy module works normally. If a certain output A, B or C has an error, if single-event inversion occurs, the output F _ V1, F _ V2 and F _ V3 are still correct values after passing through the voting circuit.
If the redundant module in fig. 2 contains a cross-clock domain transmission path, i.e., the redundant module contains a cross-clock domain synchronizer (i.e., the circuitry required to transfer data from one clock domain to another, including but not limited to level synchronizers, rising edge synchronizers, asynchronous FIFOs, data selection synchronization circuitry, etc.), the redundant circuitry may lose interference immunity. As shown in fig. 4, ideally, if the inputs q1_ Txclk, q2_ Txclk, and q3_ Txclk are input into each cross-clock domain synchronizer at the same time (the inputs q1_ Txclk, q2_ Txclk, q3_ Txclk transition at the same time according to the transmit clock domain clock), we expect the values of the synchronizer outputs Rx _ sig _ C1, rx _ sig _ C2, rx _ sig _ C3 of the three redundant modules to change at the same time in the receive clock domain. However, since signals are transmitted across clock domains, it is difficult to ensure that the wires, clock paths, operating environments (such as circuit supply voltage and electromagnetic interference), and register characteristic parameters inside the synchronous circuit are completely consistent, which may cause the output Rx _ sig _ C1, rx _ sig _ C2, and Rx _ sig _ C3 of the synchronizers of the three redundant modules to fail to change synchronously in the receiving clock domain. As in the case of scene 2 and scene 3 shown in the upper part of fig. 5. Because a metastable state occurs in a clock domain crossing path, the output Rx _ sig _ C1 of the synchronizer of the redundancy module 1 in the scene 2 is earlier than the ideal condition by one receiving clock period; in scenario 3, the synchronizer output Rx _ sig _ C3 of the redundancy module 3 is delayed by one receiving clock cycle (the effective pulse width (high level) of the synchronizer outputs Rx _ sig _ C1, rx _ sig _ C2 and Rx _ sig _ C3 of the three redundancy modules is one clock cycle of the receiving clock), which reduces the capability of the triple-mode redundancy circuit against single particles. As shown in the lower part of fig. 5, if the first redundancy module is single event flipped, so that the synchronizer output Rx _ sig _ C1 of the redundancy module 1 is fixed to 0, the triple modular redundancy method cannot mask the single event flipped error of the first redundancy module under scenario 3, resulting in the output Rx _ sig _ voter of the voting circuit being 0.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a multi-bit data clock domain crossing synchronization circuit suitable for a triple modular redundancy circuit.
In order to achieve the above object, the multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit provided by the present invention comprises:
the system comprises a data/enable signal extension state machine, an enable level synchronizer, an enable judgment unit, a data selection output unit and an enable beat unit; wherein: the data output end of the data/enable signal extension state machine is connected with the data selection output unit, and the enable output end of the data/enable signal extension state machine is connected with the enable level synchronizer; the enabling level synchronizer is connected with the enabling judgment unit; the enabling judgment unit is connected with the data selection output unit and the enabling beat unit; the data/enable signal extension state machine receives the first clock input signal tx _ clk; the enabling level synchronizer, the enabling judgment unit, the data selection output unit and the enabling beat receiving second clock input signal rx _ clk; the data/enable signal extension state machine requires that an enable signal tx _ en _ P _ x of one transmission clock cycle and a data signal tx _ data _ P _ x of one transmission clock cycle are input at the same time; the enable output end of the enable level synchronizer is connected to an enable output port of the whole clock domain crossing multi-bit data selector synchronous circuit suitable for the triple modular redundancy circuit; the data output end of the data selection output unit is connected to the data output port of the whole clock domain crossing multi-bit data selector synchronous circuit suitable for the triple modular redundancy circuit; the enable decision unit is connected with output ports en _ rxclk _ y, en _ rxclk _ z of the other two data selection synchronization units, namely an enable signal en _ rxclk _2 of the second redundancy module and an enable signal en _ rxclk _3 of the third redundancy module respectively; the data selection output unit is connected with the redundant data output ports rx _ data _ y and rx _ data _ z of the other two data selection synchronous units, namely the data signal rx _ data _2 of the second redundant module and the data signal rx _ data _3 of the third redundant module respectively.
The first clock input signal tx _ clk and the second clock input signal rx _ clk are asynchronous clock signals of two different sources.
The enabling level synchronizer is composed of two registers C and D which are directly connected and used for relieving the probability of metastable state occurrence.
The enabling decision unit consists of a majority voter and a rising edge pulse generator circuit.
The data selection output unit comprises a 2-to-1 data selector mux, a bit-based majority Voter Voter2 and a data output register E.
The multi-bit data clock domain crossing synchronization circuit suitable for the triple modular redundancy circuit solves the problem that a voter cannot output correct data due to the fact that a certain path of the clock domain crossing synchronization circuit in the triple modular redundancy design is overturned, so that the triple modular redundancy circuit loses the single event upset resistance, and can still normally work under the condition that a metastable state and a certain redundancy circuit single event upset happen simultaneously when being applied to the triple modular redundancy circuit.
Drawings
Fig. 1 is a schematic structural diagram of a multi-bit data clock domain crossing synchronization circuit suitable for a triple modular redundancy circuit according to the present invention.
Fig. 2 is a block diagram of a prior art triple modular redundancy circuit.
Fig. 3 is a schematic diagram of a voting circuit implementation of the prior art.
FIG. 4 is a block diagram of a prior art implementation of a three-mode circuit with a cross-clock domain design.
FIG. 5 is a timing diagram of a prior art clock domain crossing circuit for three-mode applications.
Fig. 6 is a circuit port block diagram of three redundant data selection synchronization units in a multi-bit data clock domain crossing synchronization circuit suitable for a triple modular redundancy circuit according to the present invention.
Fig. 7 is a state transition diagram of a data/enable signal extension state machine in a multi-bit data cross-clock domain synchronization circuit suitable for a triple modular redundancy circuit according to the present invention.
Fig. 8 is a diagram of an implementation of a rising edge pulse generator circuit in a multi-bit data clock domain crossing synchronization circuit suitable for a triple modular redundancy circuit according to the present invention.
Fig. 9 is a timing diagram of the principle of single event upset resistance of the triple-modular redundancy cross-clock domain synchronization circuit in the multi-bit data cross-clock domain synchronization circuit suitable for the triple-modular redundancy circuit according to the present invention.
Detailed Description
The structure and the using method of the multi-bit data clock domain crossing synchronization circuit (here, the data selection synchronization unit is named as Dmux _ t) suitable for the triple modular redundancy circuit according to the present invention are described in detail below with reference to the accompanying drawings and specific embodiments.
First, the port and the link mode of the data selection synchronization unit Dmux _ t when implementing the triple modular redundancy circuit will be described. The invention uses three data selection synchronization units Dmux _ t to be connected with each other to form a triple modular redundancy circuit Dmux _ R. The triple-modular redundancy circuit Dmux _ R is generally formed by instantiating the data selection synchronization unit Dmux _ t shown in fig. 1 three times, where the first data selection synchronization unit Dmux _ t1 serves as a first redundancy module, the second data selection synchronization unit Dmux _ t2 serves as a second redundancy module, and the third data selection synchronization unit Dmux _ t3 serves as a third redundancy module. They implement the same logical functions.
The ports of the redundancy module Dmux _ R are explained below with reference to fig. 6:
the following describes the port of the first redundant module Dmux _ t 1:
the port of the second redundancy module Dmux _ t2 is explained below:
the port of the third redundancy module Dmux _ t3 is explained below:
the first data selection synchronization unit, the second data selection synchronization unit and the third data selection synchronization unit follow the same named rule of linking together. The three data selection synchronization units are organized together according to the port description and the link rule to form a triple modular redundancy circuit together. The three enable signals tx _ en _ P _1, tx _ en _ P _2, tx _ en _ P _3 change simultaneously, and the values of the three data signals tx _ data _ P _1, tx _ data _ P _2, tx _ data _ P _3 also change simultaneously and are equal.
The following describes the structural composition of the internal circuit of the multi-bit data clock domain crossing synchronization circuit (data selection synchronization unit Dmux _ t) suitable for the triple modular redundancy circuit provided by the present invention. Since the circuit structures and functions of the three data selection synchronizing units are completely consistent, the circuit structure and functions will be described below by taking the first data selection synchronizing unit as an example. In this case, x in FIG. 1 represents 1, y represents 2, and z represents 3. ( If FIG. 1 represents a second data selection sync unit, then x represents 2, y represents 1, and z represents 3. If FIG. 1 represents a third data selection sync element, then x represents 3, y represents 1, z represents 2 )
As shown in fig. 1, the multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy according to the present invention includes:
a data/enable signal extension state machine 1, an enable level synchronizer 2, an enable decision unit 3, a data selection output unit 4 and an enable beat 5; wherein: the data output end of the data/enable signal extension state machine 1 is connected with the data selection output unit 4, and the enable output end of the data/enable signal extension state machine 1 is connected with the enable level synchronizer 2; the enable level synchronizer 2 is connected with the enable judgment unit 3; the enabling judgment unit 3 is connected with the data selection output unit 4 and the enabling beat 5; the data/enable signal extension state machine 1 receives the first clock input signal tx _ clk; the enable level synchronizer 2, the enable decision unit 3, the data selection output unit 4 and the enable beat 5 receive a second clock input signal rx _ clk; the data/enable signal extension state machine 1 requires to input an enable signal tx _ en _ P _ x (here, the enable signal tx _ en _ P _ 1) of one transmission clock cycle T1 and a data signal tx _ data _ P _ x (at this time, the port link enable signal tx _ data _ P _ 1) of one transmission clock cycle T1 at the same time; the enable output end of the enable level synchronizer 2 is connected to an enable output port of the whole clock domain crossing multi-bit data selector synchronous circuit suitable for the triple modular redundancy circuit; the data output end of the data selection output unit 4 is connected to the data output port of the whole clock domain crossing multi-bit data selector synchronous circuit suitable for the triple modular redundancy circuit; the enable decision unit 3 is connected to the output ports en _ rxclk _ y, en _ rxclk _ z (refer to the enable signal en _ rxclk _2 of the second redundant block and the enable signal en _ rxclk _3 of the third redundant block, respectively) of the other two data selection synchronization units; the data selection output unit 4 is connected to the redundant data output ports rx _ data _ y and rx _ data _ z (rx _ data _ y refers to the data signal rx _ data _2 of the second redundant module and rx_data \ u z refers to the data signal rx _ data _3 of the third redundant module) of the other two data selection synchronization units.
The first clock input signal tx _ clk and the second clock input signal rx _ clk are asynchronous clock signals of two different sources.
In the data/enable signal extension state machine 1, an enable signal tx _ en _ P _1 and a data signal rx _ data _1 of one transmission clock cycle T1 are input, and output is
An extended enable signal of the length of one transmit clock cycle T1,
an extended data signal of length of one transmission clock cycle T1: (
Represent a round-down operator); the extended data signal is registered and output by a data register A, and the extended enable signal is registered and output by an enable register B; adjacent data transmission interval is maintained at least
The length of one transmission clock period T1, i.e., two enable signals tx _ en _ P _1 to be maintained
Interval of one transmission clock cycle T1
As shown in FIG. 7, the data/enable signal extension state machine 1 is reset and enters the IDLE state, when the enable signal tx _ EN _ P _1 is high, it enters the EN _ D state, and the Counter1 of the clock domain of the transmission clock period T1 starts counting from 0 and counts to
The state machine jumps to the DATA _ D state, where the Counter2 starts counting from zero and counts to
When this happens, the state machine jumps from DATA _ D to the IDLE state.
State IDLE output:
the data/enable signal extends the enable output tx _ en _1 of the state machine 1=0; data output tx _ data _1 of the data/enable signal extension state machine 1: the original value is kept unchanged.
State EN _ D output:
the data/enable signal extends the enable output tx _ en _1=1 of the state machine 1, and the data output tx _ data _1= tx \_data \p_1 of the state machine 1
(value of tx _ data _ P _1r at tx _ en _ P _1 high level).
State DATA _ D output:
the data/enable signal extends the enable output tx _ en _1 of the state machine 1=0, the data output tx _ data _1 of the state machine 1: remain unchanged.
The enabling level synchronizer 2 is composed of two directly connected registers C and D and is used for relieving the probability of metastable state occurrence.
The enabling decision unit 3 consists of a majority voter and a rising edge pulse generator circuit; the enable signal for the decision enable level synchronizer 2 output and the outputs en _ rxclk _ y, en _ rxclk _ z of the other two redundant modules (refer to the output en _ rxclk _2 of the second redundant module and the output en _ rxclk _3 of the third redundant module, respectively). The decision mechanism is a majority voter; the majority voter implements the function of F = a × B + a × C + B × C (where F is the output and a, B, C are the inputs), and the circuit diagram is shown in fig. 3; the output of the majority voter is input to a rising edge pulse generator for generating one reception clock cycle T2, the circuit diagram of which is shown in fig. 8, i.e., the enable pulse signal en _ rxclk _ P = en _ rxclk _ v & (| en _ rxclk _ v _ d). The enable voting delay signal en _ rxclk _ v _ d delays the enable voting signal en _ rxclk _ v by one receive clock cycle T2.
The data selection output unit 4 comprises a 2-to-1 data selector mux, a bit-based majority Voter Voter2 (namely, each bit of data selects a corresponding value according to the majority Voter), and a data output register E; the 1-from-2 data selector mux selects a signal as an output enable pulse signal en _ rxclk _ P of the enable decision unit 3, one end of a data input terminal of the 1-from-2 data selector mux is a data output terminal tx _ data _1 of the data/enable signal extension state machine 1, and the other end of the data input terminal is an output terminal rx _ data _ v of the bit-wise majority Voter 2. When the output enable pulse signal en _ rxclk _ P is at a high level, the 1-out-of-2 data selector mux selects the data output tx _ data _1 of the data/enable signal extension state machine 1 as an output, and when the output enable pulse signal en _ rxclk _ P is at a low level, the 1-out-of-2 data selector mux selects the output rx _ data _ v of the bit-based majority Voter2 as an output. One input end of the bitwise majority Voter Voter2 is an output end of the data output register E, the other two inputs are data outputs of a redundancy module, and the data output ports of rx _ data _ y and rx _ data _ z (rx _ data _ y and rx _ data _ z respectively refer to rx _ data _2 and rx _ xu _ data \ 3); each bit of the data bits implements the function of the circuit diagram shown in fig. 2.
rx_data[n]＝rx_data_x[n]*rx_data_y[n]+rx_data_x[n]*rx_data_z[n]+rx_data_y[n]*rx_data_z[n]。
The enable beat 5 delays the output enable pulse signal en _ rxclk _ P of the enable decision unit 3 by two clock beats in order to validate the output data rx _ data _1 when the output enable pulse signal en _ rxclk _ P _1 is high.
The working principle of the circuit is explained as follows:
the data/enable signal extension state machine 1, the enable level synchronizer 2, the enable judgment unit 3, the data selection output unit 4 and the enable beat 5 can be realized on an FPGA or an ASIC by adopting a hardware description language. With this circuit, the data and enable signals are first stretched by the data/enable signal stretching state machine 1 in the data select synchronizing unit, stretching the enable signal tx _ en _ P _1 for one transmit clock cycle T1 and the data signal tx _ data _ P _1 for one transmit clock cycle T1. After extending the state machine 1 by a data/enable signal, it is generated
The data/enable signal that is long enough for one transmission clock cycle T1 extends the enable output signal tx _ en _1 of the state machine 1,
The data/enable signal, which is long for one receive clock cycle T2, extends the data output tx _ data _1 of the state machine 1 and ensures that the next data interval remains between data transmissions and the current data intervalThe interval is to be maintained at least
One transmission clock period T1. The enable output signal tx _ en _1 of the data/enable signal extension state machine 1 is output to the enable level synchronizer 2, and since the path is transferred across clock domains, the enable level synchronizer 2 is used, and the probability of metastable state occurrence is reduced. Since the enable signal tx _ en _ P _1 for one transmit clock cycle T1 is stretched using the data/enable signal stretching state machine 1, the active level of the generated enable level synchronizer output en _ rxclk _1 when the enable output signal tx _ en _1 of the data/enable signal stretching state machine 1 is transmitted to the receive clock domain may be made longer than two receive clock cycles T2. The output en _ rxclk _1 of the enable level synchronizer 2, the output en _ rxclk _2 of the enable level synchronizer 2 of the second redundant module, and the output en _ rxclk _3 of the enable level synchronizer 2 of the third redundant module are output to a majority voter of the enable decision unit 3.
en_rxclk_v＝en_rxclk_1*en_rxclk_1+en_rxclk_1*en_rxclk_3+en_rxclk_2*en_rxclk_3。
The enabling level synchronizer 2 ensures that in a redundant module, if a certain redundant module goes wrong, the enabling judger can still output correct results. Since the metastable state causes the enable level synchronizer 2 to output en _ rxclk _1, en _rxclk _, or en _ rxclk _3, which cannot arrive at the same time at the same receiving clock active edge of the same receiving clock domain, but since the enable level synchronizer 2 outputs en _ rxclk _1, en _rxclk _, or en _ rxclk _3, which is maintained for at least two clock cycles, it can be ensured that the enable decider can still output an active enable signal in the event of a flip error in a redundant circuit at the active clock sampling edge of a certain receiving clock, as shown in the right side of fig. 9. The output enable voting signal en _ rxclk _ v is output to the rising edge pulse generator circuit, so that the output enable pulse signal en _ rxclk _ P is ensured to have only one valid period of the receiving clock, and the repeated output of data in the receiving clock domain can be avoided.
The output enable pulse signal en _ rxclk _ P signal is linked to the data selection output unit 4. The 1-out-of-2 data selector mux selects the data output tx _ data _1 of the state machine 1 as an output when the output enable pulse signal en _ rxclk _ P is high, and selects the discrimination data signal rx _ data _ v as an output when the output enable pulse signal en _ rxclk _ P is low. Each bit output by the discrimination data signal rx _ data _ v is equal to the majority voting result of the corresponding bit of rx _ data _ x, rx _ data _ y, rx _ data _ z: rx _ data _ v [ n ] = rx _ data _ x [ n ]. Rx _ data _ y [ n ] + rx _ data _ x [ n ]. Rx _ data _ z [ n ] + rx _ data _ y [ n ]. Rx _ data _ z [ n ].
Thus, if one bit of rx _ data _ x [ n ] \ rx _ data _ y [ n ] \ rx _ data _ z [ n ] is flipped, the discrimination data signal rx _ data _ v can still output a correct value.
In order to determine the valid output time of the data signal rx _ data _1, the enable pulse signal en _ rxclk _ P is delayed by an enable beat 5, and after the enable pulse signal en _ rxclk _ P is delayed by two receiving clock cycles T2, the enable beat 5 outputs en _ rxck _ P _1. When the enable beat 5 output en _ rxck _ P _1 is high, the data signal rx _ data _1 is valid.
The multi-bit data cross-clock-domain synchronization circuit suitable for triple modular redundancy solves the problem that when a certain cross-clock-domain synchronization circuit is subjected to single event upset, the triple modular redundancy circuit can output error data or lose data.
Claims (5)
1. A multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy, comprising: the multi-bit data cross clock domain synchronization circuit suitable for triple modular redundancy comprises:
the device comprises a data/enable signal extension state machine (1), an enable level synchronizer (2), an enable judgment unit (3), a data selection output unit (4) and an enable beat unit (5); wherein: the data output end of the data/enable signal extension state machine (1) is connected with the data selection output unit (4), and the enable output end of the data/enable signal extension state machine (1) is connected with the enable level synchronizer (2); the enabling level synchronizer (2) is connected with the enabling judgment unit (3); the enabling judgment unit (3) is connected with the data selection output unit (4) and the enabling beat unit (5); the data/enable signal extension state machine (1) receives a first clock input signal tx _ clk; the enabling level synchronizer (2), the enabling judgment unit (3), the data selection output unit (4) and the enabling beat unit (5) receive a second clock input signal rx _ clk; the data/enable signal extension state machine (1) requires to simultaneously input an enable signal tx _ en _ P _ x for one transmission clock cycle (T1) and a data signal tx _ data _ P _ x for one transmission clock cycle (T1); the enable output end of the enable level synchronizer (2) is connected to an enable output port of the whole clock domain crossing multi-bit data selector synchronization circuit suitable for the triple modular redundancy circuit; the data output end of the data selection output unit (4) is connected to the data output port of the whole clock domain crossing multi-bit data selector synchronous circuit suitable for the triple modular redundancy circuit; the enabling decision unit (3) is connected with output ports en _ rxclk _ y, en _ rxclk _ z of the other two data selection synchronization units, namely an enabling signal en _ rxclk _2 of the second redundancy module and an enabling signal en _ rxclk _3 of the third redundancy module respectively; the data selection output unit (4) is connected with the redundant data output ports rx _ data _ y and rx _ data _ z of the other two data selection synchronization units, namely the data signal rx _ data _2 of the second redundant module and the data signal rx _ data _3 of the third redundant module respectively.
2. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the first clock input signal tx _ clk and the second clock input signal rx _ clk are asynchronous clock signals of two different sources.
3. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the enabling level synchronizer (2) consists of two registers C and D which are directly connected and is used for relieving the probability of metastable state occurrence.
4. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the enabling decision unit (3) consists of a majority voter and a rising edge pulse generator circuit.
5. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the data selection output unit (4) comprises a 2-to-1 data selector mux, a bit-based majority Voter Voter2 and a data output register E.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010493325.3A CN111650992B (en) | 2020-06-03 | 2020-06-03 | Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010493325.3A CN111650992B (en) | 2020-06-03 | 2020-06-03 | Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111650992A CN111650992A (en) | 2020-09-11 |
| CN111650992B true CN111650992B (en) | 2023-03-14 |
Family
ID=72351143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010493325.3A Active CN111650992B (en) | 2020-06-03 | 2020-06-03 | Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111650992B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113225065B (en) * | 2021-04-29 | 2022-11-04 | 北京时代民芯科技有限公司 | Configurable sampling circuit implementation device |
| CN114115005B (en) * | 2021-11-12 | 2024-05-03 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Flight control task synchronization system and method based on three-CPU redundancy architecture |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203870506U (en) * | 2014-04-08 | 2014-10-08 | 北京航天自动控制研究所 | Low frequency clock signal synchronous circuit for multiple redundant computer systems |
| CN104426535A (en) * | 2013-09-09 | 2015-03-18 | 株式会社巨晶片 | Synchronization system and frequency divider circuit |
| CN104881544A (en) * | 2015-05-29 | 2015-09-02 | 西北工业大学 | Multi-data triple modular redundancy judgment module based on FPGA (Field Programmable Gate Array) |
| CN109669823A (en) * | 2018-12-03 | 2019-04-23 | 中国工程物理研究院电子工程研究所 | Anti- Multiple-bit upsets error chip reinforcement means based on modified triple-modular redundancy system |
-
2020
- 2020-06-03 CN CN202010493325.3A patent/CN111650992B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104426535A (en) * | 2013-09-09 | 2015-03-18 | 株式会社巨晶片 | Synchronization system and frequency divider circuit |
| CN203870506U (en) * | 2014-04-08 | 2014-10-08 | 北京航天自动控制研究所 | Low frequency clock signal synchronous circuit for multiple redundant computer systems |
| CN104881544A (en) * | 2015-05-29 | 2015-09-02 | 西北工业大学 | Multi-data triple modular redundancy judgment module based on FPGA (Field Programmable Gate Array) |
| CN109669823A (en) * | 2018-12-03 | 2019-04-23 | 中国工程物理研究院电子工程研究所 | Anti- Multiple-bit upsets error chip reinforcement means based on modified triple-modular redundancy system |
Non-Patent Citations (4)
| Title |
|---|
| Reliability and Cost based Redundancy Design for Modular Multilevel Converter;Pengfei Tu 等;《IEEE》;全文 * |
| The Use of Triple-Modular Redundancy to Improve Computer Reliability;R. E. Lyons 等;《IEEE》;全文 * |
| 基于 SRAM 型 FPGA 的实时容错自修复系统设计方法;徐伟杰 等;《微电子技术》;第45卷(第7期);全文 * |
| 基于FPGA动态可重构计算机的三模冗余改进法;谢燕 等;《宜宾学院学报》;第19卷(第12期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111650992A (en) | 2020-09-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111650992B (en) | Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit | |
| US7843216B2 (en) | Techniques for optimizing design of a hard intellectual property block for data transmission | |
| KR100252063B1 (en) | Glitch-free clock enable circuit | |
| EP1624635B1 (en) | Device and method for synchronous parallel data transmission using reference signal | |
| US8363773B2 (en) | Digital phase interpolation control for clock and data recovery circuit | |
| US5555213A (en) | Interface circuit, system and method for interfacing an electronic device and a synchronous state machine having different clock speeds | |
| US7783911B2 (en) | Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements | |
| EP0506136A3 (en) | Broadcast/switching apparatus for executing broadcast/multi-cast transfers over unbuffered asynchronous switching networks | |
| US7340021B1 (en) | Dynamic phase alignment and clock recovery circuitry | |
| WO2001050673A3 (en) | Multiple arbiter jitter estimation system | |
| US7795921B2 (en) | Semiconductor integrated circuit and method of reducing noise | |
| US6970115B1 (en) | Cycle slip framing system and method for selectively increasing a frame clock cycle to maintain related bits within the same parallel-output frame of a deserializer | |
| JPH086913A (en) | Network of computer processor and data half-synchronous transmission method | |
| US8509367B2 (en) | Receiver interface | |
| US5920213A (en) | Pulse discriminating clock synchronizer for logic derived clock signals for a programmable device | |
| US7213090B2 (en) | Data transfer apparatus for serial data transfer in system LSI | |
| US5929676A (en) | Asynchronous pulse discriminating synchronizing clock pulse generator for logic derived clock signals for a programmable device | |
| US5282210A (en) | Time-division-multiplexed data transmission system | |
| CN114637369A (en) | Data delay compensator circuit | |
| CN114519031A (en) | Programmable interconnection channel structure capable of keeping duty ratio and FPGA chip | |
| JP3868776B2 (en) | Bidirectional data transmission / reception method and system | |
| CN109558111A (en) | True random number generating device based on d type flip flop meta-stable behavior | |
| US5923194A (en) | Fast clock generator and clock synchronizer for logic derived clock signals for a programmable device | |
| US4809302A (en) | Clock injector circuit | |
| WO2023074931A1 (en) | Mipi c-phy toggle generation circuit, and mipi c-phy clock recovery circuit including same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |