CN111650992B - Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit - Google Patents

Multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy circuit Download PDF

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CN111650992B
CN111650992B CN202010493325.3A CN202010493325A CN111650992B CN 111650992 B CN111650992 B CN 111650992B CN 202010493325 A CN202010493325 A CN 202010493325A CN 111650992 B CN111650992 B CN 111650992B
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enable
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CN111650992A (en
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范毓洋
王鹏
马振洋
金志威
邓智
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Civil Aviation University of China
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Abstract

A multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy. The system comprises a data/enable signal extension state machine, an enable level synchronizer, an enable judgment unit, a data selection output unit and an enable beat unit; wherein: the data output end of the data/enable signal extension state machine is connected with the data selection output unit, and the enable output end of the data/enable signal extension state machine is connected with the enable level synchronizer; the enabling level synchronizer is connected with the enabling judgment unit; the enabling judgment unit is connected with the data selection output unit and the enabling beating connection. The invention solves the problem that the voter can not output correct data due to a certain path of upset of a clock domain crossing synchronous circuit in the triple modular redundancy design, so that the triple modular redundancy circuit loses the single event upset resistance, and can still normally work under the condition that metastable state and a certain redundant circuit single event upset occur simultaneously when being applied to the triple modular redundancy circuit.

Description

一种适用于三模冗余电路的多比特数据跨时钟域同步电路A multi-bit data synchronization circuit across clock domains suitable for triple-mode redundant circuits

技术领域technical field

本发明属于电子设备技术领域,适用于数字逻辑电路设计,特别是涉及一种适用于三模冗余电路的多比特数据跨时钟域同步电路。The invention belongs to the technical field of electronic equipment, is applicable to the design of digital logic circuits, and in particular relates to a multi-bit data cross-clock domain synchronous circuit applicable to triple-mode redundant circuits.

背景技术Background technique

随着电子硬件设计规模的增大和片上系统(SOC,System On Chip)的出现,现场可编程门阵列(FPGA,Field Programmable Gate Array)和专用集成电路(ASIC,ApplicationSpecific Integrated Circuit)设计中跨时钟域信号电路也相应增多,从而致使电路中由跨时钟域引起的亚稳态的概率也增大,因此需要使用跨时钟域同步器使亚稳态传递概率达到很低水平。但是如果将目前的跨时钟域同步器直接应用于三模冗余电路,由于实际布局布线情况很难使三个冗余电路对应连线的延迟完全一致,不能保证传输到目的时钟域的三个值完全同步变化,导致某一路出现翻转时,表决器不能有效判决输出正确的值,使三模冗余电路失去了抗单粒子翻转能力。With the increase of electronic hardware design scale and the appearance of System On Chip (SOC, System On Chip), cross-clock domain The number of signal circuits also increases accordingly, which increases the probability of metastable states caused by crossing clock domains in the circuits. Therefore, it is necessary to use cross clock domain synchronizers to make the transfer probability of metastable states reach a very low level. However, if the current cross-clock domain synchronizer is directly applied to the triple-mode redundant circuit, due to the actual layout and wiring, it is difficult to make the delays of the corresponding connections of the three redundant circuits exactly the same, and it cannot guarantee that the three redundant circuits transmitted to the destination clock domain The value changes completely synchronously, so that when a certain channel is flipped, the voting device cannot effectively judge and output the correct value, so that the three-mode redundant circuit loses the ability to resist single event flipping.

三模冗余电路是将同一功能模块的电路复制三次,然后在输出端使用投票电路进行多数选择判决,其结构如图2所示。The three-mode redundant circuit is to duplicate the circuit of the same functional module three times, and then use the voting circuit at the output end to make a majority selection decision. Its structure is shown in Figure 2.

图2所示的第一冗余模块、第二冗余模块、第三冗余模块完成相同的逻辑功能。各冗余模块的输出共同连接到投票电路。投票电路也可以进行三冗余,图2的三模冗余电路对投票电路也进行三模冗余,即有投票1,投票2,投票3。投票电路实现多数表决器功能,如图3所示,F=AB+AC+BC(其中F为输出,A、B、C为输入);如果投票电路输出结果是多比特位数据,数据位的每一比特(第n比特)都实现F[n]=A[n]B[n]+A[n]C[n]+B[n]C[n]的功能。The first redundant module, the second redundant module, and the third redundant module shown in FIG. 2 perform the same logical function. The output of each redundancy module is commonly connected to the voting circuit. The voting circuit can also be triple-redundant. The triple-redundant circuit in FIG. Voting circuit realizes majority voter function, as shown in Figure 3, F=AB+AC+BC (wherein F is output, and A, B, C are input); If voting circuit output result is multi-bit data, the number of data bits Each bit (bit n) realizes the function of F[n]=A[n]B[n]+A[n]C[n]+B[n]C[n].

使用图2所示的三模冗余电路时,将相同的输入q1,q2,q3分别输入第一冗余模块、第二冗余模块和第三冗余模块的数据输入端,并保证三个冗余模块的初始状态一致。若冗余设计为同步时钟域设计(不含跨时钟路径),在各冗余模块正常工作的情况下,会同时获得相同的输出A、B、C。若发生某一输出A、B或C出错的情况,如发生单粒子反转,经过投票电路后输出F_V1、F_V2、F_V3仍为正确的值。When using the three-mode redundant circuit shown in Figure 2, input the same input q1, q2, q3 into the data input terminals of the first redundant module, the second redundant module and the third redundant module respectively, and ensure that the three The initial status of the redundant modules is consistent. If the redundant design is a synchronous clock domain design (excluding cross-clock paths), the same outputs A, B, and C will be obtained at the same time when each redundant module is working normally. If a certain output A, B or C is wrong, such as a single event reversal, the output F_V1, F_V2, F_V3 is still the correct value after passing the voting circuit.

如果图2中的冗余模块内含有跨时钟域传输路径,即冗余模块含跨时钟域同步器(即数据从一个时钟域传递到另一个时钟域所需的电路,包括但不限于电平同步器、上升沿同步器、异步FIFO、数据选择同步电路等),则该冗余电路可能会失去抗干扰能力。如图4所示,理想情况下,如果将输入q1_Txclk、q2_Txclk和q3_Txclk同时输入到各跨时钟域同步器中(输入q1_Txclk、q2_Txclk、q3_Txclk按照发送时钟域时钟同时变换),我们期望三个冗余模块的同步器输出Rx_sig_C1、Rx_sig_C2、Rx_sig_C3的值在接收时钟域同时变化。但由于信号经过了跨时钟域传输,因此很难保证同步器之间的连线、时钟路径、工作环境(如电路供电电压和电磁干扰)、同步电路内部的寄存器特性参数等完全一致,会导致三个冗余模块的同步器输出Rx_sig_C1、Rx_sig_C2、Rx_sig_C3不能在接收时钟域同步变化。如发生图5上部所示的场景2和场景3的情况。由于跨时钟域路径出现亚稳态状况,场景2中冗余模块1的同步器输出Rx_sig_C1比理想情况提前一个接收时钟周期;在场景3中冗余模块3的同步器输出Rx_sig_C3推迟一个接收时钟周期(三个冗余模块的同步器输出Rx_sig_C1、Rx_sig_C2、Rx_sig_C3有效脉冲宽度(高电平)为接收时钟的一个时钟周期),这就会降低该三模冗余电路抗单粒子的能力。如图5下部所示,第一冗余模块发生单粒子翻转,致使冗余模块1的同步器输出Rx_sig_C1固定在0值,则在场景3下三模冗余方法不能将第一冗余模块的单粒子翻转的错误屏蔽,导致投票电路输出Rx_sig_voter输出为0。If the redundant module in Figure 2 contains a cross-clock domain transmission path, that is, the redundant module contains a cross-clock domain synchronizer (that is, the circuit required for data transfer from one clock domain to another clock domain, including but not limited to the level synchronizer, rising edge synchronizer, asynchronous FIFO, data selection synchronous circuit, etc.), the redundant circuit may lose anti-interference ability. As shown in Figure 4, ideally, if the inputs q1_Txclk, q2_Txclk, and q3_Txclk are input to each cross-clock domain synchronizer at the same time (the inputs q1_Txclk, q2_Txclk, and q3_Txclk are simultaneously converted according to the transmit clock domain clock), we expect three redundant The values of Rx_sig_C1, Rx_sig_C2 and Rx_sig_C3 output by the synchronizer of the module change simultaneously in the receiving clock domain. However, since the signals are transmitted across clock domains, it is difficult to ensure that the connections between synchronizers, clock paths, working environments (such as circuit power supply voltage and electromagnetic interference), and the characteristic parameters of the registers inside the synchronization circuit are completely consistent, which will lead to The synchronizer outputs Rx_sig_C1, Rx_sig_C2, and Rx_sig_C3 of the three redundant modules cannot change synchronously in the receive clock domain. Such as the situation of scene 2 and scene 3 shown in the upper part of Fig. 5 . Due to the metastable state of the cross-clock domain path, the synchronizer output Rx_sig_C1 of redundancy module 1 in scenario 2 is earlier than the ideal situation by one receive clock cycle; in scenario 3, the synchronizer output Rx_sig_C3 of redundancy module 3 is delayed by one receive clock cycle (The effective pulse width (high level) of the synchronizer outputs Rx_sig_C1, Rx_sig_C2 and Rx_sig_C3 of the three redundant modules is one clock cycle of the receiving clock), which will reduce the anti-single event capability of the triple-mode redundant circuit. As shown in the lower part of Figure 5, a single-event flip occurs in the first redundant module, causing the synchronizer output Rx_sig_C1 of redundant module 1 to be fixed at 0. In scenario 3, the three-mode redundancy method cannot False masking of single-event upsets, causing the voting circuit output Rx_sig_voter to output 0.

发明内容Contents of the invention

为了解决上述问题,本发明的目的在于提供一种适用于三模冗余电路的多比特数据跨时钟域同步电路。In order to solve the above problems, the object of the present invention is to provide a multi-bit data cross-clock domain synchronization circuit suitable for triple-mode redundant circuits.

为了达到上述目的,本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路包括:In order to achieve the above object, the multi-bit data cross-clock domain synchronization circuit suitable for triple-mode redundant circuits provided by the present invention includes:

数据/使能信号延长状态机、使能电平同步器、使能判决单元、数据选择输出单元和使能打拍;其中:数据/使能信号延长状态机的数据输出端与数据选择输出单元连接,数据/使能信号延长状态机的使能输出端与使能电平同步器相连接;使能电平同步器与使能判决单元连接;使能判决单元与数据选择输出单元连接及使能打拍连接;数据/使能信号延长状态机接收第一时钟输入信号tx_clk;使能电平同步器、使能判决单元、数据选择输出单元和使能打拍接收第二时钟输入信号rx_clk;数据/使能信号延长状态机要求同时输入一个发送时钟周期的使能信号tx_en_P_x和一个发送时钟周期的数据信号tx_data_P_x;使能电平同步器的使能输出端连接到适用于三模冗余电路的跨时钟域多比特数据选择器同步电路整体的使能输出端口;数据选择输出单元的数据输出端连接到适用于三模冗余电路的跨时钟域多比特数据选择器同步电路整体的数据输出端口;使能判决单元与其余两个数据选择同步单元的输出端口en_rxclk_y,en_rxclk_z,即分别为第二冗余模块的使能信号en_rxclk_2和第三冗余模块的使能信号en_rxclk_3相连接;数据选择输出单元与其余两个数据选择同步单元的冗余数据输出端口rx_data_y、rx_data_z,即分别为第二冗余模块的数据信号rx_data_2和第三冗余模块的数据信号rx_data_3相连接。Data/enable signal extension state machine, enable level synchronizer, enable decision unit, data selection output unit and enable beat; wherein: the data output end of the data/enable signal extension state machine and the data selection output unit Connection, the enable output of the data/enable signal extension state machine is connected with the enable level synchronizer; the enable level synchronizer is connected with the enable judgment unit; the enable judgment unit is connected with the data selection output unit and used Can beat connection; data/enable signal extension state machine receives first clock input signal tx_clk; enables level synchronizer, enables decision unit, data selection output unit and enables beat to receive second clock input signal rx_clk; The data/enable signal extension state machine requires the input of an enable signal tx_en_P_x of a transmit clock cycle and a data signal tx_data_P_x of a transmit clock cycle at the same time; the enable output of the enable level synchronizer is connected to a triple-mode redundant circuit The enable output port of the overall multi-bit data selector synchronization circuit across the clock domain; the data output end of the data selection output unit is connected to the overall data output of the multi-bit data selector synchronization circuit across the clock domain applicable to the triple-mode redundant circuit Port; enable the judgment unit to be connected with the output ports en_rxclk_y and en_rxclk_z of the remaining two data selection synchronization units, which are respectively the enable signal en_rxclk_2 of the second redundancy module and the enable signal en_rxclk_3 of the third redundancy module; data selection The output unit is connected to the redundant data output ports rx_data_y and rx_data_z of the other two data selection synchronization units, namely the data signal rx_data_2 of the second redundancy module and the data signal rx_data_3 of the third redundancy module respectively.

所述的第一时钟输入信号tx_clk与第二时钟输入信号rx_clk为两个不同源的异步时钟信号。The first clock input signal tx_clk and the second clock input signal rx_clk are asynchronous clock signals from two different sources.

所述的使能电平同步器由两个直接相连的寄存器C、寄存器D组成,用于缓解亚稳态发生的概率。The enable level synchronizer is composed of two directly connected registers C and D, which are used to alleviate the probability of metastability.

所述的使能判决单元由多数表决器和上升沿脉冲生成器电路组成。The enabling decision unit is composed of a majority voter and a rising edge pulse generator circuit.

所述的数据选择输出单元包括2选1数据选择器mux、按位多数表决器Voter2和数据输出寄存器E。The data selection output unit includes a 2-to-1 data selector mux, a bit majority voter Voter2 and a data output register E.

本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路解决了三模冗余设计中跨时钟域同步电路由于某一路翻转导致表决器不能输出正确数据,使三模冗余电路失去了抗单粒子翻转能力的问题,可以在应用于三模冗余电路中时,在亚稳态和某一冗余电路单粒子翻转同时发生的情况下仍然能正常工作。The multi-bit data cross-clock domain synchronization circuit suitable for triple-mode redundant circuits provided by the present invention solves the problem that the cross-clock domain synchronization circuits in the triple-mode redundant design cannot output correct data due to the inversion of a certain path, making the triple-mode redundant The problem that the circuit loses the anti-single event flipping ability can still work normally when the metastable state and the single event flipping of a redundant circuit occur simultaneously when it is applied to a three-mode redundant circuit.

附图说明Description of drawings

图1为本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路的结构示意图。FIG. 1 is a schematic structural diagram of a multi-bit data cross-clock domain synchronization circuit suitable for a triple-mode redundant circuit provided by the present invention.

图2为已有技术的三模冗余电路构成框图。FIG. 2 is a block diagram of a triple-mode redundant circuit in the prior art.

图3为已有技术的投票电路实现原理图。FIG. 3 is a schematic diagram of a voting circuit in the prior art.

图4为已有技术的含跨时钟域设计的三模电路实现框图。FIG. 4 is a block diagram of a prior art three-mode circuit including cross-clock domain design.

图5为已有技术的跨时钟域电路三模应用时序图。FIG. 5 is a timing diagram of a three-mode application of a cross-clock domain circuit in the prior art.

图6为本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路中三个冗余数据选择同步单元电路端口框图。FIG. 6 is a block diagram of three redundant data selection synchronization unit circuit ports in a multi-bit data cross-clock domain synchronization circuit suitable for a triple-mode redundant circuit provided by the present invention.

图7为本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路中数据/使能信号延长状态机的状态转移图。FIG. 7 is a state transition diagram of a data/enable signal extension state machine in a multi-bit data cross-clock domain synchronization circuit suitable for a triple-mode redundant circuit provided by the present invention.

图8为本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路中上升沿脉冲生成器电路实现图。FIG. 8 is an implementation diagram of a rising-edge pulse generator circuit in a multi-bit data cross-clock domain synchronization circuit suitable for a triple-mode redundant circuit provided by the present invention.

图9为本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路中三模冗余跨时钟域同步电路抗单粒子翻转原理时序图。FIG. 9 is a timing diagram of anti-single event upset principle of the triple-mode redundant cross-clock domain synchronization circuit in the multi-bit data cross-clock domain synchronization circuit applicable to the triple-mode redundancy circuit provided by the present invention.

具体实施方式Detailed ways

下面结合附图和具体实施例对本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路(此处指数据选择同步单元,命名为Dmux_t)的结构和使用方法进行详细说明。The structure and method of use of the multi-bit data cross-clock domain synchronization circuit (here referred to as the data selection synchronization unit, named Dmux_t) suitable for triple-mode redundant circuits provided by the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

首先介绍数据选择同步单元Dmux_t进行三模冗余电路实现时的端口及其链接方式。本发明使用三个数据选择同步单元Dmux_t互相连接构成三模冗余电路Dmux_R。三模冗余电路Dmux_R一般对图1所示的数据选择同步单元Dmux_t实例化三次构成,其中第一数据选择同步单元Dmux_t1作为第一冗余模块,第二数据选择同步单元Dmux_t2作为第二冗余模块,第三数据选择同步单元Dmux_t3作为第三冗余模块。它们实现相同的逻辑功能。Firstly, it introduces the port and its connection mode when the data selection synchronization unit Dmux_t realizes the triple-mode redundant circuit. In the present invention, three data selection synchronization units Dmux_t are connected to each other to form a triple-mode redundant circuit Dmux_R. The three-mode redundant circuit Dmux_R generally instantiates the data selection synchronization unit Dmux_t shown in Figure 1 three times, wherein the first data selection synchronization unit Dmux_t1 is used as the first redundancy module, and the second data selection synchronization unit Dmux_t2 is used as the second redundancy module. module, the third data selects the synchronization unit Dmux_t3 as the third redundant module. They implement the same logical function.

下面结合图6对冗余模块Dmux_R的端口进行说明:The ports of the redundancy module Dmux_R are described below in conjunction with Figure 6:

Figure BDA0002521931080000051
Figure BDA0002521931080000051

Figure BDA0002521931080000061
Figure BDA0002521931080000061

下面对第一冗余模块Dmux_t1的端口进行说明:The ports of the first redundancy module Dmux_t1 are described below:

Figure BDA0002521931080000062
Figure BDA0002521931080000062

Figure BDA0002521931080000071
Figure BDA0002521931080000071

下面对第二冗余模块Dmux_t2的端口进行说明:The ports of the second redundancy module Dmux_t2 are described below:

Figure BDA0002521931080000072
Figure BDA0002521931080000072

Figure BDA0002521931080000081
Figure BDA0002521931080000081

下面对第三冗余模块Dmux_t3的端口进行说明:The ports of the third redundancy module Dmux_t3 are described below:

Figure BDA0002521931080000082
Figure BDA0002521931080000082

Figure BDA0002521931080000091
Figure BDA0002521931080000091

第一数据选择同步单元、第二数据选择同步单元和第三数据选择同步单元端口链接关系遵从相同命名的链接到一起的规则。三个数据选择同步单元按上述端口描述和链接规则组织到一起,共同构成三模冗余电路。三个使能信号tx_en_P_1、tx_en_P_2、tx_en_P_3同时变化,三个数据信号tx_data_P_1、tx_data_P_2、tx_data_P_3的值也同时变化,且值相等。The port link relationship of the first data selection synchronization unit, the second data selection synchronization unit and the third data selection synchronization unit follows the same-named link-together rule. The three data selection synchronous units are organized together according to the above-mentioned port description and linking rules, and together constitute a triple-mode redundant circuit. The three enable signals tx_en_P_1, tx_en_P_2, and tx_en_P_3 change at the same time, and the values of the three data signals tx_data_P_1, tx_data_P_2, and tx_data_P_3 also change at the same time, and the values are equal.

下面具体对本发明提供的适用于三模冗余电路的多比特数据跨时钟域同步电路(数据选择同步单元Dmux_t)内部电路的结构组成进行说明。由于三个数据选择同步单元的电路结构和功能完全一致,下面以第一数据选择同步单元为例进行电路结构及功能说明。此时,图示1中的x代表1,y代表2,z代表3。(若图示1代表第二数据选择同步单元,则x代表2,y代表1,z代表3。若图示1代表第三数据选择同步单元,则x代表3,y代表1,z代表2)The structure and composition of the internal circuit of the multi-bit data cross-clock domain synchronization circuit (data selection synchronization unit Dmux_t) suitable for triple-mode redundant circuits provided by the present invention will be specifically described below. Since the circuit structures and functions of the three data selection synchronization units are completely consistent, the circuit structure and functions will be described below taking the first data selection synchronization unit as an example. At this time, x in Figure 1 represents 1, y represents 2, and z represents 3. (If the figure 1 represents the second data selection synchronization unit, then x represents 2, y represents 1, and z represents 3. If the figure 1 represents the third data selection synchronization unit, then x represents 3, y represents 1, and z represents 2 )

如图1所示,本发明提供的适用于三模冗余的多比特数据跨时钟域同步电路包括:As shown in Figure 1, the multi-bit data cross-clock domain synchronization circuit suitable for triple-mode redundancy provided by the present invention includes:

数据/使能信号延长状态机1、使能电平同步器2、使能判决单元3、数据选择输出单元4和使能打拍5;其中:数据/使能信号延长状态机1的数据输出端与数据选择输出单元4连接,数据/使能信号延长状态机1的使能输出端与使能电平同步器2相连接;使能电平同步器2与使能判决单元3连接;使能判决单元3与数据选择输出单元4连接及使能打拍5连接;数据/使能信号延长状态机1接收第一时钟输入信号tx_clk;使能电平同步器2、使能判决单元3、数据选择输出单元4和使能打拍5接收第二时钟输入信号rx_clk;数据/使能信号延长状态机1要求同时输入一个发送时钟周期T1的使能信号tx_en_P_x(此处该使能信号为tx_en_P_1)和一个发送时钟周期T1的数据信号tx_data_P_x(此时该端口链接使能信号tx_data_P_1);使能电平同步器2的使能输出端连接到适用于三模冗余电路的跨时钟域多比特数据选择器同步电路整体的使能输出端口;数据选择输出单元4的数据输出端连接到适用于三模冗余电路的跨时钟域多比特数据选择器同步电路整体的数据输出端口;使能判决单元3与其余两个数据选择同步单元的输出端口en_rxclk_y,en_rxclk_z(分别指第二冗余模块的使能信号en_rxclk_2和第三冗余模块的使能信号en_rxclk_3)相连接;数据选择输出单元4与其余两个数据选择同步单元的冗余数据输出端口rx_data_y、rx_data_z(rx_data_y指第二冗余模块的数据信号rx_data_2,rx_data_z指第三冗余模块的数据信号rx_data_3)相连接。Data/enable signal extension state machine 1, enable level synchronizer 2, enable decision unit 3, data selection output unit 4 and enable beat 5; wherein: data output of data/enable signal extension state machine 1 Terminal is connected with data selection output unit 4, and the enable output end of data/enabling signal extension state machine 1 is connected with enable level synchronizer 2; Enable level synchronizer 2 is connected with enabling judgment unit 3; The judgment unit 3 is connected with the data selection output unit 4 and the beat 5 is connected; the data/enable signal extension state machine 1 receives the first clock input signal tx_clk; the level synchronizer 2 is enabled, the judgment unit 3, Data selection output unit 4 and enable beat 5 to receive the second clock input signal rx_clk; data/enable signal extension state machine 1 requires to input simultaneously the enable signal tx_en_P_x of a transmission clock cycle T1 (this enable signal is tx_en_P_1 here ) and a data signal tx_data_P_x that sends a clock cycle T1 (at this time, the port is linked with the enable signal tx_data_P_1); the enable output of the enable level synchronizer 2 is connected to the cross-clock domain multi-bit applicable to the triple-mode redundant circuit The overall enable output port of the data selector synchronization circuit; the data output end of the data selection output unit 4 is connected to the overall data output port of the cross-clock domain multi-bit data selector synchronization circuit applicable to the triple-mode redundant circuit; the enable judgment Unit 3 is connected to the output ports en_rxclk_y and en_rxclk_z of the remaining two data selection synchronization units (referring to the enable signal en_rxclk_2 of the second redundancy module and the enable signal en_rxclk_3 of the third redundancy module); the data selection output unit 4 is connected to The remaining two data select the redundant data output ports rx_data_y and rx_data_z of the synchronization unit (rx_data_y refers to the data signal rx_data_2 of the second redundancy module, and rx_data_z refers to the data signal rx_data_3 of the third redundancy module) to be connected.

所述的第一时钟输入信号tx_clk与第二时钟输入信号rx_clk为两个不同源的异步时钟信号。The first clock input signal tx_clk and the second clock input signal rx_clk are asynchronous clock signals from two different sources.

在数据/使能信号延长状态机1中,输入为一个发送时钟周期T1的使能信号tx_en_P_1和一个数据信号rx_data_1,输出为

Figure BDA0002521931080000101
Figure BDA0002521931080000102
个发送时钟周期T1长度的延长后的使能信号,
Figure BDA0002521931080000103
Figure BDA0002521931080000104
个发送时钟周期T1长度的延长后的数据信号(
Figure BDA0002521931080000105
表示向下取整操作符);其中,延长后的数据信号被数据寄存器A寄存输出,延长后的使能信号被使能寄存器B寄存输出;相邻数据发送间隔要保持至少
Figure BDA0002521931080000106
个发送时钟周期T1的长度,即两个使能信号tx_en_P_1要保持
Figure BDA0002521931080000107
个发送时钟周期T1的间隔In the data/enable signal extension state machine 1, the input is an enable signal tx_en_P_1 of a transmission clock cycle T1 and a data signal rx_data_1, and the output is
Figure BDA0002521931080000101
Figure BDA0002521931080000102
The extended enable signal of the transmit clock cycle T1 length,
Figure BDA0002521931080000103
Figure BDA0002521931080000104
The extended data signal (
Figure BDA0002521931080000105
Indicates the rounding down operator); wherein, the extended data signal is registered and output by the data register A, and the extended enable signal is registered and output by the enable register B; the interval between adjacent data transmissions should be kept at least
Figure BDA0002521931080000106
The length of a send clock cycle T1, that is, the two enable signals tx_en_P_1 should be kept
Figure BDA0002521931080000107
The interval of sending clock cycle T1

如图7所示,所述的数据/使能信号延长状态机1复位后进入IDLE状态,当使能信号tx_en_P_1为高电平时,进入EN_D状态,同时发送时钟周期T1时钟域的计数器Counter1从0开始计数,计数到

Figure BDA0002521931080000111
Figure BDA0002521931080000112
状态机跳转到DATA_D状态,在DATA_D状态下计数器Counter2从零开始计数,计数到
Figure BDA0002521931080000113
时,状态机从DATA_D跳转到IDLE状态。As shown in Figure 7, the data/enable signal extension state machine 1 enters the IDLE state after being reset, and enters the EN_D state when the enable signal tx_en_P_1 is at a high level, and at the same time, the counter Counter1 in the clock domain of the sending clock cycle T1 changes from 0 to start counting, count up to
Figure BDA0002521931080000111
Figure BDA0002521931080000112
The state machine jumps to the DATA_D state. In the DATA_D state, the counter Counter2 starts counting from zero and counts to
Figure BDA0002521931080000113
, the state machine jumps from DATA_D to IDLE state.

状态IDLE输出:Status IDLE output:

数据/使能信号延长状态机1的使能输出tx_en_1=0;数据/使能信号延长状态机1的数据输出tx_data_1:保持原值不变。The enable output tx_en_1 of the data/enable signal extension state machine 1=0; the data output tx_data_1 of the data/enable signal extension state machine 1: keep the original value unchanged.

状态EN_D输出:Status EN_D output:

数据/使能信号延长状态机1的使能输出tx_en_1=1,数据/使能信号延长状态机1的数据输出tx_data_1=tx_data_P_1The data/enable signal extends the enable output tx_en_1 of state machine 1=1, and the data/enable signal extends the data output of state machine 1 tx_data_1=tx_data_P_1

(tx_en_P_1高电平时的tx_data_P_1r的值)。(The value of tx_data_P_1r when tx_en_P_1 is high).

状态DATA_D输出:Status DATA_D output:

数据/使能信号延长状态机1的使能输出tx_en_1=0,数据/使能信号延长状态机1的数据输出tx_data_1:保持不变。The enable output tx_en_1 of the data/enable signal extension state machine 1=0, the data output tx_data_1 of the data/enable signal extension state machine 1: remain unchanged.

所述的使能电平同步器2由两个直接相连的寄存器C、寄存器D组成,用于缓解亚稳态发生的概率。The enable level synchronizer 2 is composed of two directly connected registers C and D, which are used to alleviate the probability of metastability.

所述的使能判决单元3由多数表决器和上升沿脉冲生成器电路组成;用于判决使能电平同步器2输出的使能信号和其他两个冗余模块的输出en_rxclk_y,en_rxclk_z(分别指第二冗余模块的输出en_rxclk_2和第三冗余模块的输出en_rxclk_3)。判决机理为多数表决器;多数表决器实现F=A*B+A*C+B*C的功能(其中F为输出,A、B、C为输入),电路图如图3所示;多数表决器的输出输入到用于生成一个接收时钟周期T2的上升沿脉冲生成器,上升沿脉冲生成器的电路图如图8所示,即使能脉冲信号en_rxclk_P=en_rxclk_v&(!en_rxclk_v_d)。使能投票延迟信号en_rxclk_v_d为使能投票信号en_rxclk_v延迟一接收时钟周期T2。Described enabling judgment unit 3 is made up of majority voter and rising edge pulse generator circuit; It is used to judge the enabling signal of enabling level synchronizer 2 output and the output en_rxclk_y of other two redundant modules, en_rxclk_z (respectively Refers to the output en_rxclk_2 of the second redundancy module and the output en_rxclk_3 of the third redundancy module). The judgment mechanism is the majority voter; the majority voter realizes the function of F=A*B+A*C+B*C (wherein F is the output, A, B, and C are the inputs), and the circuit diagram is shown in Figure 3; the majority vote The output of the device is input to a rising edge pulse generator used to generate a receive clock cycle T2. The circuit diagram of the rising edge pulse generator is shown in Figure 8, that is, the pulse signal en_rxclk_P=en_rxclk_v&(!en_rxclk_v_d). The enable voting delay signal en_rxclk_v_d is delayed by one receive clock period T2 for the enabling voting signal en_rxclk_v.

数据选择输出单元4包括2选1数据选择器mux、按位多数表决器Voter2(即数据的每一比特位都按多数表决器选择相应的值)和数据输出寄存器E;2选1数据选择器mux选择信号为使能判决单元3的输出使能脉冲信号en_rxclk_P,2选1数据选择器mux的数据输入端一端为数据/使能信号延长状态机1的数据输出端tx_data_1,另一个数据输入端为按位多数表决器Voter2的输出端rx_data_v。其中,输出使能脉冲信号en_rxclk_P为高电平时,2选1数据选择器mux选择数据/使能信号延长状态机1的数据输出tx_data_1作为输出,输出使能脉冲信号en_rxclk_P为低电平时,2选1数据选择器mux选择按位多数表决器Voter2的输出rx_data_v作为输出。按位多数表决器Voter2输入一端为数据输出寄存器E的输出端,另外两个输入为冗余模块数据输出,rx_data_y、rx_data_z(rx_data_y、rx_data_z分别指rx_data_2,rx_data_3)的数据输出端口;数据位的每一比特都实现如图2所示电路图的功能。Data selection output unit 4 comprises 2 to select 1 data selector mux, bitwise majority voter Voter2 (that is, each bit of data selects corresponding value by majority voter) and data output register E; 2 selects 1 data selector The mux selection signal is the output enable pulse signal en_rxclk_P of the enable decision unit 3, the data input end of the 2-to-1 data selector mux is the data output end tx_data_1 of the data/enable signal extension state machine 1, and the other data input end It is the output terminal rx_data_v of the bit majority voter Voter2. Among them, when the output enable pulse signal en_rxclk_P is at a high level, the 2-to-1 data selector mux selects the data output tx_data_1 of the data/enable signal extension state machine 1 as an output, and when the output enable pulse signal en_rxclk_P is at a low level, the 2-selection 1. The data selector mux selects the output rx_data_v of the bitwise majority voter Voter2 as an output. One end of the input of the bitwise majority voter Voter2 is the output end of the data output register E, and the other two inputs are the data output ports of the redundancy module, rx_data_y, rx_data_z (rx_data_y, rx_data_z refer to rx_data_2, rx_data_3 respectively); Each bit realizes the function of the circuit diagram shown in FIG. 2 .

rx_data[n]=rx_data_x[n]*rx_data_y[n]+rx_data_x[n]*rx_data_z[n]+rx_data_y[n]*rx_data_z[n]。rx_data[n]=rx_data_x[n]*rx_data_y[n]+rx_data_x[n]*rx_data_z[n]+rx_data_y[n]*rx_data_z[n].

使能打拍5将使能判决单元3的输出使能脉冲信号en_rxclk_P延迟两个时钟节拍,目的是使输出使能脉冲信号en_rxclk_P_1为高电平时,输出数据rx_data_1有效。The enable beat 5 delays the output enable pulse signal en_rxclk_P of the enable decision unit 3 by two clock beats, so that the output data rx_data_1 is valid when the output enable pulse signal en_rxclk_P_1 is at high level.

下面解释该电路工作原理:Here's how the circuit works:

所述的数据/使能信号延长状态机1、使能电平同步器2、使能判决单元3、数据选择输出单元4和使能打拍5可采用硬件描述语言在FPGA或ASIC上实现。使用该电路时,数据和使能信号首先通过数据选择同步单元中的数据/使能信号延长状态机1,将一个发送时钟周期T1的使能信号tx_en_P_1和一个发送时钟周期T1的数据信号tx_data_P_1拉长。经过数据/使能信号延长状态机1后,生成

Figure BDA0002521931080000131
Figure BDA0002521931080000132
个发送时钟周期T1长的数据/使能信号延长状态机1的使能输出信号tx_en_1、
Figure BDA0002521931080000133
个接收时钟周期T2长的数据/使能信号延长状态机1的数据输出tx_data_1,并且保证下个数据与当前数据间隔保持数据发送间隔要保持至少
Figure BDA0002521931080000134
个发送时钟周期T1。数据/使能信号延长状态机1的使能输出信号tx_en_1输出到使能电平同步器2,由于该路径进行了跨时钟域传输,所以使用了使能电平同步器2,降低了亚稳态发生的概率。由于使用数据/使能信号延长状态机1对一个发送时钟周期T1的使能信号tx_en_P_1进行了拉长,可使数据/使能信号延长状态机1的使能输出信号tx_en_1发送到接收时钟域时生成使能电平同步器输出en_rxclk_1的有效电平长于两个接收时钟周期T2。使能电平同步器2的输出en_rxclk_1与第二冗余模块的使能电平同步器2的输出en_rxclk_2、第三冗余模块的使能电平同步器2的输出en_rxclk_3输出到使能判决单元3的多数表决器。The data/enable signal extension state machine 1, enable level synchronizer 2, enable decision unit 3, data selection output unit 4 and enable beat 5 can be realized on FPGA or ASIC by using hardware description language. When using this circuit, the data and enable signals first extend the state machine 1 through the data/enable signal in the data selection synchronization unit, and pull the enable signal tx_en_P_1 of one transmission clock cycle T1 and the data signal tx_data_P_1 of one transmission clock cycle T1 long. After the data/enable signal is extended to state machine 1, the generated
Figure BDA0002521931080000131
Figure BDA0002521931080000132
The data/enable signal with a long transmission clock cycle T1 extends the enable output signal tx_en_1 of the state machine 1,
Figure BDA0002521931080000133
The data/enable signal with a long receiving clock cycle T2 extends the data output tx_data_1 of the state machine 1, and ensures that the next data and the current data interval maintain the data transmission interval at least
Figure BDA0002521931080000134
transmit clock cycle T1. The enable output signal tx_en_1 of the data/enable signal extension state machine 1 is output to the enable level synchronizer 2. Since this path is transmitted across the clock domain, the enable level synchronizer 2 is used to reduce the metastability probability of occurrence. Since the enable signal tx_en_P_1 of a transmit clock cycle T1 is elongated by using the data/enable signal extension state machine 1, the enable output signal tx_en_1 of the data/enable signal extension state machine 1 can be sent to the receive clock domain The active level of the generate enable level synchronizer output en_rxclk_1 is longer than two receive clock periods T2. The output en_rxclk_1 of the enable level synchronizer 2 and the output en_rxclk_2 of the enable level synchronizer 2 of the second redundancy module, and the output en_rxclk_3 of the enable level synchronizer 2 of the third redundancy module are output to the enable decision unit 3 majority voters.

en_rxclk_v=en_rxclk_1*en_rxclk_1+en_rxclk_1*en_rxclk_3+en_rxclk_2*en_rxclk_3。en_rxclk_v=en_rxclk_1*en_rxclk_1+en_rxclk_1*en_rxclk_3+en_rxclk_2*en_rxclk_3.

该使能电平同步器2保证了在冗余模块中,某一冗余模块出错,使能判决器仍然能输出正确结果。由于亚稳态致使使能电平同步器2输出en_rxclk_1,en_rxclk_2或en_rxclk_3不能在同一个接收时钟域的同一个接收时钟有效沿同时到来,但由于使能电平同步器2输出en_rxclk_1,en_rxclk_2或en_rxclk_3保持了至少两个时钟周期,所以可以保证在某一个接收时钟的有效时钟采样沿,在某一冗余电路出现翻转错误的情况下,使能判决器仍然可以输出有效的使能信号,如图9右边所示。将输出使能投票信号en_rxclk_v输出到上升沿脉冲生成器电路,即可保证输出使能脉冲信号en_rxclk_P只有一个接收时钟的有效周期,可避免数据在接收时钟域的重复输出。The enable level synchronizer 2 ensures that if a redundant module fails in a redundant module, the enable decision unit can still output a correct result. Due to the metastable state, the enable level synchronizer 2 outputs en_rxclk_1, en_rxclk_2 or en_rxclk_3 cannot arrive at the same receive clock active edge in the same receive clock domain at the same time, but because the enable level synchronizer 2 outputs en_rxclk_1, en_rxclk_2 or en_rxclk_3 At least two clock cycles are maintained, so it can be guaranteed that at the effective clock sampling edge of a certain receiving clock, in the case of a flip error in a redundant circuit, the enable decision device can still output a valid enable signal, as shown in the figure 9 is shown on the right. Outputting the output enable voting signal en_rxclk_v to the rising edge pulse generator circuit can ensure that the output enable pulse signal en_rxclk_P has only one valid period of the receive clock, which can avoid repeated output of data in the receive clock domain.

将输出使能脉冲信号en_rxclk_P信号链接到数据选择输出单元4。当输出使能脉冲信号en_rxclk_P为高电平时,2选1数据选择器mux选择状态机1的数据输出tx_data_1作为输出,当输出使能脉冲信号en_rxclk_P为低电平时,选择判别数据信号rx_data_v作为输出。其中,判别数据信号rx_data_v输出的每一比特位等于rx_data_x、rx_data_y、rx_data_z对应比特位的多数表决结果:rx_data_v[n]=rx_data_x[n]*rx_data_y[n]+rx_data_x[n]*rx_data_z[n]+rx_data_y[n]*rx_data_z[n]。Link the output enable pulse signal en_rxclk_P signal to the data selection output unit 4 . When the output enable pulse signal en_rxclk_P is at a high level, the 2-to-1 data selector mux selects the data output tx_data_1 of the state machine 1 as an output, and when the output enable pulse signal en_rxclk_P is at a low level, selects the discrimination data signal rx_data_v as an output. Among them, each bit output by the discrimination data signal rx_data_v is equal to the majority voting result of the corresponding bit of rx_data_x, rx_data_y, rx_data_z: rx_data_v[n]=rx_data_x[n]*rx_data_y[n]+rx_data_x[n]*rx_data_z[n] +rx_data_y[n]*rx_data_z[n].

这样,如果rx_data_x[n]\rx_data_y[n]\rx_data_z[n]中有一比特位出现翻转,判别数据信号rx_data_v仍然可以输出正确的值。In this way, if one bit in rx_data_x[n]\rx_data_y[n]\rx_data_z[n] is reversed, the judgment data signal rx_data_v can still output the correct value.

为了判别数据信号rx_data_1有效输出时间,对使能脉冲信号en_rxclk_P使用使能打拍5进行延迟,使能脉冲信号en_rxclk_P延迟两个接收时钟周期T2后,使能打拍5输出en_rxck_P_1。使能打拍5输出en_rxck_P_1为高电平时,数据信号rx_data_1有效。In order to judge the effective output time of the data signal rx_data_1, the enable pulse signal en_rxclk_P is delayed by the enable beat 5, and the enable pulse signal en_rxclk_P is delayed by two receive clock cycles T2, and the enable beat 5 outputs en_rxck_P_1. When the beat 5 output en_rxck_P_1 is at high level, the data signal rx_data_1 is valid.

本发明提供的适用于三模冗余的多比特数据跨时钟域同步电路,解决了某一路跨时钟域同步电路出现单粒子翻转时,三模冗余电路可能输出错误数据或丢失数据的问题。The multi-bit data cross-clock domain synchronization circuit suitable for triple-mode redundancy provided by the invention solves the problem that the triple-mode redundancy circuit may output wrong data or lose data when a single-event reversal occurs in a certain cross-clock domain synchronization circuit.

Claims (5)

1. A multi-bit data clock domain crossing synchronization circuit suitable for triple modular redundancy, comprising: the multi-bit data cross clock domain synchronization circuit suitable for triple modular redundancy comprises:
the device comprises a data/enable signal extension state machine (1), an enable level synchronizer (2), an enable judgment unit (3), a data selection output unit (4) and an enable beat unit (5); wherein: the data output end of the data/enable signal extension state machine (1) is connected with the data selection output unit (4), and the enable output end of the data/enable signal extension state machine (1) is connected with the enable level synchronizer (2); the enabling level synchronizer (2) is connected with the enabling judgment unit (3); the enabling judgment unit (3) is connected with the data selection output unit (4) and the enabling beat unit (5); the data/enable signal extension state machine (1) receives a first clock input signal tx _ clk; the enabling level synchronizer (2), the enabling judgment unit (3), the data selection output unit (4) and the enabling beat unit (5) receive a second clock input signal rx _ clk; the data/enable signal extension state machine (1) requires to simultaneously input an enable signal tx _ en _ P _ x for one transmission clock cycle (T1) and a data signal tx _ data _ P _ x for one transmission clock cycle (T1); the enable output end of the enable level synchronizer (2) is connected to an enable output port of the whole clock domain crossing multi-bit data selector synchronization circuit suitable for the triple modular redundancy circuit; the data output end of the data selection output unit (4) is connected to the data output port of the whole clock domain crossing multi-bit data selector synchronous circuit suitable for the triple modular redundancy circuit; the enabling decision unit (3) is connected with output ports en _ rxclk _ y, en _ rxclk _ z of the other two data selection synchronization units, namely an enabling signal en _ rxclk _2 of the second redundancy module and an enabling signal en _ rxclk _3 of the third redundancy module respectively; the data selection output unit (4) is connected with the redundant data output ports rx _ data _ y and rx _ data _ z of the other two data selection synchronization units, namely the data signal rx _ data _2 of the second redundant module and the data signal rx _ data _3 of the third redundant module respectively.
2. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the first clock input signal tx _ clk and the second clock input signal rx _ clk are asynchronous clock signals of two different sources.
3. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the enabling level synchronizer (2) consists of two registers C and D which are directly connected and is used for relieving the probability of metastable state occurrence.
4. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the enabling decision unit (3) consists of a majority voter and a rising edge pulse generator circuit.
5. The multi-bit data cross-clock-domain synchronization circuit for triple modular redundancy of claim 1, wherein: the data selection output unit (4) comprises a 2-to-1 data selector mux, a bit-based majority Voter Voter2 and a data output register E.
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