KR102415074B1 - Delay circuit, controller for asynchronous pipeline, method of controlling the same, and circuit having the same - Google Patents

Abstract

The present invention relates to a delay circuit, an asynchronous pipeline controller, a control method thereof, and a circuit having the same. According to an embodiment of the present invention, a delay circuit for delaying and transmitting an input signal includes at least one delay unit; and a logic element connected to the at least one delay unit, wherein the logic circuit is configured such that, when a transition of the input signal occurs, the input signal repeatedly passes through the at least one delay unit at least twice or more. A logical operation can be performed.

Description

Delay circuit, controller for asynchronous pipeline, method of controlling the same, and circuit having the same

The present invention relates to circuit technology, and more particularly, to a delay circuit, an asynchronous pipeline controller using the same, a control method thereof, and a circuit having the same.

Synchronous circuit design is the basis for the proliferation of very-large-scale integration (VLSI) systems and the development of the semiconductor industry. One of the advantages of the synchronous circuit design is that it can simplify the synchronization of all components of the system through a global clock network. When designing the synchronous circuit, a plurality of sequentially serially connected delay buffers corresponding to a target delay value (hereinafter referred to as a delay buffer chain) are artificially inserted to match the timing. can A signal passes through a plurality of delay buffers connected in series, and may be delayed due to delay characteristics of each buffer. Accordingly, as the target delay value increases, the number of serially connected buffers increases. Due to the configuration of such a delay buffer chain in a synchronous circuit, an area overhead may occur when designing an asynchronous circuit.

Due to recent advances in semiconductor manufacturing processes and advances in fields such as deep neural networks, electronic circuits operating at higher speeds and with lower power are required. However, in a synchronous circuit, applications are further limited due to noise and delay variability due to increased process-voltage-temperature (PVT) fluctuations, and power consumption of a clock network faces a large problem.

In order to reduce power consumption in such a clock network, an asynchronous circuit is introduced. Unlike a synchronization mechanism that uses the global clock network of the synchronous circuit, the asynchronous circuit uses a handshaking protocol for communication between circuit components. The handshaking protocol consumes relatively less dynamic power than the synchronous circuit and can operate at high frequencies. In the case of the synchronous circuit, a significant portion of the total dynamic power is consumed in the global clock network, and the performance of the entire system, ie, the minimum clock period, is affected by the most important timing path. On the other hand, since the asynchronous circuit is independent of the clock time, a clock network that consumes a lot of power is not required.

The handshaking protocol consists of three connection lines, namely, data, request (req), and acknowledgment (ack) signals, and data (data) and request (req) signals are provided by the transmitter and acknowledgment (ack) The signal is provided by the receiver. When the transmitter transmits a request (req) signal to the receiver before transmitting data to the receiver and receives an acknowledgment (ack) signal corresponding to the request (req) signal from the receiver, data can be transmitted.

In addition, the asynchronous circuit has a pipeline structure of several to tens of stages, and operates based on a bundled data protocol. The packed data protocol is similar to IP (Internet Protocol) in TCP/IP, but TCP/IP requires continuous end-to-end connections, whereas the packed data protocol operates in a Store-and-Forward manner. is the protocol.

However, the asynchronous circuit based on the packed data protocol must satisfy the timing constraint that the receiver must not accept the request signal before receiving the data signal from the transmitter. To ensure the timing constraint, a chain of delay buffers is provided to deliberately provide a long delay path to each stage of the pipeline structure. As with the synchronous circuit, an area overhead may occur when designing an asynchronous circuit due to the configuration of the delay buffer chain. In particular, as the delay required to satisfy the handshaking protocol increases, the delay buffer occupies a significant portion of the pipeline structure.

Accordingly, there is a need for a technique for improving the area overhead due to the delay buffer chain in the synchronous circuit or the asynchronous circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a delay circuit that improves power consumption and area overhead due to an increase in the number of delay buffers.

An object of the present invention is to provide an asynchronous pipeline controller that improves power consumption and area overhead due to an increase in the number of delay buffers while satisfying timing constraints in an asynchronous circuit having a pipeline structure.

Another technical object of the present invention is to provide a method for controlling an asynchronous pipeline having the above-described advantages.

Another technical object of the present invention is to provide a circuit having an asynchronous pipeline having the above-mentioned advantages.

According to an embodiment of the present invention, there is provided a delay circuit for delaying transmission of an input signal, the delay circuit comprising: at least one delay unit providing a delay path; and at least one or more logic elements connected to the at least one or more delay units, wherein the logic circuit uses the input signal at least twice to reuse the delay path when a transition of the input signal occurs. It is possible to perform a logical operation that passes repeatedly.

In one embodiment, there is provided a first latch element having a first input terminal for receiving the input signal, a first output terminal for outputting the input signal, and a second output terminal for inverting and outputting the input signal; a second latch element connected to the first output terminal of the first latch element and having a first input terminal for receiving the input signal passing through the first latch element and an output terminal for outputting the input signal; and disabling the second latch element while enabling the first latch element at a first time point, and disabling the first latch element at a second time point later than the first time point. A control circuit may be further included to enable and control the input signal to pass through the at least one delay unit at least two times without collision. The control element may include: a first XOR element that outputs 0 or 1 to the input signal and an inverted input signal from a second output terminal of the first latch element; a second XOR element configured to output 0 or 1 to an input signal output from an output terminal of the first latch element and an input signal outputted from an output terminal of the second latch element; and a NOR element configured to enable or disable the first latch element by outputting 0 or 1 to the output signal of the first XOR element and the output signal of the second XOR element as inputs, wherein the delay unit includes the first 1 is disposed between the output terminal of the XOR element and the input terminal of the NOR element, and may delay the output signal of the first XOR element to be transmitted to the input terminal of the NOR element and the input terminal of the second latch element. An input terminal of the first XOR element and the second output terminal of the first latch element are connected, and a first input terminal of the second XOR element and a first output terminal of the first latch element are connected, and the second XOR element may be connected to a second input terminal of the , and an output terminal of the second latch element, and connected to an output terminal of the NOR element and a second input terminal of the first latch element. An output terminal of the first XOR element may be connected to a first input terminal of the NOR element and a second input terminal of the second latch element, and a second input terminal of the NOR element may be connected to an output terminal of the second XOR element. In one embodiment, the delay unit may be connected in series with at least one buffer or inverter in a chain form or may be connected without a buffer or inverter.

In an embodiment, when the number of the at least one delay unit is m, the m delay units are electrically connected to each other through a second logic circuit identical to but physically separated from the first logic element to transmit the input signal by 2 ^m . , 2 ^m-1 ,.., 2 ¹ passes and sequentially passes to the next first delay unit, and the m-th delay unit passes the input signal twice and transmits it to the m-1 delay unit, and the m-1 delay part 2 The input signal may be passed through the input signal twice to be transmitted to the m-2 delay unit, and the m-2 th delay unit may be passed through the input signal twice to be transmitted to the m-3 th delay unit.

According to another embodiment of the present invention, a second timing having an area at least partially overlapping with the first timing path based on a first request signal coming from a first timing path controlled by a first asynchronous pipeline controller a second asynchronous pipeline controller for controlling a path, the second asynchronous pipeline controller including a delay path unit for providing the second timing path such that the first request signal passes through the overlapping region at least two times or more can do. The delay path unit includes a first input terminal for receiving the first request signal, a first output terminal for outputting a second confirmation signal in response to the first request signal, and a second output terminal for inverting and outputting the second confirmation signal a first latch element having a; a second latch element having a first input terminal connected to a first output terminal of the first latch element and an output terminal outputting a second request signal in response to a third confirmation signal; and deactivating the second latch element while operating the first latch element at a first time point, and disabling the second latch element at a second time point later than the first time point. and a logic circuit that operates to output the second request signal to a third asynchronous pipeline controller. The logic element may include: a first XOR element outputting 0 or 1 to the first request signal and the inverted second confirmation signal as inputs; a second XOR element that outputs 0 or 1 to the second acknowledgment signal and a third acknowledgment signal fed back from the third asynchronous pipeline controller; a NOR element that operates or deactivates the first latch element by outputting 0 or 1 to the output signal of the first XOR element and the output signal of the second XOR element; and a shared delay circuit disposed between the output terminal of the first XOR element and the input terminal of the NOR element to delay the output signal of the first XOR element and provide the delayed output signal to the input terminal of the NOR element. In the shared delay circuit, at least one buffer or inverter may be connected in series in a chain form, or may be connected without a buffer or inverter. An input terminal of the first XOR element and a second output terminal of the first latch element are connected, the first input terminal of the second XOR element and a third timing path are connected, and the second input terminal of the second XOR element and the It may be connected to a first output terminal of the first latch element, and may be connected to an output terminal of the NOR element and a second input terminal of the first latch element. An output terminal of the first XOR element may be connected to a first input terminal of the NOR element and a second input terminal of the second latch element, and a second input terminal of the NOR element may be connected to an output terminal of the second XOR element.

In one embodiment, it further comprises a non-shared delay circuit connected to the output terminal of the second latch element, the non-shared delay circuit, at least one buffer or inverter is connected in series in a chain form, or may be connected without a buffer or inverter. The delay of the second timing path may be adjusted by the number of buffers or inverters of the shared delay circuit and the non-shared delay circuit. A time interval between arrival of the first request signal and closing of the first latch element may be less than or equal to a time interval in which the first latch element is operated by a third confirmation signal provided from the third timing path . A time interval between arrival of the first request signal and closing of the first latch element may be less than or equal to an interval between first request signals provided from the first timing path. The overlapping region may include the first XOR element and the shared delay circuit.

In an embodiment, when the delay path unit includes m delay circuits, the m delay circuits are electrically connected to each other to transmit the first request signal 2 ^m , 2 ^m-1 ,.., 2 ¹ , respectively. pass the number of times, but the mth delay circuit is 2 time passing the first request signal to an m-1 delay circuit, and the m-1 delay circuit times the first request signal is passed to the m-2 delay circuit, and the m-2 delay circuit is It is possible to pass the first request signal to the m-3 delay circuit.

In accordance with another embodiment of the present invention, a second timing path having a first region that at least partially overlaps with a first timing path controlled by a first asynchronous pipeline controller is controlled, the second timing path being coupled to the first timing path. A method for controlling a second asynchronous pipeline controller comprising a first latch element, a second latch element connected to the first latch element, and a logic element controlling the first and second latch elements, wherein the first timing receiving a first request signal through a path; transitioning the first latch element to an enabled state in response to the first request signal; transitioning the first latch element from the enabled state to the disabled state and transitioning the second latch element to the enabled state in response to an inverted output signal of the first latch element in the enabled state; and outputting a second request signal through the second latch element.

The method may further include receiving a third acknowledgment signal from a third timing path controlled by a third asynchronous pipeline controller that includes a second region that at least partially overlaps the second timing path. a first XOR element in which the logic element is connected to a second output terminal of the first latch element, a second XOR element connected to a first output terminal of the first latch element, an output terminal of the first XOR element and the second XOR element; In response to the first request signal, when the NOR element connected and connected to the input terminal of the first latch element is configured with a shared delay circuit disposed between the output terminal of the first XOR element and the input terminal of the NOR element, the first latch Transitioning the device to the enabled state may include: first activating the first XOR device based on the first request signal and an inverted signal from a first output terminal of the first latch device; first activating the second XOR element based on an output signal of the first latch element and a third confirmation signal transmitted from a third timing path; first activating a NOR element based on output signals of the first XOR element and the second XOR element; and enabling the first latch element by the output signal of the NOR element. Transitioning the first latch element from the enabled state to the disabled state and transitioning the second latch element to the enabled state in response to an inverted output signal of the first latch element in the enabled state; second activating the first XOR element based on an inverted output signal of the first latch element in the enabled state and the first request signal; and enabling the second latch element by the output signal of the first XOR element.

In an embodiment, the method may further include: second activating the second XOR element based on an output signal of the first latch element and a third confirmation signal transmitted from a third timing path; activating a second NOR element based on output signals of the first XOR element and the second XOR element; and disabling the first latch element by the output signal of the NOR element. The output signal of the first XOR element may be delayed and transferred to the input terminal of the NOR element and the input terminal of the second latch element through the shared delay circuit. A second acknowledgment signal corresponding to the second request signal does not arrive before the enable signal provided to the second latch element D2 falls, or the second acknowledgment signal to prevent invalid transfer of the first request signal. The second confirmation signal may arrive at the second latch element D2 before the enable signal provided to the second latch element D2 rises.

According to another embodiment of the present invention, there is provided an asynchronous pipeline circuit comprising n pipeline stages, each pipeline stage comprising: a data latch providing a data path; and the asynchronous pipeline controller of claim 8 for actuating or deactivating the data latch.

According to an embodiment of the present invention, by performing a logical operation such that an input signal repeatedly passes through the at least one delay unit at least twice or more in the delay element, power consumption and area due to an increase in the number of delay buffers A delay circuit capable of improving overhead may be provided.

According to another embodiment of the present invention, based on a first request signal coming from a first timing path controlled by* a first asynchronous pipeline controller, a second second having an area that at least partially overlaps with the first timing path. Asynchronous with a pipeline structure by including a delay path unit for providing the second timing path so that the second asynchronous pipeline controller controlling the timing path causes the first request signal to pass through the overlapping region at least twice or more An asynchronous pipeline controller capable of improving power consumption and area overhead due to an increase in the number of delay buffers while satisfying timing constraints in a circuit may be provided.

Further, according to another embodiment of the present invention, a control method of an asynchronous pipeline controller having the above-described advantages may be provided.

Further, according to another embodiment of the present invention, an asynchronous circuit having a pipeline structure using an asynchronous pipeline controller having the above-described advantages can be provided.

1A and 1B are schematic configuration diagrams of a delay circuit according to an embodiment of the present invention.
2A to 2C are diagrams illustrating a delay circuit according to an embodiment of the present invention.
3 is a schematic circuit diagram of an asynchronous pipeline structure including a plurality of processing stages according to an embodiment of the present invention.
4 is a diagram for explaining a handshaking protocol based on bundled data according to an embodiment of the present invention.
5 is a block diagram of a delay path unit constituting an asynchronous pipeline controller according to an embodiment of the present invention.
6 is a diagram illustrating a configuration circuit of an asynchronous pipeline controller according to an embodiment of the present invention.
7 is a view for explaining an overlapping region of an i-th timing path of an i-th pipeline stage and an i+1-th timing path of an i+1-th pipeline stage in an asynchronous circuit having a pipeline structure according to an embodiment of the present invention; to be.
8 is a waveform showing the timing of an asynchronous pipeline controller according to an embodiment of the present invention.
9 is a diagram for explaining a logical operation of an asynchronous pipeline controller according to an embodiment of the present invention.
10 is a flowchart illustrating a method of designing a shared delay circuit (SDC) and a non-shared delay circuit (NSDC) of an asynchronous pipeline controller having an asynchronous pipeline structure according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Examples of the present invention are provided to more completely explain the present invention to those of ordinary skill in the art, and the following examples may be modified in various other forms, and the scope of the present invention is as follows It is not limited to an Example. Rather, these examples are provided so as to fully convey the spirit of the present invention to those skilled in the art.

In the drawings, like reference numerals refer to like elements. Also, as used herein, the term “and/or” includes any one and all combinations of one or more of those listed items.

The terminology used herein is used to describe the embodiment, and is not intended to limit the scope of the present invention. Also, although the singular is used herein, the plural form may be included unless the context clearly indicates the singular. Also, as used herein, the terms "comprise" and/or "comprising" specify the presence of the recited shapes, numbers, steps, actions, members, elements, and/or groups thereof. It does not preclude the presence or addition of other shapes, numbers, movements, members, elements and/or groups.

Reference herein to a layer formed “on” a substrate or other layer refers to a layer formed directly on the substrate or other layer, or an intermediate layer or intermediate layers formed on the substrate or other layer. It may also refer to a layer. Also, for those skilled in the art, a structure or shape disposed "adjacent" to another shape may have a portion disposed above or below the adjacent shape.

As used herein, “below”, “above”, “upper”, “lower”, “horizontal” or “vertical” Relative terms such as , as shown in the drawings, may be used to describe the relationship that one constituent member, layer or region has with another constituent member, layer or region. It should be understood that these terms encompass not only the orientation indicated in the drawings, but also other orientations of the device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to cross-sectional views schematically illustrating ideal embodiments (and intermediate structures) of the present invention. In these drawings, for example, the size and shape of the members may be exaggerated for convenience and clarity of description, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to the specific shapes of the regions shown herein. Also, reference numerals for members in the drawings refer to the same members throughout the drawings.

1A to 1B are schematic configuration diagrams of a delay circuit according to an embodiment of the present invention.

Referring to FIG. 1A , the delay element DC1 physically and logically connects the first delay unit BDL0, the second delay unit BDL1, and the first delay unit BDL0 and the second delay unit BDL1. A logic circuit LC1 may be included. When a transition of the input signal IN occurs, the logic circuit LC1 performs a logical operation so that the input signal IN repeatedly passes through the second delay unit BDL1 at least twice or more. can do. That is, a delay path that is reused at least twice or more by the second delay unit BDL1 may be provided. The input signal delayed through the second delay unit BDL1 may pass through the first delay unit BDL0 once and be output as the output signal OS. The delay of the delay element DC1 may be adjusted by the first delay unit BDL0 and the second delay unit BDL1 . In an embodiment, the first delay unit BDL0 may be omitted, but the present invention is not limited thereto.

Referring to FIG. 1B , the delay element DC2 includes a first delay unit BDL0 and m second delay units BDL ₁ to BDL _m and second delay units BDL ₁ to BDL _m each providing a delay path. ) by physically and logically connecting them to provide a reuse delay path composed of second delay units, the logic circuits LC ₁ to LC _m may be included. The logic circuits LC ₁ to LC _m may have the same circuit configuration. When the number of the second delay units BDL ₁ to BDL _m is m (m > 1), the m second delay units BDL ₁ to BDL _m are electrically connected to each other through the logic circuits LC ₁ to LC _m . to the first delay unit BDL0 by passing the input signal 2 ^m , 2 ^m-1 ,.., 2 ¹ times. The m-th second delay unit BDL _m passes the input signal IN twice and transmits it to the m-1 th second delay unit BDL _m-1 , and the m-1 th second delay unit BDL _m-1 ) passes the input signal to the m-2 th second delay unit BDL _m-2 , and the m-2 th second delay unit BDL _m-2 receives the input signal twice. can be passed to the m-3 th second delay unit BDL _m-3 . In this way, the delay path provided by the m second delay units BDL ₁ to BDL _m can achieve the delay of the input signal in such a way that it is reused. Detailed description of the logic circuits LC1 to LCm is Reference is made to FIGS. 2A to 2C, which will be described later.

2A to 2C are diagrams illustrating delay circuits DC1, DC2, and DC3 according to another embodiment of the present invention.

Referring to FIG. 2A , the logic element LC1 of the delay circuit DC1 has an input terminal for receiving the input signal IN, a first output terminal for outputting the input signal IN, and inverting and outputting the input signal IN. A first latch element (D1) having a second output terminal, a first input terminal connected to the first output terminal of the first latch element (D1) to receive an input signal (S1) passing through the first latch element (D1); Disabling the second latch element D2 while enabling the second latch element D2 and the first latch element D1 having an output terminal for outputting the input signal S3 at the first time point, and at the first time point At a later second time point, the second latch element D2 is enabled while the first latch element D1 is disabled so that the initial input signal IN passes through the second delay unit BDL1 twice without collision. It may include a control circuit (two XOR, one NOR) to control. The input signal S1 refers to a signal from which the input signal IN is output through the first latch element D1 , and the input signal S2 is the input signal IN which is inverted through the first latch element D1 . Refers to an output signal, and the input signal S3 refers to a signal from which the input signal S1 is output through the second latch element D2.

In one embodiment, the control element is a first XOR element XOR1 that outputs 0 or 1 to the input signal IN and the inverted input signal S2 from the second output terminal of the first latch element D1. ), a second XOR element that outputs 0 or 1 to the input signal S3 output from the output terminal of the second latch element D2 and the input signal S1 output from the output terminal of the first latch element D1 as inputs A NOR element for enabling or disabling the first latch element D1 by outputting 0 or 1 to (XOR2) and the output signal of the first XOR element XOR1 and the output signal of the second XOR element XOR2 as inputs (NOR). The second delay unit BDL1 is disposed between the output terminal of the first XOR element XOR1 and the input terminal of the NOR element NOR, and delays the output signal of the first XOR element XOR1 to the input terminal of the NOR element NOR. and an input terminal of the second latch element D2. Here, the signal provided to the input terminal of the second latch element D2 through the first XOR element XOR1 and the second delay unit BDL1 is a control signal for enabling or disabling the second latch element D2. can be used

In one embodiment, the input terminal of the first XOR element XOR1 and the second output terminal of the first latch element D1 are connected, and the first input terminal of the second XOR element XOR2 and the first latch element D1 are connected. connected to the first output of It may be connected to the second input terminal. Also, an output terminal of the first XOR element XOR1 may be connected to a first input terminal of the NOR element NOR and a second input terminal of the second latch element D2 . A second input terminal of the NOR element NOR and an output terminal of the second XOR element XOR2 may be connected.

In an embodiment, at least one buffer or inverter may be serially connected to the first delay unit BDL0 or the second delay unit BDL1 in a chain form. The delay of the delay circuit DC may be adjusted by the total number of buffers of the first delay unit BDL0 and the second delay unit BDL1 . Alternatively, the first delay unit BDL0 and the second delay unit BDL1 may be configured without a buffer or an inverter.

In an embodiment, the initial input signal IN ₁ passes through the first XOR element XOR1 , the second delay unit BDL1 , and the NOR element NOR to pass through the second delay unit BDL1 once. At this time, the first latch element D1 is enabled by the output signal of the NOR element NOR, and the inverted input signal S2 is input to the first XOR element XOR1, but the second latch element D2 is Since it is disabled, the input signal S1 output from the first latch element D1 is not stored in the second latch element D2.

Thereafter, by the inverted input signal S2 , the input signal IN ₂ passes through the first XOR element XOR1 , the second delay unit BDL1 and the NOR element NOR to pass the second delay unit BDL1 to 2 will pass through At this time, the first latch element D1 is disabled by the output signal of the NOR element NOR, the second latch element D2 is enabled, and the input signal S1 outputted from the first latch element D1 is ) may be stored in the second latch element D2 and output.

Referring to FIG. 2B , the delay element DC2 includes a first logic element LC1 , a second logic element LC2 , a first delay unit BDL0 , a second delay unit BDL1 , and a third delay unit BDL2 . ) may be included. In an embodiment, the first delay unit BDL0, the second delay unit BDL1, and the third delay unit BDL2 may be configured as a buffer chain or an inverter chain. However, the present invention is not limited thereto, and the delay unit may be configured through a plurality of D latch elements connected in series. The logic element LC1 and the logic element LC2 may each include a first latch element D1 , a second latch element D2 , and a control circuit (two XORs and one NOR). Unless contradicted, the descriptions of the first latch element D1, the second latch element D2, and the control circuit refer to the first latch element D1, the second latch element D2, and the control circuit in FIG. 2A. You can refer to the description.

In an embodiment, the second logic element LC2 may be disposed between the XOR element XOR1 of the first logic element LC1 and the second delay unit BDL1 , and the output of the second logic element LC2 is The signal S3 is provided to the input terminal of the NOR element NOR of the first logic element LC1 through the second delay unit BDL1 , and is output from the first XOR element XOR1 of the first logic element LC1 . The signal may be provided to an input terminal of the first XOR element XOR1 of the second logic element LC2 . The third delay unit BDL2 may be disposed between the NOR element NOR of the second logic element LC2 and the first XOR element XOR1 . The first delay unit BDL0 may be connected to the output terminal of the first logic element LC1 to delay the output signal S3 .

In one embodiment, in order to enable the first latch element D1 of the first logic element LC1 , the first latch element D1 and the second latch element D2 of the second logic element LC2 are enabled. should be enabled sequentially. Here, in order to enable the second latch element D2 of the second logic element LC2 , the input signal IN must pass through the third delay unit BDL2 repeatedly twice. Specifically, when the input signal IN passes through the third delay unit BDL2 once, the first latch element D1 of the second logic element LC2 is enabled and the second logic element LC2 ) of the second latch element D2 is disabled, and when the input signal IN passes through the third delay unit BDL2 again twice (or the second latch of the second logic element LC2) When the inverted signal S2 of the element D2 is input to the first XOR element XOR1), the first latch element D1 of the second logic element LC2 is disabled and the second logic element The second latch element D2 of LC2 may be enabled to transmit the input signal IN to the second delay unit BDL1. Thereafter, the input signal IN passing through the second delay unit BDL1 passes through the NOR element NOR of the first logic element LC1 to enable the first latch element D1.

After the first latch element D1 of the first logic element LC1 is enabled, the inverted signal S2 output from the first latch element D1 of the first logic element LC1 is the first logic It is input to the first XOR element XOR1 of the element LC1 , and in this case, the output signal of the first XOR element XOR1 of the first logic element LC1 is the first XOR element XOR1 of the second logic element LC2 ) can be re-entered. Thereafter, the output signal of the first XOR element XOR1 of the first logic element LC1 passes through the third delay unit BDL2 twice again, so that the first latch element D1 of the first logic element LC1 may be disabled and the second latch element D2 of the first logic element LC1 may be enabled. As described above, the input signal IN of the delay element DC2 repeatedly passes through the third delay unit BDL2 a total of four times (=2 ² ), and passes through the second delay unit BDL1 a total of two times ( =21), so the number of delay buffers can be reduced. Accordingly, according to an embodiment of the present invention, since the number of delay buffers can be reduced, problems such as area overhead and/or leakage power caused by an increase in the number of delay buffers can be solved. In one embodiment, when the delay circuit according to an embodiment of the present invention is applied to a timing control circuit of an asynchronous circuit replacing a clock network, there is an advantage in that a low-power, high-performance semiconductor chip can be provided.

Referring to FIG. 2C , the delay element DC3 includes a first logic element LC1 , a second logic element LC2 , a third logic element LC3 , a first delay unit BDL0 , and a second delay unit BDL1 . ), a third delay unit BDL2 and a fourth delay unit BDL3 may be included. In an embodiment, the first delay unit BDL0, the second delay unit BDL1, the third delay unit BDL2, and the fourth delay unit BDL3 may be configured as a buffer chain or an inverter chain. The delay unit may be configured through a plurality of D latch elements connected in series. The logic element LC1, the logic element LC2, and the logic element LC3 may each include a first latch element D1, a second latch element D2, and a control circuit (two XORs, one NOR). have. Unless contradicted, the descriptions of the first latch element D1, the second latch element D2, and the control circuit refer to the first latch element D1, the second latch element D2, and the control circuit in FIG. 2A. You can refer to the description.

In an embodiment, the third logic element LC3 is disposed between the XOR element XOR1 of the second logic element LC2 and the third delay unit BDL2, and the second logic element LC2 includes the first logic element LC2. It may be disposed between the XOR element XOR1 of the element LC1 and the second delay unit BDL1 . In addition, in order for the first latch element D1 of the first logic element LC1 to be enabled, the second latch element D2 of the second logic element LC2 must be enabled, and the second logic element D1 must be enabled. In order to enable the second latch element D2 of the element LC2, the first latch element D1 of the second logic element LC2 must be inactive. To this end, the third logic element LC3 is The second latch element D2 may provide a signal for switching the first latch element D1 of the second logic element LC2 from operation to non-operation.

Here, in order for the first latch element D1 of the first logic element LC1 to be enabled in disable and the second latch element D2 of the first logic element LC1 to maintain disable, the input signal IN is 4 It must pass through the delay unit BDL3 four times and then pass through the third delay unit BDL2 twice. Thereafter, the input signal IN is applied so that the first latch element D1 of the first logic element LC1 is again disabled in enable and the second latch element D2 of the first logic element LC1 is enabled in disable. It must pass through the fourth delay unit BDL3 four times and then pass through the third delay unit BDL2 twice. Consequently, in order for the input signal IN to pass through the first delay unit BDL0 and output, the input signal IN passes through the fourth delay unit BDL3 eight times (=2 ³ ), and the third delay It must pass through the section BDL2 4 times (=2 ² ) and pass through the second delay section BDL1 twice (=2 ¹ ).

Specifically, when the input signal IN passes through the fourth delay unit BDL3 once, the first latch element D1 of the third logic element LC3 is enabled and the third logic element is activated. The second latch element D2 of LC3 is disabled, and thereafter, when the input signal IN passes through the fourth delay unit BDL3 twice (or the third logic element LC3) When the inverted signal S2 of the first latch element D1 is input to the first XOR element XOR1 of the third logic element LC3), the first latch element D1 of the third logic element LC3 is It is disabled and the second latch element D2 of the third logic element LC3 is enabled, and the input signal IN is transferred to the third delay unit BDL2, and the second logic element LC2 ) of the first latch element D1 may be enabled.

Thereafter, the inversion signal S2 of the first latch element D1 of the second logic element LC2 is transferred to the first XOR element XOR1 of the second logic element LC2 and the The output signal of the first XOR element XOR1 is again transferred to the first XOR element XOR1 of the third logic element LC3 so that the input signal IN passes through the fourth delay unit BDL3 three times. In this case, the first latch element D1 of the third logic element LC3 is enabled in the disabled state, and the second latch element D2 of the third logic element LC3 is disabled. do. Afterwards, when the input signal IN passes through the fourth delay unit BDL3 four times (or the inverted signal S2 of the first latch element D1 of the third logic element LC3 is changed to the first XOR element XOR1 ) )), the first latch element D1 of the third logic element LC3 is disabled and the second latch element D2 of the third logic element LC3 is enabled. The input signal IN is transmitted to the third delay unit BDL2 , so that the first latch element D1 of the second logic element LC2 is disabled and the second latch element D2 is enabled.

Thereafter, the input signal IN passing through the second logic element LC2 and the second delay unit BDL1 passes through the NOR element NOR of the first logic element LC1 to the first logic element LC1 . of the first latch element D1 is enabled. And after the first latch element D1 of the first logic element LC1 is enabled, the inverted signal S2 of the first latch element D1 of the first logic element LC1 becomes the first logic element It is input to the first XOR element XOR1 of LC1, and in this case, the output signal of the first XOR element XOR1 of the first logic element LC1 is the first XOR element XOR1 of the second logic element LC2 may be input back to the first XOR element XOR1 of the third logic element LC3 through

At this time, the input signal IN passes through the fourth delay unit BDL3 five times, the first latch element D1 of the third logic element LC3 is enabled, and the third logic element LC3 is activated. The second latch element D2 is disabled. Then, when the input signal IN passes through the fourth delay unit BDL3 six times (or the inverted signal S2 of the first latch element D1 of the third logic element LC3 is ) of the first XOR element XOR1), the first latch element D1 of the third logic element LC3 is disabled and the second latch element ( D2 is enabled to transmit the input signal IN to the third delay unit BDL2 to enable the first latch element D1 of the second logic element LC2.

Thereafter, the inversion signal S2 of the first latch element D1 of the second logic element LC2 is transferred to the first XOR element XOR1 of the second logic element LC2 and the The output signal of the first XOR element XOR1 is again transferred to the first XOR element XOR1 of the third logic element LC3 so that the input signal IN passes through the fourth delay unit BDL3 seven times. In this case, the first latch element D1 of the third logic element LC3 is enabled in the disabled state, and the second latch element D2 of the third logic element LC3 is disabled. do. Thereafter, when the input signal IN passes through the fourth delay unit BDL3 eight times (or the inverted signal S2 of the first latch element D1 of the third logic element LC3 is ) of the first XOR element XOR1), the first latch element D1 of the third logic element LC3 is disabled and the second latch element ( D2) is enabled to transmit the input signal IN to the fourth delay unit BDL3, the first latch element D1 of the second logic element LC2 is disabled, and the second latch element D2 is enabled.

Thereafter, the input signal IN passing through the second logic element LC2 and the second delay unit BDL1 passes through the NOR element NOR of the first logic element LC1 to the first logic element LC1 . of the first latch element D1 may be disabled and the second latch element D2 of the first logic element LC1 may be enabled. In this case, the input signal S3 output from the second latch element D2 of the first logic element LC1 may be output to the first delay unit BDL0.

As described above, the input signal IN of the delay element DC3 repeatedly passes through the fourth delay unit BDL3 a total of 8 times (=2 ³ ), and passes through the third delay unit BDL2 a total of 4 times ( =2 ² ) and passes through the second delay unit BDL1 a total of two times (=2 ¹ ), so that the number of delay buffers can be reduced. In an embodiment, a delay path may be provided so that the input signal IN passes through the M delay units BDL ₁ to BDL _m at least twice or more. When the M delay units are electrically connected to each other, the input signal IN passes through the delay unit BDL _m a total of 2 ^m times and passes through the delay unit BDL _m-1 2 ^m-1 times, The delay unit (BDL ₁ ) is passed through a total of two times (=2 ¹ ).

3 is a schematic asynchronous circuit of a pipeline structure composed of a plurality of processing stages according to an embodiment of the present invention.

Referring to FIG. 3 , an asynchronous circuit having a pipeline structure may include n pipeline stages. The flyline structure is a structure in which an output of a processing step is connected in a manner that leads to an input of a next processing step. In one embodiment, each processing step may consist of the same or different combinational circuits CC ₁ , CC ₂ ,..., CC _n . The first combination circuit (CC ₁ ) may receive data from the transmitting end, process it, and output the processed data to the second combination circuit (CC ₂ ), and the n-th combination circuit (CC _n ) is an n-1th combination The data output from the circuit CC _n-1 may be received and processed, and the processed data may be output to the receiving end. The combination circuit may be defined as a module.

In one embodiment, the asynchronous circuit of the pipeline structure may perform data transfer between pipeline stages or between modules based on a handshaking protocol. The handshaking protocol additionally uses a request signal and an acknowledgment signal in addition to a data line between neighboring modules. When it is necessary to start an operation of a neighboring module, a request signal indicating the start of the operation is transmitted from the transmitting module to the receiving module, and the receiving module receiving the request signal may start an operation. When the operation is completed, a confirmation signal is sent to the transmission module that transmitted the request signal to indicate that the operation is finished.

In addition, in an asynchronous circuit having a pipeline structure in which a symbol of transmission data and a start time of the symbol are variable, an accurate transition indicating the validity of an event is required. A signaling scheme and a data encoding scheme can be used to generate (from the transmitter side) or detect (the receiver side) an accurate transition. Various implementation methods are possible according to each method, and the asynchronous handshaking method may be implemented in various ways according to channel types.

The signaling method is 4 depending on whether only one of the rising and falling of the request and acknowledgment signal pairs, which means the data validity time and the completion of data processing, is used or all are used. It is divided into -phase (use one side) and two-phase (use both sides). 4-phase signaling must always go through an initialization state (space state), and 2-phase signaling does not have an initialization state (space state).

In the bundled data method, the request signal informs the valid timing of data, just as the clock signal informs the valid timing of data in a synchronous circuit without additional data encoding. Specifically, the request signal and transmission data may be synchronized and generated. A timing constraint follows that the request signal must not be accepted before receiving the valid data.

In one embodiment, to support the handshaking protocol described above, each pipeline stage includes an asynchronous pipeline controller (APC ₁ , APC ₂ ,..., APC _n ), a data latch (DD ₁ , DD ₂ ,. .., DD _n ). The asynchronous pipeline controllers (APC ₁ , APC ₂ ,..., APC _n ) each have a request signal (R ₀ , R ₁ ,..., R _n ) and an acknowledgment signal (A ₁ , A,..., A _n+1 ) to enable (hereinafter, referred to as 'operational') or disable (hereinafter referred to as 'inactive') the data latches DD ₁ , DD ₂ , ..., DD _n by the transition The control signals CS ₁ , CS ₂ , ..., CS _n may be output. Based on the control signals CS ₁ , CS ₂ , ..., CS _n , the data latches DD ₁ , DD ₂ ,..., DD _n may store and forward data.

In one embodiment, each pipeline stage communicates with each other using a request signal (R ₀ , R ₁ ,..., R _n ) and an acknowledgment signal ( A ₁ , A,..., A _N+1 ). . The request signals (R ₀ , R ₁ , ..., R _n ) may be received from the transmitting end and transmitted to the receiving end. Similarly, the acknowledgment signals A ₁ , A ₂ , ..., A _n+1 may be received from the receiving end and transmitted to the transmitting end.

In one embodiment, when data passes through the data latches DD ₁ , DD ₂ ,..., DD _n of the corresponding pipeline stage, n operations may occur in parallel. (i) Data is forwarded for further processing from the current stage to the subsequent stage together with the corresponding request signal. (ii) The acknowledgment signal is sent from the current stage to the previous stage, and is freed until processing the next data. (iii) The data latch itself of the current stage is quickly blocked (ie, becomes opaque) to prevent overlapping by new data generated in the previous stage. Then, when an acknowledgment signal is received from the subsequent stage, the data latch of the current pipeline stage is re-enabled (ie, made transparent). For example, when data is transferred through the data latch DD ₁ of the first pipeline stage, the following operations occur in parallel. (i) The data and the corresponding request signal R ₁ are passed to a second pipeline stage for further processing. (ii) the acknowledgment signal A ₁ is passed to the previous stage of the first pipeline stage, and (iii) the data latch DD ₁ of the first pipeline stage is blocked so that new data generated by the previous pipeline stage It is possible to prevent overlapping with the current data. Then, the data latch DD ₁ may be re-enabled when the confirmation signal A ₂ is received in the second pipeline stage.

In one embodiment, valid data is greater than acceptance of request signals R ₀ , R ₁ ,..., R _n prior to receiving valid data than request signals R ₀ , R ₁ ,..., R _n . _In order to guarantee _{the timing constraint} that _it cannot ,...,DS _n ). Specifically, by arranging the delay circuits DS ₁ , DS ₂ ,...,DS _n in the timing path for transmitting the request signals R ₀ , R ₁ ,..., R _n , the timing constraint can satisfy The delay circuits DS ₁ , DS ₂ , ..., DS _n may include a plurality of buffer or inverter elements connected in series in a chain form.

However, since the data is processed through the combination circuits CC ₁ , CC ₂ ,..., CC _n in each pipeline stage, each combination circuit CC ₁ , CC ₂ ,..., CC _n is After receiving the request signals (R ₀ , R ₁ , ..., R _n ), each operation is driven according to the respective operation delay time, so the operation completion time may be all different. Accordingly, as the operation delay time of the combinational circuits CC ₁ , CC ₂ , ..., CC _n increases, more delay buffers are required. If the number of buffers or inverters connected in such a chain is increased, area overhead may increase and leakage power consumption may increase.

In the present invention, by at least partially overlapping the first and second timing paths controlled by the asynchronous pipeline controllers APC ₁ , APC ₂ , ..., APC _n adjacent to each other, the request signals R ₀ , R ₁ ,..., R _n ) may pass through the overlapping region at least twice or more. By disposing a shared delay circuit to be described later in the overlapping area, the number of buffers or inverters of the delay circuits DS ₁ , DS ₂ , ..., DS _n can be reduced. The first timing path may be a timing circuit corresponding to a first pipeline stage and the second timing path may be a timing circuit corresponding to a second pipeline stage.

4A and 4B show an example of a handshaking protocol based on bundled data according to an embodiment of the present invention.

Referring to FIG. 4A , a handshaking operation of a two-phase bundled data method is shown. Specifically, a transaction for a handshaking operation may start with data issued by the sender and a transition (eg, 1→0, 0→1) for a request (req) signal. In addition, when the receiver accepts the signal for the request signal, the transaction can be completed by starting to read data and performing a transition (eg, 1→0, 0→1) for the ack signal.

Referring to FIG. 4B , a handshaking operation of the 4-phase bundled data method is shown. First, the transmitter issues data and sets the request signal req to '1', and then the receiver detects the request signal and starts reading data. Afterwards, while the acknowledgment signal (ack) is set to '1', the transmitting end accepts the acknowledgment signal (ack), initializes the request signal (req) to '0', and finally the receiving end sets the acknowledgment signal (ack) to '0'. ' to complete the transaction.

5 is a block diagram of a delay path unit (DPU) constituting the asynchronous pipeline controllers (APC ₁ , APC ₂ , ..., APC _n ) according to an embodiment of the present invention.

Referring to FIG. 5 , the delay path unit may include a first latch element D1 , a second latch element D2 , and a logic circuit LC. In one embodiment, the first latch element D1 and the second latch element D2 may be configured as a D latch circuit. The D latch circuit has two inputs (D, Enable). In the enable state, a new bit is read from the D input terminal and outputs it, and in the disabled state, the stored bit can be maintained.

In an embodiment of the present invention, the first latch circuit D1 may output S2 by input signals S1 and CS1 or maintain the current state, and the second latch circuit D2 may hold S3 by input signals S2 and CS2. You can print it out or keep the current state. S1 is a request signal (req) introduced from a previous pipeline stage in the asynchronous circuit of the aforementioned pipeline structure, and S2 is an output signal of the first latch circuit (D1) and an acknowledgment signal (ack) output from the current pipeline stage At the same time, it is an input signal of the second latch circuit D2 , and S3 is an output signal of the second latch circuit D2 and may be a request signal req output in the current pipeline stage.

In an embodiment, S1 may be a signal that passes through a timing path of a previous pipeline stage (hereinafter referred to as a first timing path) and flows into a timing path of a current pipeline stage (hereinafter referred to as a second timing path). The second timing path refers to a path including the first latch element D1 , the logic circuit LC, and the second latch element D2 .

Also, at least a portion of the first timing path and the second timing path may physically overlap, and the overlapping region may exist in the logic circuit LC. Here, when the first latch circuit D1 is in a disabled state, the S1 signal may flow into the logic circuit LC and pass through the overlapped region. At this time, the logic circuit LC outputs a control signal CS1 for operating (enables) the first latch circuit D1 and at the same time a control signal CS2 for inactivating (disables) the second latch circuit D2. ) can be printed. Thereafter, the S1 signal is stored according to the enable control signal CS1. However, in this case, when the second latch circuit D2 is in the disabled state, the output signal S2 of the first latch circuit D1 is not stored in the second latch circuit D2.

Thereafter, the S2 signal may be provided to the logic circuit LC to pass through the overlapped region, and in this case, the logic circuit LC may be a control signal CS1 for inactivating (disabling) the first latch circuit D1. ) and simultaneously outputting the control signal CS2 for operating (enabling) the second latch circuit D2 . At this time, the first latch circuit D1 maintains the current state in the disabled state, and the output signal S2 of the first latch circuit D1 is stored in the second latch circuit D2 and then the output signal S3 can be output as

As described above, the logic circuit LC deactivates (disables) the second latch circuit D2 while operating (enabling) the first latch circuit D1 by the transition of the input signal S1. . Thereafter, the logic circuit LC switches the first latch circuit D1 from operation (enable) to non-operation (disable) by the output signal S2 of the first latch circuit D1, and the second latch circuit By operating (enable) D2 from non-operation (disable), the output signal S3 of the second latch circuit D2 can be output. As a result, by blocking the input signal S1 from passing through the second timing path until the second latch circuit D2 is enabled, the second latch circuit D2 operates from non-operation (disable) to operation ( Since the S1 signal can be delayed by the time until transition to enable), the size of the delay element disposed at the end of the second timing path can be reduced.

6 is a diagram illustrating a configuration circuit of an asynchronous pipeline controller (APC ₁ , APC ₂ , ..., APC _n ) according to an embodiment of the present invention.

Referring to FIG. 6 , the delay path unit DPU constituting the asynchronous pipeline controller may include a first latch element D1 , a second latch element D2 and a logic circuit LC to form a timing path. have. The timing path refers to a path through which a request signal or a confirmation signal related to a valid time of data is transmitted.

The first latch element D1 is a first input terminal that receives the first request signal req ^(i- 1) from the previous pipeline stage i-1, 'enable' or 'disable' or ' The second input terminal receives the first control signal EN1 for switching from 'disable' to 'enable', and outputs the output signal S2 in response to the first request signal req ^(i-1) in the 'enable' state It may include a first output terminal and a second output terminal for outputting the inverted signal (S3) of the output signal (S2). The output signal S2 may be transmitted as a second confirmation signal ack ⁽ⁱ⁾ to an input terminal of a second XOR element XOR2 to be described later. The second latch element D2 is a first input terminal that receives the output signal S2 or the second confirmation signal ack ⁽ⁱ⁾ , a first input terminal for switching from 'enable' to 'disable' or 'disable' to 'enable' 2 In response to the second input terminal receiving the control signal EN2 and the output signal S2 or the second acknowledgment signal ack ⁽ⁱ⁾ in the 'enable' state, the second request signal req ⁽ⁱ⁾ is output. It may include an output stage. Also, a first input terminal of the second latch element D2 may be connected to an input terminal of a second XOR element XOR2 to be described later.

In an embodiment, the logic circuit LC disables the second latch element D2 while enabling the first latch element D1 at a first time point, and later than the first time point. At the second time point, while the first latch element D1 is disabled, the second latch element D2 is operated to transmit the output signal S2 or the second request signal ack ⁽ⁱ⁾ to the current timing path ( or to the next timing path (or the next pipeline stage (timing path of pipeline stage (i+1)) that at least partially overlaps with the current pipeline stage (timing path of pipeline stage (i)). The index i is the identifier of the pipeline stage.

In an embodiment, the logic element LC may include a first XOR element XOR1 , a second XOR element XOR2 , a NOR element NOR, and a shared delay circuit SDC. The first XOR element XOR1 receives the inverted signal S3 of the first request signal req ^(i-1) and the output signal S2 (or the second confirmation signal ack ⁽ⁱ⁾ ) to be 0 or 1 can be printed. The second XOR element XOR2 receives the output signal S2 or the second confirmation signal ack ⁽ⁱ⁾ and the third confirmation signal ack ⁽ⁱ⁺ 1) from the pipeline stage (i+1) to receive 0 or 1 can be output. The NOR element NOR may receive the output values of the first XOR element XOR1 and the second XOR element XOR2 and output 0 or 1 . The output value (0 or 1) of the NOR element NOR may be used as a first control signal EN1 for operating or deactivating the first latch element D1. The shared delay circuit SDC is disposed between the output terminal of the first XOR element XOR1 and the input terminal of the NOR element NOR, and delays the output signal of the first XOR element XOR1 to either the input terminal or the second terminal of the NOR element NOR. 2 may be transferred to the latch element D2. At least one buffer or inverter may be serially connected to the shared delay circuit SDC in a chain form. Alternatively, the shared delay circuit SDC may be configured without a buffer or an inverter.

Optionally, the non-shared delay circuit NSDC is connected to the second latch element D2 to delay the output value req ⁽ⁱ⁾ of the second latch element D2 to the timing path of the pipeline stage (i+1). can transmit Similar to the shared delay circuit SDC, the non-shared delay circuit NSDC may include at least one buffer or inverter connected in series in a chain form. Alternatively, the non-shared delay circuit NSDC may be configured without a buffer or inverter.

In one embodiment, the delay of the timing path in pipeline stage (i) is combined with a shared delay circuit (SDC) to ensure a timing constraint that a request signal must not be accepted before receiving valid data in pipeline stage (i). It can be adjusted by the number of buffers or inverters of the non-shared delay circuit (NSDC). If only the shared delay circuit SDC can ensure the timing constraint, the non-shared delay circuit NSDC may be omitted.

In an embodiment, the specific timing constraint of the asynchronous pipeline controller of FIG. 6 satisfies the timing constraint 1 and the timing constraint 2 as follows. Timing constraint conditions 1 and 2 to be described later may be defined by the following <Equation 1> and <Equation 2>, respectively.

Timing constraint 1: When the logical value of the request signal req ^(i-1) flowing into the input of the first latch element D1 in pipeline stage i starts to change, the asynchronous pipeline controller of pipeline stage i temporarily The acknowledgment signal ack ⁽ⁱ⁺¹⁾ MUST NOT change the logical value associated with pipeline stage i until it is in the aborted (steady) state.

In the embodiment of the present invention, (1) the output signals of the first XOR element XOR1 and the second XOR element XOR2 are 'high', (2) the output signal of the NOR is 'low', and (3) the second 1 When the latch element D1 is closed, the asynchronous pipeline controller of pipeline stage i in the suspended (steady) state can be called. This timing constraint 1 may be defined as in Equation 1 below.

<Equation 1>

The left term of <Equation 1> represents the lapse of time between the arrival of the request signal req ^(i-1) and the closing of the first latch element D1, and the right term of <Equation 1> is the confirmation signal ack ^{(i) +1)} represents the time interval until the moment when this enable signal en ⁱ is affected.

Timing constraint 2: When the logical value of the request signal req ^(i-1) flowing into the input of the first latch element D1 in pipeline stage i starts to change, the asynchronous pipeline controller of pipeline stage i temporarily The logic value of the request signal req ^(i-1) must be maintained until the stop (steady) state is reached. This timing constraint 2 may be defined as in Equation 2 below.

<Equation 2>

The left term of <Equation 2> is the same as the left term of <Equation 1>, whereas the right term of <Equation 2> is the time between two consecutive transitions of the request signal req ^(i-1) indicates the elapsed time. There must be no risk to the region shared by the timing path that is maintained when timing constraint 2 is met. Furthermore, the data signal q ⁱ _f is transmitted to the second latch element D2 before the fall of the enable signal en ^i→(i+1) in order to prevent an invalid transfer of the request signal req ^(i-1) . should not arrive Similarly, the data signal q ⁱ _f or the confirmation signal ack ⁱ must arrive before en ^{i → (i+1)} rises to the second latch element D2.

In <Equation 1> and <Equation 2>, req ^(i-1) is a request signal flowing from pipeline stage i-1, and ack ⁽ⁱ⁺¹⁾ is input from pipeline stage i+1 , w ⁱ _xoru is the output signal of the first XOR element (XOR1) of pipeline stage i, w ⁱ _xorl is the output signal of the second XOR element (XOR2) of pipeline stage i, en ⁱ is is a control signal for enabling or disabling the first latch element D1 of pipeline stage i, en ^i→(i+1) is a control signal for enabling or disabling the second latch element D2 of pipeline stage i, and , qn ⁱ _f is an inverted output signal of the first latch element D1 , q ⁱ _f is an output signal of the first latch element D1 , and q ⁱ _r is an output signal of the second latch element D2 .

In addition, the asynchronous pipeline controller used in the asynchronous pipeline circuit in the embodiment of the present invention must satisfy Equation 3 and Equation 4 below.

<Equation 3>

<Equation 4>

In <Equation 3> and <Equation 4>, w ⁽ⁱ⁺¹⁾ _xoru is the output signal of the first XOR element XOR1 of the pipeline stage i+1, and en ^{(i+1)→( i+2)} is a control signal for enabling or disabling the second latch element D2 of the pipeline stage i+1, and en ⁽ⁱ⁺¹⁾ is the first latch element D1 of the pipeline stage i+1 a control signal to enable or disable, D _L ⁽ⁱ⁺¹⁾ is the propagation delay of the enable signal falling in the pipeline stage i+1, D ⁱ _L is the propagation delay of the enable signal falling in the pipeline stage i , where T ⁱ _C is the enable-to-Q delay of the pipeline register in pipeline stage i, D ⁱ _P is the delay of the datapath in pipeline stage i, and T _S ⁽ⁱ⁺¹⁾ is the pipeline stage i is the setup time of the pipeline register at +1, and T _h ⁽ⁱ⁺¹⁾ is the hold time of the pipeline register at pipeline stage i+1.

7 is an i-th timing path (PATH1, red line) of an i-th pipeline stage and an i+1-th timing path ( ) of an i+1th pipeline stage in a circuit having an asynchronous pipeline structure according to an embodiment of the present invention; PATH2, blue line) is a diagram for explaining the overlapping area.

Referring to FIG. 7 , the request signal req ⁽ⁱ⁾ may be transmitted to the i+1th pipeline stage through the timing path PATH1 of the i-th pipeline stage. Specifically, the request signal req ⁽ⁱ⁾ may be delayed delivered to the i+1th pipeline stage through the shared delay circuit SDC and the non-shared delay circuit NSDC of the i-th pipeline stage.

Further, the request signal req ⁽ⁱ⁾ passes once through the shared delay circuit SDC of the i+1th pipeline stage along the timing path PATH1 , where the first latch of the i+1th pipeline stage Although the device D1 is 'enable', the request signal req ⁽ⁱ⁾ output from the first latch device D1 is generated by the second latch device D2 in the 'disable' state in the i+1th pipeline stage. It is not passed to the shared non-delay circuit (NSDC). However, the request signal req ⁽ⁱ⁾ passes through the shared delay circuit SDC of the i+1th pipeline stage twice by the inverted signal of the first latch element D1.

In one embodiment, the overlap region of the i-th timing path (red line) and the i+1-th timing path (blue line) is the shared delay circuit (SDC) and the shared delay circuit (SDC) of the i+1th pipeline stage and It can be defined as a connected XOR element. Since the request signal req ⁽ⁱ⁾ passes at least two times or more in this overlapping region, it is possible to replace the delay of the conventional non-shared delay circuit (NSDC) for ensuring the timing limitation to some extent, and thereby, the non-shared delay The number of delay buffers of the circuit NSDC may be reduced.

8 is a waveform showing the timing of an asynchronous pipeline controller according to an embodiment of the present invention. Here, the asynchronous pipeline controller will be described as the asynchronous pipeline controller of FIG. 6 as an example.

Referring to FIG. 8 , the i-th asynchronous pipeline controller receives an acknowledgment signal ack ^{(i+1) from} the i+1-th asynchronous pipeline controller, and a request signal req (req ^{( i-1)} ) can be received. Here, any one of the acknowledgment signal ack ⁽ⁱ⁺¹⁾ and the request signal req ^(i-1) may first be transmitted to the i-th asynchronous pipeline controller or may be simultaneously transmitted regardless of the order. In FIG. 8 , the acknowledgment signal ack ⁽ⁱ⁺¹⁾ is transmitted to the i-th asynchronous pipeline controller and then the request signal req ^(i-1) is transmitted to the i-th asynchronous pipeline controller.

First, when the acknowledgment signal ack ⁽ⁱ⁺¹⁾ transmitted from the i+1th asynchronous pipeline controller transitions from '1' to '0', the second XOR element (XOR2) of the i-th asynchronous pipeline controller The output signal w ⁱ _xorl of is transitioned from '1' to '0'. In addition, when the request signal req ^(i-1) transmitted from the i-1th asynchronous pipeline controller transitions from '0' to '1', the first XOR element XOR1 of the i-1th asynchronous pipeline controller The output signal w ⁱ _xoru of is transitioned from '1' to '0'. At this time, the first latch element D1 of the i-th asynchronous pipeline controller transitions to '1', and accordingly, the output signal w ⁱ _xoru of the first XOR element XOR1 changes from '0' to '1'. become a cloth Here, the output signal w ⁱ _xoru of the first XOR element XOR1 is a control signal en ^i→(i+1) for switching the second latch element D2 of the i-th asynchronous pipeline controller to enable or disable. ), and is delayed by a predetermined time through the shared delay circuit (SDC) of the i-th asynchronous pipeline controller, so that the output signal w ⁱ _xoru is delay-shifted as shown in FIG. 8 and the control signal en ^{i→( i+1)} ) may appear.

In addition, as the output signal w ⁱ _xoru of the first XOR element XOR1 is delayed from '0' to '1' and transitioned, the control signal en ^{i → (i+1)} ' from '1' to ' Before the transition to 0', the control signal en ⁱ of the first latch element D1 may transition to '1' as shown in FIG. 8 . In addition, the output signal w ⁱ _xorl of the second XOR element XOR2 transitions from '0' to '1' by the control signal en ⁱ of the first latch element D1 . At this time, the output signal w ⁱ _xorl of the second XOR element XOR2 is aligned at the transition point from '0' to '1', and the output signal w ⁱ _xoru of the first XOR element XOR1 is '0' transitions from '1' to '1'. At this time, the output signal w ⁱ _xoru of the first XOR element XOR1 changes from '0' to '1', and the output signal w ⁱ _xorl of the second XOR element XOR2 changes from '0' to '1' At the time of transition to , the control signal en ⁱ of the first latch element D1 is triggered from '1' to '0', and after a predetermined time delay (Delay of SDC), the control signal en ^{i → (i +1)} ) transitions from '0' to '1'.

In addition, when the control signal en ⁱ of the first latch element D1 is transitioned to '1', an acknowledgment signal ack ⁽ⁱ⁾ from the i-th asynchronous pipeline controller is output, and the control signal en ^{i →(i+1)} ), the request signal req ⁽ⁱ⁾ from the i-th asynchronous pipeline controller may be output by being aligned at the transition point from '0' to '1'. Here, the request signal req ⁽ⁱ⁾ may be enabled-to-Q-delayed by a delay of the output signal of the second latch element D2 by a predetermined time. Also, the request signal req ⁽ⁱ⁾ may be transmitted to the i+1th asynchronous pipeline controller through the non-shared delay circuit NSDC of the i-th asynchronous pipeline controller. req ⁽ⁱ⁾ Before NSDC is aligned at the time of transition from '0' to '1' of the control signal (en ^i→(i+1) ), and the request signal (req ⁽ⁱ ) output from the i-th asynchronous pipeline controller) ⁾ ), and req ⁽ⁱ⁾ after NSDC is a signal that the request signal req ⁽ⁱ⁾ is output through the non-shared delay circuit (NSDC) of the i-th asynchronous pipeline controller.

9 is a diagram for explaining a logical operation of an asynchronous pipeline controller according to an embodiment of the present invention. Here, the asynchronous pipeline controller will be described as the asynchronous pipeline controller of FIG. 6 as an example.

Referring to FIG. 9 , the asynchronous pipeline controller includes a logic state A (state A) and a logic state B (state B), and the transition between the logic state A and the logic state B is performed by input of a request signal and a confirmation signal. can work It is assumed that the initial values of req ^(i-1) , ack ⁽ⁱ⁾ , req ⁽ⁱ⁾ , and ack ⁽ⁱ⁺¹⁾ are 0, 0, 0, and 1, respectively. req ^(i-1) is the request signal transmitted from the previous asynchronous pipeline controller, ack ⁽ⁱ⁾ and req ⁽ⁱ⁾ are the acknowledgment and request signals output from the current asynchronous pipeline controller, respectively, and ack ^{(i+) 1)} is the confirmation signal from the next asynchronous pipeline controller.

Looking at the logic operation of the asynchronous pipeline controller, after req ^(i-1) transitions to '1' in logic state A, ack ⁽ⁱ⁺¹⁾ transitions to '0' or ack ⁽ⁱ⁺¹⁾ becomes '0'', req ^(i-1) may transition to '1'. First, when req ^(i-1) is input as '1', it is transmitted to the first XOR element XOR1 and the output value of the first XOR element XOR1 is changed to '0', and the first XOR element XOR1 An output value of may be transmitted to the NOR element and the second latch element D2 ( 100 ). At this time, regardless of the '1' input of req ^(i-1) , the NOR element NOR, the second XOR element XOR2, and the first latch element D1 and the second latch element D2 display the current state. maintain. Thereafter, when ack ⁽ⁱ⁺¹⁾ is input as '0', the output value of the second XOR element XOR2 is changed from '1' to '0' (110).

On the other hand, when ack ⁽ⁱ⁺¹⁾ is first input as '0', it is transmitted to the second XOR element XOR2, and the output value of the second XOR element XOR2 is changed to '0', and the second XOR element XOR2 ) may be transmitted to the NOR element ( 105 ). At this time, regardless of the '0' input of ack ⁽ⁱ⁺¹⁾ , the NOR element NOR, the first XOR element XOR1, and the first latch element D1 and the second latch element D2 display the current state. maintain. Thereafter, when req ^(i-1) is input as '1', it is transmitted to the first XOR element XOR1 and the output value of the first XOR element XOR1 is changed to '0', and the first XOR element XOR1 ) may be transmitted to the NOR element and the second latch element D2 ( 115 ). Considering the states of 110 and 115, it can be confirmed that the operation can be performed without malfunction even in a collision between the request signal and the confirmation signal.

In an embodiment, in step 110 or 115, all input values of the NOR element NOR become '0', so that the output value of the NOR element NOR transitions to '1', and the output value of the NOR element NOR becomes '1'. enables the first latch element D1. At this time, as in step 120, the first latch element D1 may output '1', and the output value '1' of the first latch element D1 is output as a confirmation signal ack ⁽ⁱ⁾ At the same time, it is transmitted to the input terminal of the second XOR element XOR2. In addition, the inverted output value '0' of the first latch element D1 is transmitted to the input terminal of the first XOR element XOR1.

Thereafter, as in step 130, the first XOR element XOR1 converts '1' to the NOR element by the '1' of req ^(i-1) and the inverted output value '0' of the first latch element D1. Output as (NOR). At this time, the output value '1' of the first XOR element XOR1 is delayed and transferred to the NOR element NOR and the second latch element D2. At the same time, the second XOR element XOR2 outputs '1' to the NOR element NOR by the confirmation signal ack ⁽ⁱ ) '1' and the confirmation signal ack ⁽ⁱ⁺¹⁾ '0'. At this time, the NOR element NOR outputs '0' by the output value '1' of the first XOR element XOR1 and the output value '1' of the second XOR element XOR2, and By the output value '0', the first latch element D1 may transition from the operating state to the non-operating state, and the output value '1' of the first XOR element XOR1 does not equal the second latch element D2. By transitioning from the operating state to the operating state, the second latch element D2 may output '1'. The state of step 130 is referred to as logic state B.

In logical state B, after req ^(i-1) transitions to '0', ack ⁽ⁱ⁺¹⁾ transitions to '1' (200, 210) or ack ⁽ⁱ⁺¹⁾ transitions to '1' After req ^(i-1) may be transitioned to '0' (205, 215). First, when req ^(i-1) is input as '0', it is transmitted to the first XOR element XOR1 and the output value of the first XOR element XOR1 is changed to '0', and the first XOR element XOR1 The output value of may be transmitted to the NOR element and the second latch element D2 ( 200 ). At this time, regardless of the '0' input of req ^(i-1) , the NOR element NOR, the second XOR element XOR2, and the first latch element D1 and the second latch element D2 display the current state. maintain. Thereafter, when ack ⁽ⁱ⁺¹⁾ is input as '1', the output value of the second XOR element XOR2 is changed from '1' to '0' ( 210 ).

On the other hand, when ack ⁽ⁱ⁺¹⁾ is first input as '1', it is transmitted to the second XOR element XOR2, and the output value of the second XOR element XOR2 is changed to '0', and the second XOR element XOR2 ) may be transferred to the NOR element ( 205 ). At this time, regardless of the '1' input of ack ⁽ⁱ⁺¹⁾ , the NOR element NOR, the first XOR element XOR1, and the first latch element D1 and the second latch element D2 display the current state. maintain. Thereafter, when req ^(i-1) is input as '0', it is transmitted to the first XOR element XOR1 and the output value of the first XOR element XOR1 is changed to '0', and the first XOR element XOR1 ) may be transmitted to the NOR element and the second latch element D2 ( 215 ). Considering the states of 210 and 215, it can be confirmed that operation can be performed without malfunction even in a collision between the request signal and the confirmation signal.

In an embodiment, in step 210 or 215, all input values of the NOR element NOR become '0', so that the output value of the NOR element NOR transitions to '1', and the output value of the NOR element NOR becomes '1'. enables the first latch element D1. At this time, as in step 220, the first latch element D1 may output '0', and the output value '0' of the first latch element D1 is output as a confirmation signal ack ⁽ⁱ⁾ and at the same time It is transmitted to the input terminal of the second XOR element XOR2. In addition, the inverted output value '1' of the first latch element D1 is transmitted to the input terminal of the first XOR element XOR1.

Thereafter, as in step 230, the first XOR element XOR1 converts '1' to the NOR element by '0' of req ^(i-1) and the inverted output value '1' of the first latch element D1. Output as (NOR). At this time, the output value '1' of the first XOR element XOR1 is delayed and transferred to the NOR element NOR and the second latch element D2. At the same time, the second XOR element XOR2 outputs '1' to the NOR element NOR by the confirmation signal ack ⁽ⁱ ) '0' and the confirmation signal ack ⁽ⁱ⁺¹⁾ '1'. At this time, the NOR element NOR outputs '0' by the output value '1' of the first XOR element XOR1 and the output value '1' of the second XOR element XOR2, and By the output value '0', the first latch element D1 may transition from the operating state to the non-operating state, and the output value '1' of the first XOR element XOR1 does not equal the second latch element D2. By transitioning from the operating state to the operating state, the second latch element D2 may output '0'. The state of step 230 is referred to as a logic state A.

Operations corresponding to steps 120, 130, 220, and 230 may be performed without an error in order to transmit a '1' state and a '0' state of the request signal and the confirmation signal, respectively, in the timing path.

In another embodiment of the present invention, the shared delay circuit (SDC) and the non-shared delay circuit (NSDC) of the asynchronous pipeline controller of FIG. 6 described above may be designed as shown in FIG. 10 below.

10 is a flowchart illustrating a method of designing a shared delay circuit (SDC) and a non-shared delay circuit (NSDC) of an asynchronous pipeline controller having an asynchronous pipeline structure according to an embodiment of the present invention.

Referring to FIG. 10 , the design sequence is a step of analyzing timing information required for each pipeline step ( S100 ), and analyzing the cycle time characteristics of each step based on the timing analysis result of each pipeline step. In consideration of the analysis results of steps S110 and S110, modeling the minimum expected area of the delay circuit according to the delay to be implemented in each step (S120), using the modeling to minimize the total area of the asynchronous pipeline controller It may include determining a delay value to be implemented with each delay circuit ( S130 ) and determining a delay circuit structure and the number of delay buffers based on the determined delay value ( S140 ). As a result, the logic synthesis of the asynchronous pipeline controller based on the two-phase bundled data protocol having a minimum area can finally be completed.

In an embodiment, in operation S110 , a cycle time of each pipeline stage may be estimated from a target delay calculated in timing analysis of a corresponding data path after logic synthesis is completed for each pipeline stage.

In step S120, for each target propagation delay sample, all possible delay circuits may be generated from partial linear modeling between the target delay and the area-minimal delay circuit implementation. Because the minimum retention times of the shared delay circuit (SDC) and non-shared delay circuit (NSDC) are different, it is possible to construct a partial linear model for SDC and NSDC in the entire pipeline stage. Except for implementing a simple delay buffer chain, the above-mentioned timing constraints must be satisfied to synthesize the delay circuit. Therefore, the minimum number of delay buffers required in each layer of the delay circuit while satisfying all constraints to synthesize a plurality of delay circuits for a given minimum retention time ⁰ and target delay d _target is calculated using Equation 5 below can be calculated

<Equation 5>

Here, n _l represents the number of delay buffers in the L layer and d _margin represents the modeling margin.

Δ ^L is the minimum retention time of the L-layer, d _target is the target delay, w ^DPU _l-xoru is the output signal of the first XOR element (XOR1) of pipeline stage L, en ^DPU _{lr is} pipeline stage L is a control signal for _enabling or ^disabling the second ^latch element _D2 of The inverted output signal of (D1), signa _in of the pipeline stage is the input signal, and signal _out is the output signal of the pipeline stage.

In an embodiment, in step S130 , the delay allocation for the delay circuit may be determined by Equation 6 below with reference to the partial linear model.

<Equation 6>

Here, Area ⁱ _S and Area ⁱ _NS are mapping functions of the minimum area delay circuit of pipeline stage i for SDC and NSDC, respectively. ε is a value to prevent inconsistency of the gate delay model, Delay ⁱ is the delay of pipeline stage i, Cycle ^i. is the cycle time of pipeline stage i. w ⁱ _xoru is the output signal of the first XOR element (XOR1) of pipeline stage i, w ⁱ _xorl is the output signal of the second XOR element (XOR2) of pipeline stage i, en ⁱ is the output signal of pipeline stage i is a control signal for enabling or disabling the first latch element D1, en ^i→(i+1) is a control signal for enabling or disabling the second latch element D2 of pipeline stage i, qn ⁱ _f is an inverted output signal of the first latch element D1 , q ⁱ _f is an output signal of the first latch element D1 , and q ⁱ _r is an output signal of the second latch element D2 .

In one embodiment, in step S140, the solution of <Equation 6> is once again obtained with the delay values assigned to all delay circuits generated by the solution of <Equation 5>, and the pipeline controller of the minimum total area synthesis can be completed.

It is common in the art to which the present invention pertains that the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and that various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those who have knowledge.

Claims (27)

A delay circuit for delaying an input signal, comprising:
The delay circuit is
at least one delay unit providing a delay path; and
at least one logic element connected to the at least one delay unit,
When a transition of the input signal occurs, the logic element performs a logical operation for repeatedly passing the input signal through at least two times to reuse the delay path. The method of claim 1,
The logic element is
a first latch element having a first input terminal for receiving the input signal, a first output terminal for outputting the input signal, and a second output terminal for inverting and outputting the input signal;
a second latch element connected to the first output terminal of the first latch element and having a first input terminal for receiving the input signal passing through the first latch element and an output terminal for outputting the input signal; and
disabling the second latch element while enabling the first latch element at a first time point, and disabling the second latch element while disabling the first latch element at a second time point later than the first time point and a control unit enabling the input signal to pass through the at least one delay unit at least two times without collision. 3. The method of claim 2,
The control unit is
a first XOR element that outputs 0 or 1 to the input signal and an inverted input signal from a second output terminal of the first latch element;
a second XOR element configured to output 0 or 1 to an input signal output from a first output terminal of the first latch element and an input signal outputted from an output terminal of the second latch element; and
and a NOR element for enabling or disabling the first latch element by outputting 0 or 1 to the output signal of the first XOR element and the output signal of the second XOR element as inputs;
The delay unit is disposed between the output terminal of the first XOR element and the first input terminal of the NOR element, and delays the output signal of the first XOR element, the first input terminal of the NOR element and the second input terminal of the second latch element A delay circuit that passes to the input stage. 4. The method of claim 3,
an input terminal of the first XOR element and the second output terminal of the first latch element are connected;
connected to a first input terminal of the second XOR element and a first output terminal of the first latch element, and connected to a second input terminal of the second XOR element and an output terminal of the second latch element;
A delay circuit connected to an output terminal of the NOR element and a second input terminal of the first latch element. 4. The method of claim 3,
An output terminal of the first XOR element is connected to an input terminal of the delay unit, and an output terminal of the delay unit is connected to a first input terminal of the NOR element and a second input terminal of the second latch element;
A delay circuit in which a second input terminal of the NOR element and an output terminal of the second XOR element are connected. The method of claim 1,
The delay unit is a delay circuit in which at least one buffer or inverter is connected in series or without a buffer or inverter in a chain form. The method of claim 1,
When the number of the at least one delay unit is m, the m delay units are electrically connected to each other through the logic element, pass the input signal 2 ^m , 2 ^m-1 ,.., 2 ¹ times to pass the next first Delivered sequentially to the delay unit,
The m-th delay unit passes the input signal twice and transmits it to the m-1 th delay unit, and the m-1 delay unit passes the input signal 2 times. A delay circuit for passing the input signal twice and transferring it to an m-2 delay unit, and passing the input signal through the m-2 delay unit twice and transferring the input signal to an m-3 delay unit. A second asynchronous pipeline controlling a second timing path having a region at least partially overlapping with the first timing path based on a first request signal coming from a first timing path controlled by the first asynchronous pipeline controller As a controller,
and the second asynchronous pipeline controller includes a delay path unit that provides the second timing path so that the first request signal passes through the overlapping region at least twice or more. 9. The method of claim 8,
The delay path unit,
A first latch element having a first input terminal for receiving the first request signal, a first output terminal for outputting a second confirmation signal in response to the first request signal, and a second output terminal for inverting and outputting the second confirmation signal ;
a second latch element having a first input terminal connected to a first output terminal of the first latch element and an output terminal outputting a second request signal in response to a third confirmation signal; and
The second latch element is deactivated while the first latch element is operated at a first time point, and the second latch element is operated while the first latch element is deactivated at a second time point later than the first time point. and a logic circuit for controlling to output the second request signal to a third asynchronous pipeline controller. 10. The method of claim 9,
The logic circuit is
a first XOR element outputting 0 or 1 to the first request signal and the inverted second confirmation signal as inputs;
a second XOR element that outputs 0 or 1 to the second acknowledgment signal and a third acknowledgment signal fed back from the third asynchronous pipeline controller as inputs;
a NOR element that operates or deactivates the first latch element by outputting 0 or 1 to the output signal of the first XOR element and the output signal of the second XOR element; and
a second asynchronous pipe disposed between an output terminal of the first XOR element and a first input terminal of the NOR element, the second asynchronous pipe including a shared delay circuit delaying the output signal of the first XOR element and providing it to a first input terminal of the NOR element line controller. 11. The method of claim 10,
The shared delay circuit is a second asynchronous pipeline controller in which at least one buffer or inverter is connected in series or without a buffer or inverter in a chain form. 11. The method of claim 10,
an input terminal of the first XOR element and a second output terminal of the first latch element are connected;
connected to a first input terminal of the second XOR element and a first output terminal of the first latch element, and connected to a second input terminal and a third timing path of the second XOR element;
a second asynchronous pipeline controller connected to an output terminal of the NOR element and a second input terminal of the first latch element. 11. The method of claim 10,
an output terminal of the first XOR element is connected to an input terminal of the shared delay circuit, and an output terminal of the shared delay circuit is connected to a first input terminal of the NOR element and a second input terminal of the second latch element;
A second asynchronous pipeline controller in which a second input terminal of the NOR element and an output terminal of the second XOR element are connected. 10. The method of claim 9,
Further comprising a non-shared delay circuit connected to the output terminal of the second latch element,
The non-shared delay circuit is a second asynchronous pipeline controller in which at least one buffer or inverter is connected in series or without a buffer or inverter in a chain form. 15. The method of claim 10 or 14,
a second asynchronous pipeline controller wherein the delay of the second timing path is adjusted to a number of buffers or inverters in the shared delay circuit or the non-shared delay circuit. 10. The method of claim 9,
The time interval between the arrival of the first request signal and the non-operation time of the first latch element is less than or equal to the time interval during which the first latch element is operated by the third confirmation signal,
a second asynchronous pipeline controller, wherein the third acknowledgment signal is received from a third asynchronous pipeline controller that controls a third timing path coupled to the second timing path. 10. The method of claim 9,
a second asynchronous pipeline controller, wherein a time interval between the arrival of the first request signal and an inactive time of the first latch element is less than or equal to an interval between first request signals provided from the first timing path. 11. The method of claim 10,
and the overlapping region includes the first XOR element and the shared delay circuit. 9. The method of claim 8,
When the delay path unit includes m delay circuits, the m delay circuits are electrically connected to each other to pass the first request signal 2 ^m , 2 ^m-1 ,.., 2 ¹ times, respectively,
The mth delay circuit is 2 time passing the first request signal to an m-1 delay circuit, and the m-1 delay circuit times the first request signal is passed to the m-2 delay circuit, and the m-2 delay circuit is a second asynchronous pipeline controller passing the first request signal to an m-3 delay circuit. a first latch element coupled with the first timing path, a second latch coupled with the first latch element, controlling a second timing path that at least partially overlaps a first timing path controlled by the first asynchronous pipeline controller a second XOR element connected to a first output terminal of the first latch element, a second XOR element connected to a second output terminal of the first latch element, the first XOR element controlling the first latch element and the second latch element; A logic element comprising: a NOR element connected to one XOR element and an output terminal of the second XOR element and connected to an input terminal of the first latch element; and a shared delay circuit disposed between an output terminal of the first XOR element and an input terminal of the NOR element; In the control method of the second asynchronous pipeline controller consisting of:
receiving a first request signal via the first timing path;
transitioning the first latch element to an enabled state in response to the first request signal;
transitioning the first latch element from the enabled state to the disabled state and transitioning the second latch element to the enabled state in response to an inverted output signal of the first latch element in the enabled state; and
and outputting a second request signal through the second latch element. 21. The method of claim 20,
and receiving a third acknowledgment signal from a third timing path that at least partially overlaps the second timing path and is controlled by a third asynchronous pipeline controller. 21. The method of claim 20,
Transitioning the first latch element to an enabled state in response to the first request signal includes:
first activating the first XOR element based on the first request signal and an inverted signal from a second output terminal of the first latch element;
first activating the second XOR element based on an output signal from a first output terminal of the first latch element and a third confirmation signal transmitted from a third timing path;
first activating a NOR element based on output signals of the first XOR element and the second XOR element; and
and enabling the first latch element by an output signal of the NOR element. 21. The method of claim 20,
Transitioning the first latch element from the enabled state to the disabled state and transitioning the second latch element to the enabled state in response to an inverted output signal of the first latch element in the enabled state;
second activating the first XOR element based on an inverted output signal of the first latch element in the enabled state and the first request signal; and
and enabling the second latch element by an output signal of the first XOR element. 24. The method of claim 23,
second activating the second XOR element based on an output signal of the first latch element and a third confirmation signal transmitted from a third timing path;
activating a second NOR element based on output signals of the first XOR element and the second XOR element; and
and disabling the first latch element by an output signal of the NOR element. 24. The method of claim 23,
The output signal of the first XOR element is delayed and transferred to the input terminal of the NOR element and the input terminal of the second latch element through the shared delay circuit. 24. The method of claim 23,
A second confirmation signal corresponding to the second request signal is provided to the second latch element D2 before the enable signal provided to the second latch element D2 falls so as to prevent abnormal transmission of the first request signal. A method of controlling a second asynchronous pipeline controller that does not arrive at the first input of the second asynchronous pipeline controller, but arrives at the first input of the second latch element (D2) before the enable signal rises. An asynchronous pipeline circuit consisting of n pipeline stages,
Each pipeline stage is
a data latch providing a data path; and
9. An asynchronous pipeline circuit comprising the asynchronous pipeline controller of claim 8 to activate or deactivate the data latch.

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