CN104506270B - A kind of temporal frequency synchronous integrated realizes system and implementation method - Google Patents
A kind of temporal frequency synchronous integrated realizes system and implementation method Download PDFInfo
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Abstract
System and implementation method, including time reference input block, frequency reference input block, clock unit, time output unit, frequency output unit, system control unit, power subsystem, fan unit and backboard unit are realized the invention discloses a kind of temporal frequency synchronous integrated；With frequency reference input block be combined time reference input block by the present invention, the alarm of whole equipment, input/output state, performance parameter are inquired about and configuration management by system control unit, realize synchronous and Frequency Synchronization the function of time of fusion simultaneously, for user's networking provides great convenience and reduces networking cost, it is possible to the flexible requirement for meeting the different user demand different with Frequency Synchronization to the time.
Description
Technical field
The invention belongs to temporal frequency simultaneous techniques field, and in particular to a kind of temporal frequency synchronous integrated realizes system
And implementation method.
Background technology
In the communications industry, the synchronization to temporal frequency always has requirement higher.It was in the past the demand to Frequency Synchronization,
Now with the development of 3G/4G technologies and ripe, the also development of various emerging technologies such as synchronous ethernet, necessary not only for frequency
It is synchronous, also there is requirement higher to time synchronized.
At present, in the market Frequency Synchronization and time synchronized are nearly all 2 kinds of separate equipment, user to realize frequency and when
Between if synchronization, just must simultaneously purchase 2 kinds of equipment, and be respectively connected in system, it is relatively costly thus to there is networking, safeguards
Difficulty, the maintenance cost also defect such as higher.With advances in technology with the demand in market, current 2 kinds of synchronizers combine together
Trend it is apparent, single complete equipment meets user to time and the integration requirement of Frequency Synchronization simultaneously, is also user
Networking is provided and greatly facilitates and reduce networking cost, it is possible to flexibly meet different user to time and Frequency Synchronization
The requirement of different demands.
The content of the invention
It is an object of the invention to solve the above problems, there is provided a kind of temporal frequency synchronous integrated realizes system and realization
Method, the system can simultaneously realize the time synchronized and Frequency Synchronization of single device.
To achieve these goals, used technical scheme of the invention is：
A kind of temporal frequency synchronous integrated realizes system, including time reference input block, frequency reference input block,
Clock unit, time output unit, frequency output unit, system control unit, power subsystem, fan unit and backboard list
Unit；
Time reference input block is used to receive the input of timing reference signal；
Frequency reference input module is input into for receives frequency reference signal；
Clock unit is used to receive the reference signal of temporal frequency reference input unit, and these signals are filtered,
Decoding, frequency discrimination and phase demodulation computing, calculate a split-second precision signal and high accuracy frequency signal, and output to time exports single
Unit and frequency output unit；
Time output unit is used to carry out time synchronizing signal output；
Frequency output unit is used to carry out frequency synchronization signal output；
System control unit is inquired about and matched somebody with somebody for the alarm to whole equipment, input/output state, performance parameter
Put management；
Power subsystem is for system, other units to be powered；
Fan unit is radiated for being responsible for other units to system；
Backboard unit is used to provide physical connection to system unit, at the same backboard unit also for time output unit and
The 1+1 protection output function of frequency output unit provides corresponding hardware interface.
The time reference input block receives time reference by the way of MAX3232ESE chips and RJ45 sockets
Signal input.
The frequency reference input module is by the way of DS26303 chips and CC4 coaxial heads come receives frequency with reference to letter
Number input.
The clock unit is made up of S3C2440, XC3S700AN and high accuracy rubidium clock.
The time output unit carries out time synchronizing signal by the way of MAX3232ESE chips and RJ45 sockets
Output.
The frequency output unit carries out frequency synchronization signal output by the way of DS26303 and CC4 sockets.
The system control unit is made up of S3C2440, XC3S250E, XC95144XL and RTL8201CP.
Computer management software is communicated by Ethernet with system control unit, realize to the alarm of whole equipment,
Input/output state, performance parameter are inquired about, configuration management；
Wherein, S3C2440 is master cpu, for the collection to whole equipment information and is issued；
XC3S250E is used to carry out hardware detection to the information of each functional unit, and is reported to CPU；
XC95144XL is used to be extended the I/O of XC3S250E；
RTL8201CP uploads to computer management software for the information of CPU to be converted into ethernet signal.
A kind of temporal frequency synchronous integrated implementation method, comprises the following steps：
1) time signal outside the reception of time reference input block, and time signal is decoded, generation time ginseng
Examine 1PPS signals and TOD signals, output to clock unit；
2) the 2MBit signals and 2MHz signals outside the reception of frequency reference input block, frequency reference is produced by dividing
1PPS signals, output to clock unit；
3) rubidium clock of clock unit produces 10MHz signals, by 10MHz signal generation systems 1PPS；
4) when system only has frequency reference 1PPS signal inputs, system 1PPS signals directly with frequency reference 1PPS signals
Carry out phase demodulation and produce original phase demodulation data；When system only has time reference 1PPS signal inputs, system 1PPS signals directly with
Time reference 1PPS signals carry out phase demodulation and produce original phase demodulation data；When the existing time reference 1PPS signal inputs of system, have again
During frequency reference 1PPS signal inputs, system 1PPS signals will be determined and time reference 1PPS signals according to the configuration of host computer
Or phase demodulation computing is carried out with frequency reference 1PPS signals and produces original phase demodulation data；
5) after clock unit carries out medium filtering to original phase demodulation data, according to filtered phase demodulation data to the frequency of rubidium clock
Rate is adjusted.
The step 5) in, specific adjustment algorithm is as follows：
Init state Init is in when 5-1) device power starts, after detecting the equal normal work of each functional module,
Into hold mode Hold；
5-2) after rubidium clock work is ready, equipment enters catches state Fasttrack soon, can be according to mirror status system is caught soon
Mutually value carries out the adjustment of larger step size to rubidium clock so that the 1PPS output accuracies of system are within 400ns；It was when continuous 10 minutes
After the 1PPS precision of system is better than 400ns, equipment can enter following 4 kinds of states according to current tracking mode：Quadrant1、
Quadrant2, Quadrant3 and Quadrant4, this 4 kinds of states correspond to 4 quadrants of SIN function respectively；
5-3) system is just changed successively in this 4 kinds of states：
Quadrant1→Quadrant2→Quadrant3→Quadrant4→Quadrant1
Wherein, both states of Quadrant2 → Quadrant3 and Quadrant4 → Quadrant1 are referred to as system zero passage
Point, corresponding phase point is 0 and π, and in zero crossing, rubidium clock adjustment amount reduces ratio than the last linear reduction of adjustment amount
Example constant is corresponding with the performance of rubidium clock, and the output 1PPS phases of system are just presented damped oscillation, within final stabilization ± 50ns.
With frequency reference input block be combined time reference input block by the present invention, by system control unit to whole
The alarm of individual equipment, input/output state, performance parameter are inquired about and configuration management, realize time of fusion synchronization simultaneously
With the function of Frequency Synchronization, networking cost is greatly facilitated and reduced for user's networking is provided, it is possible to flexible to meet
The requirement of the different user demand different with Frequency Synchronization to the time.Backboard unit of the present invention directly exports the 1PPS+TOD times
Signal and 10MHz frequency signals, for time output board card, 1PPS+TOD signals are directly converted into the form for needing
Output.For rate-adaptive pacemaker board, then the board composition protection group output of two neighboring groove position, two plates in a protection group
Card locks same 1PPS signals simultaneously, while also mutually send monitoring signals between board, such output frequency of the two boards
It is just completely the same with phase, meet YD/T 1479-2006 national standards.
Brief description of the drawings
Fig. 1 is logical construction block diagram of the invention；
Fig. 2 is state transition diagram of the invention.
Specific embodiment
Technical scheme is described further below in conjunction with the accompanying drawings
As shown in figure 1, the present invention is a kind of logic diagram of temporal frequency synchronous integrated implementation.The program is by such as
Lower unit is constituted：Time reference input block, frequency reference input block, clock unit, time output unit, rate-adaptive pacemaker list
Unit, system control unit, power subsystem, fan unit, backboard unit.
Time reference input block is defeated to receive timing reference signal by the way of MAX3232ESE chip+RJ45 sockets
Enter.
Frequency reference input module is defeated come receives frequency reference signal by the way of DS26303 chip+CC4 coaxial heads
Enter.
Clock unit is the core of this programme.Clock unit is by S3C2440+XC3S700AN+ high accuracy rubidium clock groups
Into.The main reference signal for being responsible for receiving temporal frequency reference input unit, and these signals are filtered, decode, frequency discrimination,
The digital operations such as phase demodulation, calculate a split-second precision signal and high accuracy frequency signal, output to time output unit and
Frequency output unit.
Time output unit carries out time synchronizing signal output by the way of MAX3232ESE chip+RJ45 sockets.
Frequency output unit carries out frequency synchronization signal output by the way of DS26303+CC4 sockets.
System control unit is made up of S3C2440+XC3S250E+XC95144XL+RTL8201CP.Computer management software
Communicated with system control unit by Ethernet, realized that the alarm to whole equipment, input/output state, performance parameter are entered
Row inquiry, configuration management.Wherein S3C2440 is master cpu, is responsible for the collection of whole equipment information and issues, XC3S250E
Information to each functional unit carries out hardware detection, and is reported to CPU.XC95144XL is that the I/O of XC3S250E is expanded
Exhibition.RTL8201CP is then that the information of CPU is converted into ethernet signal to upload to computer management software.
Power subsystem is responsible for other units to system and is powered.
Fan unit is responsible for other units to system and is radiated.
Backboard unit is then to provide physical connection to system unit, at the same backboard unit also for time output unit and
The 1+1 protection output function of frequency output unit provides corresponding hardware interface.
Workflow of the invention：
Time signal outside the reception of time reference input block, and time signal is decoded, generation time reference
1PPS signals and TOD signals, output to clock unit.
2MBit signals and 2MHz signals outside the reception of frequency reference input block, frequency reference is produced by dividing
1PPS signals, output to clock unit.
The rubidium clock of clock unit produces 10MHz signals, by 10MHz signal generation systems 1PPS.
When system only has frequency reference 1PPS signal inputs, system 1PPS signals directly enter with frequency reference 1PPS signals
Row phase demodulation produces original phase demodulation data；When system only has time reference 1PPS signal inputs, system 1PPS signals directly and when
Between carry out phase demodulation with reference to 1PPS signals and produce original phase demodulation data；When the existing time reference 1PPS signal inputs of system, there is frequency again
When rate refers to 1PPS signal inputs, system 1PPS signals will be determined with time reference 1PPS signals also according to the configuration of host computer
It is to carry out phase demodulation computing with frequency reference 1PPS signals.
After clock unit carries out medium filtering to original phase demodulation data, by according to filtered phase demodulation data to the frequency of rubidium clock
Rate is adjusted, and adjustment algorithm is as follows：
The system is to realize temporal frequency fusion output, should ensure the precision of rate-adaptive pacemaker, and time output is ensured again
Precision, it is therefore desirable to use zero passage detection and damping adjustment technology.The present invention realizes that the state of key component turns using FPGA
Move as shown in Figure 2.
Operation principle is as follows：Init (init state) is in when device power starts, each functional module is detected equal
After normal work, into Hold (hold mode), this is therefore electric this section on just because rubidium clock normal working temperature is 60 DEG C
Time needs heating about 10 minutes or so.After rubidium clock work is ready, equipment enters Fasttrack (catching state soon), fast
Catching status system can carry out the adjustment of larger step size according to phase demodulation value to rubidium clock so that the 1pps output accuracies of system are in 400ns
Within.After the 1pps precision of continuous 10 minutes systems is better than 400ns, equipment can enter as follows according to current tracking mode
4 kinds of states:Quadrant1, Quadrant2, Quadrant3, Quadrant4, correspond to 4 quadrants of SIN function respectively.So
System is just changed successively in this 4 kinds of states afterwards：Quadrant1→Quadrant2→Quadrant3→Quadrant4→
Quadrant1.Wherein Quadrant2 → Quadrant3, Quadrant4 → Quadrant1 both states are referred to as system zero passage
Point, corresponding phase point is 0 and π, and in zero crossing, rubidium clock adjustment amount reduces ratio than the last linear reduction of adjustment amount
Example constant is general relevant with the performance of rubidium clock, and the output 1pps phases of such system are just presented damped oscillation, and final stabilization ±
Within 50ns.
Temporal frequency integration output：Backboard unit of the present invention directly exports 1PPS+TOD time signals and 10MHz frequently
Rate signal, for time output board card, the form for directly being converted into needing by 1PPS+TOD signals is i.e. exportable.It is defeated for frequency
Go out board, then the board of two neighboring groove position constitutes the output of protection group, and two boards in a protection group lock same simultaneously
Individual 1PPS signals, while also mutually sending monitoring signals between board, so the output frequency and phase of the two boards are with regard to complete one
Cause, meet YD/T 1479-2006 national standards.
Above content is only explanation technological thought of the invention, it is impossible to limit protection scope of the present invention with this, every to press
According to technological thought proposed by the present invention, any change done on the basis of technical scheme each falls within claims of the present invention
Protection domain within.
Claims (10)
1. a kind of temporal frequency synchronous integrated realizes system, it is characterised in that：Including time reference input block, frequency reference
Input block, clock unit, time output unit, frequency output unit, system control unit, power subsystem, fan unit with
And backboard unit；
Time reference input block is used to receive the input of timing reference signal；
Frequency reference input module is input into for receives frequency reference signal；
Clock unit is used to receive the reference signal of temporal frequency reference input unit, and these signals are filtered, are decoded,
Frequency discrimination and phase demodulation computing, calculate a split-second precision signal and high accuracy frequency signal, output to time output unit and
Frequency output unit；
Time output unit is used to carry out time synchronizing signal output；
Frequency output unit is used to carry out frequency synchronization signal output；
Pipe is inquired about and configured to system control unit for the alarm to whole equipment, input/output state, performance parameter
Reason；
Power subsystem is for system, other units to be powered；
Fan unit is radiated for being responsible for other units to system；
Backboard unit is used to provide physical connection to system unit, while backboard unit is also time output unit and frequency
The 1+1 protection output function of output unit provides corresponding hardware interface；
The temporal frequency synchronous integrated realizes the implementation method of system, comprises the following steps：
1) time signal outside the reception of time reference input block, and time signal is decoded, generation time reference
1PPS signals and TOD signals, output to clock unit；
2) the 2MBit signals and 2MHz signals outside the reception of frequency reference input block, frequency reference 1PPS is produced by dividing
Signal, output to clock unit；
3) rubidium clock of clock unit produces 10MHz signals, by 10MHz signal generation systems 1PPS；
4) when system only has frequency reference 1PPS signal inputs, system 1PPS signals are directly carried out with frequency reference 1PPS signals
Phase demodulation produces original phase demodulation data；When system only has time reference 1PPS signal inputs, system 1PPS signals are directly and the time
Phase demodulation is carried out with reference to 1PPS signals produce original phase demodulation data；When the existing time reference 1PPS signal inputs of system, there is frequency again
During with reference to 1PPS signal inputs, system 1PPS signals will be determined with time reference 1PPS signals still according to the configuration of host computer
Phase demodulation computing is carried out with frequency reference 1PPS signals and produces original phase demodulation data；
5) after clock unit carries out medium filtering to original phase demodulation data, the frequency of rubidium clock is entered according to filtered phase demodulation data
Row adjustment.
2. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterised in that：The time reference is defeated
Enter unit by the way of MAX3232ESE chips and RJ45 sockets to receive timing reference signal input.
3. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterised in that：The frequency reference is defeated
Enter module and be input into come receives frequency reference signal by the way of DS26303 chips and CC4 coaxial heads.
4. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterised in that：The clock unit by
S3C2440, XC3S700AN and high accuracy rubidium clock are constituted.
5. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterised in that：The time output is single
Unit carries out time synchronizing signal output by the way of MAX3232ESE chips and RJ45 sockets.
6. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterised in that：The rate-adaptive pacemaker list
Unit carries out frequency synchronization signal output by the way of DS26303 and CC4 sockets.
7. temporal frequency synchronous integrated according to claim 1 realizes system, it is characterised in that：The system control is single
Unit is made up of S3C2440, XC3S250E, XC95144XL and RTL8201CP.
8. temporal frequency synchronous integrated according to claim 7 realizes system, it is characterised in that：Computer management software
Communicated with system control unit by Ethernet, realized that the alarm to whole equipment, input/output state, performance parameter are entered
Row inquiry, configuration management；
Wherein, S3C2440 is master cpu, for the collection to whole equipment information and is issued；
XC3S250E is used to carry out hardware detection to the information of each functional unit, and is reported to CPU；
XC95144XL is used to be extended the I/O of XC3S250E；
RTL8201CP uploads to computer management software for the information of CPU to be converted into ethernet signal.
9. a kind of temporal frequency synchronous integrated implementation method that system is realized as described in claim 1-8 any one, it is special
Levy and be, comprise the following steps：
1) time signal outside the reception of time reference input block, and time signal is decoded, generation time reference
1PPS signals and TOD signals, output to clock unit；
2) the 2MBit signals and 2MHz signals outside the reception of frequency reference input block, frequency reference 1PPS is produced by dividing
Signal, output to clock unit；
3) rubidium clock of clock unit produces 10MHz signals, by 10MHz signal generation systems 1PPS；
4) when system only has frequency reference 1PPS signal inputs, system 1PPS signals are directly carried out with frequency reference 1PPS signals
Phase demodulation produces original phase demodulation data；When system only has time reference 1PPS signal inputs, system 1PPS signals are directly and the time
Phase demodulation is carried out with reference to 1PPS signals produce original phase demodulation data；When the existing time reference 1PPS signal inputs of system, there is frequency again
During with reference to 1PPS signal inputs, system 1PPS signals will be determined with time reference 1PPS signals still according to the configuration of host computer
Phase demodulation computing is carried out with frequency reference 1PPS signals and produces original phase demodulation data；
5) after clock unit carries out medium filtering to original phase demodulation data, the frequency of rubidium clock is entered according to filtered phase demodulation data
Row adjustment.
10. temporal frequency synchronous integrated implementation method according to claim 9, it is characterised in that the step 5) in,
Specific adjustment algorithm is as follows：
Init state Init is in when 5-1) device power starts, after detecting the equal normal work of each functional module, is entered
Hold mode Hold；
5-2) after rubidium clock work is ready, equipment enters catches state Fasttrack soon, can be according to phase demodulation value status system is caught soon
The adjustment of larger step size is carried out to rubidium clock so that the 1PPS output accuracies of system are within 400ns；When continuous 10 minutes systems
After 1PPS precision is better than 400ns, equipment can enter following 4 kinds of states according to current tracking mode：Quadrant1、
Quadrant2, Quadrant3 and Quadrant4, this 4 kinds of states correspond to 4 quadrants of SIN function respectively；
5-3) system is just changed successively in this 4 kinds of states：
Quadrant1→Quadrant2→Quadrant3→Quadrant4→Quadrant1
Wherein, both states of Quadrant2 → Quadrant3 and Quadrant4 → Quadrant1 are referred to as system zero crossing,
Corresponding phase point is 0 and π, and in zero crossing, rubidium clock adjustment amount reduces ratio normal than the last linear reduction of adjustment amount
Number is corresponding with the performance of rubidium clock, and the output 1PPS phases of system are just presented damped oscillation, within final stabilization ± 50ns.
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| CN104935329B (en) * | 2015-06-29 | 2018-09-25 | 大唐电信（成都）信息技术有限公司 | A kind of soft reverse method of time synchronism equipment multichannel reference source and system |
| CN109194431B (en) * | 2018-08-13 | 2020-04-21 | 郑州威科姆华大北斗导航科技有限公司 | Clock time-frequency integrated transmission method and device |
| CN110752877B (en) * | 2019-11-04 | 2021-12-07 | 深圳市慧宇系统有限公司 | System and method for transmitting time frequency signal in optical fiber |
| CN112187363B (en) * | 2020-09-18 | 2022-03-08 | 中国科学院上海光学精密机械研究所 | High-precision optical fiber time frequency transmission system and method compatible with Ethernet |
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|---|---|---|---|---|
| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN101686120A (en) * | 2008-09-26 | 2010-03-31 | 大唐移动通信设备有限公司 | Device and method for realizing clock synchronization |
| CN102064827A (en) * | 2010-11-11 | 2011-05-18 | 国网电力科学研究院 | Rubidium oscillator-based standard frequency and time adjusting method |
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2014
- 2014-12-25 CN CN201410829415.XA patent/CN104506270B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN101686120A (en) * | 2008-09-26 | 2010-03-31 | 大唐移动通信设备有限公司 | Device and method for realizing clock synchronization |
| CN102064827A (en) * | 2010-11-11 | 2011-05-18 | 国网电力科学研究院 | Rubidium oscillator-based standard frequency and time adjusting method |
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Effective date of registration: 20180118 Address after: 100094 Yongjia North Road, Haidian District, Haidian District, Beijing, 5 Patentee after: Datang Telecommunication Science & Technology Co., Ltd. Address before: 1800 G District No. 610000 Sichuan city of Chengdu province Yizhou Road 4 6 floor Patentee before: DATANG TELECOM (CHENGDU) INFORMATION TECHNOLOGY CO., LTD. |
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Application publication date: 20150408 Assignee: DATANG TELECOM (CHENGDU) INFORMATION TECHNOLOGY CO., LTD. Assignor: Datang Telecommunication Science & Technology Co., Ltd. Contract record no.: 2019990000003 Denomination of invention: Time and frequency synchronization integration implementation system and method Granted publication date: 20170616 License type: Common License Record date: 20190107 |
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