CN1592134A - Phase alignment method for master and stand-by clocks - Google Patents
Phase alignment method for master and stand-by clocks Download PDFInfo
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- CN1592134A CN1592134A CN 03157802 CN03157802A CN1592134A CN 1592134 A CN1592134 A CN 1592134A CN 03157802 CN03157802 CN 03157802 CN 03157802 A CN03157802 A CN 03157802A CN 1592134 A CN1592134 A CN 1592134A
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Abstract
A phase alignment method for master and standby clocks is that a standby clock locks the master clock or a same reference source with the master clock by a phase detector, a signal processor and a direct frequency synthesizer(DDS) to let the master and standby output the same frequencies. The phase difference judgment is carried out to master and standby clocks to regulate the standby output phase to align their phases, the phase detection value output by the phase detector is compensated based on the phase difference so that the standby output phase regulation does not influence its lock to the reference source.
Description
Technical field
The present invention relates to communication technical field, relate in particular to the phase alignment method of master/backup clock in a kind of communication equipment.
Background technology
Adopt the reliability that main veneer is backed up raising equipment the communication equipment (as SDH Optical synchronization digital transmission system equipment), clock is a very important part for communication equipment, therefore in the design of communication equipment clock, adopted the back-up job mode, in case master clock breaks down, being equipped with the alternative immediately master clock of clock provides timing signal for communication equipment.The switching of active and standby clock will guarantee business do not exert an influence (producing professional hit, error code etc. when for example switching) as far as possible, therefore under any circumstance, must guarantee that when master/backup clock switched, the phase place of master/backup clock was alignd, otherwise equipment will produce error code even service disconnection.
Be illustrated in figure 1 as the basic structure schematic diagram of phase-locked loop (PLL), phase-locked loop is by comparing the phase place of reference clock and loop output clock, and comparative result is used for control loop output, finally reach the constant a kind of control loop of phase relation of reference clock and loop output clock.Form by three basic parts: phase discriminator (PD), loop filter (LPF) and voltage controlled oscillator (VCO).
Phase discriminator is a phase comparison device, and it compares the phase place of the output signal of input clock signal and voltage controlled oscillator, produces the error voltage (pulse) corresponding to two signal phase differences.
The effect of loop filter is to the error pulse integration, and radio-frequency component and noise in the filtering error voltage (pulse), to guarantee the desired performance of loop, increases the stability of system.
Voltage controlled oscillator is subjected to the control of error control voltage, and the frequency of voltage controlled oscillator is drawn close to the frequency of input clock signal, locks until eliminating frequency difference.
Phase-locked loop is a phase error control system, the phase difference between its comparator input signal and the voltage controlled oscillator output signal, thus produce the frequency that error control voltage is adjusted voltage controlled oscillator, to reach and input signal frequency together.When loop is started working, if frequency input signal is different with pressuring controlling oscillator frequency, then owing to have intrinsic difference on the frequency between two signals, the phase difference between them certainly will change always, and the error voltage of phase discriminator output as a result just changes within the specific limits.Under the control of this error voltage, the frequency of voltage controlled oscillator is also changing.If the frequency of voltage controlled oscillator can change to frequency input signal and equate, just on this frequency, settle out satisfying under the stability condition.Reach stable after, the frequency difference between input signal and the voltage controlled oscillator output signal is zero, differs no longer in time to change, error voltage is a fixed value, at this moment loop just enters lock-out state, the roughly process of phase-locked loop operation that Here it is.
Existing clock backup scheme mostly is master clock and adopts digital phase-locked loop track reference source, is equipped with clock and adopts analog phase-locked look to follow the tracks of master clock, and the output clock is alignd with main clock phase.It mainly is in order to guarantee that system clock satisfies the communication equipment relevant criterion that master clock adopts digital phase-locked loop, for example ITU-TG.783 " based on the characteristic of SDH (Synchronous Digital Hierarchy) (SDH) functions of the equipments assembly ", ITU-TG.813 " SDH do not have received shipment capable be suitable for from clock characteristic regularly " etc. regulation, can make clock work in various mode of operations, for example follow the tracks of, maintenance, free oscillation etc., and be beneficial to the regulation that realizes among the ITU-TG.813 about performance.And be equipped with clock employing analog loop mainly is for the consideration that master/backup clock is differed, and the analog phase-locked look residue differs comparatively constant, and high conformity is being equipped with the time-delay of clock or master clock adjusted, can reach active and standby clock output phase alignment.
In existing clock scheme, the process of rearranging main/slave clock is that the digital phase-locked loop of current mainboard switches to analog phase-locked look, follows the tracks of the plate clock; Current slave board switches to digital phase-locked loop by analog phase-locked look, the track reference source.Suppose to have two boards A and B, acquiescence A is a mainboard when powering on, if the A plate breaks down, causes taking place masterslave switchover, and the A plate becomes slave board from mainboard, and the B plate becomes mainboard by slave board.Process prescription is as follows: beginning A plate is with digital phase-locked loop track reference source (in order to guarantee various mode of operations), the B plate is followed the tracks of A plate output clock (the analog phase-locked look residue differs fixing, aligns with the A plate through the clock phase that can guarantee the output of B plate after the time-delay) with analog phase-locked look; Switch back B plate and use digital phase-locked loop track reference source, the A plate is followed the tracks of B plate output clock with analog phase-locked look.Like this, in the process of switching digital phase-locked loop and analog phase-locked look, be easy to generate phase transient (being that the clock phase place is discontinuous), occur phenomenons such as error code when causing masterslave switchover.
The digital phase-locked loop residue differs unfixing, and the residue of analog phase-locked look differs less, high conformity, if and master/backup clock uses digital phase-locked loop to follow the tracks of same road reference source simultaneously, can't guarantee the alignment of master/backup clock output clock phase so, occur phenomenons such as error code when finally causing masterslave switchover.
The VCXO of available technology adopting constant temperature, the circuit complexity, element is many, causes crystal oscillator cost height, and reliability is lower.And if existing scheme enters the maintenance pattern in very short time after masterslave switchover takes place, clock board will be difficult to satisfy among the ITU-T about keeping the regulation of performance because of keeping data deficiencies.
Summary of the invention
Technical problem to be solved by this invention is: is prone to deficiencies such as error code when overcoming communication equipment clock generation masterslave switchover such as current SDH, a kind of method of main clock phase alignment is provided, thus the generation of error code when avoiding masterslave switchover.
The present invention solves the problems of the technologies described above the technical scheme that is adopted to be:
The phase alignment method of this master/backup clock may further comprise the steps:
Be equipped with the clock tracing master clock or follow the tracks of same reference source, make master/backup clock output frequency unanimity with master clock;
Master/backup clock is differed judgement, be equipped with the adjustment of clock output phase, make the main clock phase alignment according to master/backup clock phase difference.
When clock and master clock are followed the tracks of same reference source fully, according to described master/backup clock phase difference the phase demodulation value that is equipped with clock and reference source is compensated, the adjustment of clock output phase is not fully influenced be equipped with the locking of clock the reference source frequency.
Be equipped with clock and pass through phase discriminator, signal processor and direct synthesizer (DDS) are followed the tracks of master clock or are followed the tracks of same reference source with master clock, described phase discriminator compares the phase difference between DDS output clock and master clock or the reference source, this phase difference is carried out digitlization, differing after the digitlization sent into and carried out Digital Signal Processing in the signal processor, data after signal processor will be handled are converted to frequency control word and output to DDS, be converted into the clock of corresponding frequencies by DDS, making master clock or reference source and DDS output clock is a steady state value at the phase difference of phase discriminator input port, makes output clock frequency locking master clock or reference source.
Employing differs decision circuitry master/backup clock is differed judgement, master/backup clock is differed report described signal processor, by the phase control words of signal processor modification DDS, adjusts clock output phase fully, makes the main clock phase alignment.
Employing differs decision circuitry master/backup clock is differed judgement, master/backup clock is differed report described signal processor, by the time-delay of signal processor by the control valve foot control system delay chip of delay chip, makes the phase alignment of master/backup clock.
The adjustment amount of main clock phase alignment can be the phase difference of master/backup clock or the stepping amount of fixed step size or variable step.
Described signal processor adopts digital signal processor (DSP) or microprocessor or programmable logic device to realize.
When clock and master clock are followed the tracks of same reference source fully, under free oscillation or maintenance pattern, master/backup clock works in free oscillation or the maintenance pattern of oneself separately, the active and standby phase alignment part of master clock is not worked, the active and standby phase alignment that is equipped with clock is partly worked, and guarantees to be equipped with the clock output phase and aligns with the master clock output phase all the time.
Beneficial effect of the present invention is: the present invention is equipped with clock and locks same reference source by phase discriminator, signal processor and direct synthesizer (DDS) locking master clock or with master clock, makes master/backup clock output frequency unanimity; And carry out master/backup clock and differ judgement by differing decision circuitry, be equipped with the adjustment of clock output phase according to master/backup clock phase difference, make the main clock phase alignment; For not influenced, the adjustment of clock output phase fully is equipped with the locking of clock to the reference source phase place, in signal processor, phase discriminator output phase demodulation value is compensated according to master/backup clock phase difference, the present invention has realized the phase alignment of master/backup clock like this, and does not influence slave board locking reference source.Utilize the present invention, master/backup clock is followed the tracks of same reference source simultaneously, has improved the reliability and the flexibility of equipment, and the main clock phase alignment does not provide necessary condition for equipment has the error code masterslave switchover.
The present invention can adopt and decide the frequency crystal oscillator owing to the design feature of DDS itself, and the number of elements in the crystal oscillator reduces at this moment, the corresponding increase of the reliability of crystal oscillator, and cost also reduces, and has improved the reliability of equipment.And the present invention can lock reference source by active and standby plate simultaneously, independently keeps data separately so active and standby plate has, and the masterslave switchover backup board can enter the maintenance pattern immediately, can can't not pass through because of keeping data deficiencies among the ITU-T about keeping the regulation of performance.
Description of drawings
Fig. 1 is a phase-locked loop basic structure schematic diagram;
Fig. 2 is main clock phase alignment scenario-frame schematic diagram of the present invention;
Fig. 3 is a phase adjusted schematic diagram of the present invention.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
The present invention differs the phase-locked and phase alignment system that decision circuitry is formed jointly by digital phase discriminator, DDS (direct synthesizer), DSP (digital signal processor), master/backup clock, guarantee that the master/backup clock output frequency locks same road reference source, be equipped with clock phase locking main clock phase.The filter circuit that digital signal processor (DSP) also can adopt microprocessor or programmable logic device to realize.
As shown in Figure 1, be equipped with clock and lock same road reference source, be equipped with clock simultaneously by differing decision circuitry and master clock differs comparison by digital phase discriminator, DDS, DSP and master clock, and by DSP and DDS realization phase alignment.If the communication equipment clock work is in the master clock mode of operation, then the circuit of dotted portion is not worked; When the communication equipment clock work when being equipped with clock module, the dotted portion circuit will participate in phase-locked.The phase-locked loop that the outer part of dotted line constitutes can be described as main phase-locked loop, and dotted portion can be described as secondary phase-locked loop.Main phase-locked loop partly is made of the FREQUENCY CONTROL of digital phase discriminator, DSP, DDS, and secondary phase-locked loop is made of the phase control part that master/backup clock differs decision circuitry, DDS.
Phase discriminator compares the phase difference between DDS output clock and the reference source, this phase difference is carried out digitlization, differing after the digitlization sent into and carried out Digital Signal Processing in the DSP, the result that DSP will handle outputs to DDS, be converted into the clock of corresponding frequencies by DDS, it is a steady state value at the phase difference of phase discriminator input port that whole loop finally makes reference source and DDS output clock, then exports clock lock in reference source.Master/backup clock is respectively by the same external reference source of main pll lock.
DSP (digital signal processor) has powerful digital signal processing capability, mainly finish and carry out Filtering Processing differing, after the Filtering Processing phase difference is converted to frequency control word (FTW), or other forms of controlled quentity controlled variable, output to DDS, be converted into the clock signal of corresponding frequencies by DDS according to this frequency control word, the output frequency of control DDS reaches the purpose of pll lock at last.
DDS (direct synthesizer) will do frequency multiplication by the reference clock signal that crystal oscillator produces, and produce the very high system clock of frequency, under the effect of system clock, control the frequency and the phase place of its output clock by the control register of chip then.There is phase accumulator DDS inside, phase accumulator is adjusted word to frequency and is added up under the effect of system clock, result after adding up sends into the phase-magnitude look-up table of a cosine, obtain the range value in this moment by tabling look-up, with the D/A digital to analog converter this range value is converted to correspondent voltage then, in process so continuously, the output of D/A converter has just produced a cosine waveform.Loop is constantly adjusted, and is steady state value up to the difference that makes adjacent twice phase difference data, and at this moment phase-locked loop has just locked.
The effect of DDS is equivalent to the VCO (voltage controlled oscillator) of common phase-locked loop, exactly by providing a frequency control word, makes the clock of DDS chip output certain frequency; It is exactly by changing phase control words, the phase place of output clock being changed that the DDS chip also provides an other function simultaneously.
The communication equipment clock work when the master clock mode of operation, main phase-locked loop operation, DSP only finishes the locking to reference source.The communication equipment clock work is when being equipped with the clock work pattern, DSP is except handling normal reference source locking process, also will handle this plate of decision circuitry output and differing of mainboard, and, make it to align with the mainboard output clock phase with this phase place that differs control DDS chip output clock.
Secondary principle of PLL is as follows, differ decision circuitry and regularly detect the phase difference that mainboard is delivered to the clock of the clock of slave board and slave board output, this is differed report DSP, revise the phase control words of DDS chip by DSP, the phase place of slave board output clock is adjusted, the phase alignment of sending here with mainboard.If but the difference of the double phase demodulation value of main phase-locked loop changes, phase-locked loop will losing lock so, so when DDS output clock is carried out the phase place adjustment, the phase difference data that at every turn obtains that must guarantee main phase-locked loop is constant, therefore, the phase difference data that in DSP main phase-locked loop is collected here compensates with DDS phase modulation value, to guarantee after secondary phase-locked loop carries out the phase modulation operation, do not influence the locking of main phase-locked loop, finally realize the main clock phase alignment.
Except that adopting DDS to carry out the phase alignment, also can adopt delay chip to realize the phase alignment of master/backup clock, differ after decision circuitry differs judgement to master/backup clock, master/backup clock differed report DSP, by the time-delay of DSP, make the phase alignment of master/backup clock by the control valve foot control system delay chip of delay chip.What of control valve foot control system delay chip time-delay, the phase control words that the control pin of delay chip can be regarded as the DDS chip, for example: A clock hysteresis B clock 3ns, then can behind the B clock, add delay chip, the time-delay of delay chip is adjusted to the 3ns place, can finishes the alignment of two clocks.
Foregoing description is the situation under the lock-out state, as be operated under free oscillation or the maintenance pattern, master/backup clock will work under the free oscillation or maintenance pattern of oneself separately, the secondary phase-locked loop of master clock (phase alignment part) is not worked, be equipped with secondary phase-locked loop (phase alignment part) work of clock, guarantee to be equipped with the clock output phase and align with the master clock output phase all the time.
Be illustrated in figure 2 as phase adjusted schematic diagram of the present invention, be equipped with timing reference input (Slave Ref) and master clock homology, the phase adjusted purpose makes exactly that fully clock output (Slave Local) phase place is consistent with master clock output (Master Clock) phase place, but guarantees that again the output frequency that is equipped with clock does not change when the adjustment output phase.If the just simple output phase that is equipped with clock that changes, certainly will destroy the poised state of original main phase-locked loop so, so the present invention is after having regulated output clock phase, notify main phase-locked loop this phase adjusted amount, and in DSP, data based this phase adjusted amount of the phase demodulation of phase discriminator is compensated, thereby avoid regulating output clock phase the phase-locked process of main phase-locked loop is exerted an influence.
As can be seen from Figure 2, be equipped with clock and begin to regulate output phase constantly, establish original master/backup clock and differ and be that Δ φ, the phase difference that phase discriminator obtains are respectively P (t1), P (t2), P (t3), P (t4), P (t5) from t3.If do not adjust the DDS output phase, then the phase difference should be P (t1)=P (t2)=P (t3)=P (t4)=P (t5) under lock-out state.If begin to adjust the DDS output phase constantly from t3, then the phase difference of phase discriminator (is discussed a kind of situation for the time being for subtract Δ φ on original phase difference basis, situation about subtracting and situation about adding are similar), promptly participating in phase-locked phase difference is P (t1), P (t2), P (t3)-Δ φ, P (t4)-Δ φ, P (t5)-Δ φ, the phase difference that change on the phase discriminator this moment is because the adjusting of output clock phase causes, so in the phase demodulation value, should give compensation, promptly the phase demodulation value that will be obtained from phase discriminator by DSP from t3 constantly, each phase difference all compensates Δ φ, make the phase difference that finally enters phase locked algorithm satisfy original constant requirement that differs equally, thereby guaranteeing does not influence the lock characteristic of main phase-locked loop when adjusting output clock phase.
When adjusting active and standby phase alignment, master/backup clock adopts the mode of phase demodulation to judge whether the phase place of master/backup clock aligns, if alignment then adjust phase place be zero or about it, carry out among a small circle in the adjustment action, if the phase place adjustment is not then proceeded in alignment.The adjustment amount of phase alignment can be the phase difference of master/backup clock or the stepping amount of fixed step size (or variable step), is stable at aligned condition at last.
Certainly be equipped with clock and also can utilize phase discriminator, DSP, DDS directly to lock master clock, utilize the present invention can realize the main clock phase alignment equally.The present invention can follow the tracks of the phase place of regulating self output clock in the process of same reference source at the master/backup clock of communication equipment, thereby makes the phase place of clock output fully and the phase alignment of master clock, has avoided producing error code in the process of masterslave switchover.
Claims (8)
1, a kind of phase alignment method of master/backup clock is characterized in that, may further comprise the steps:
Be equipped with the clock tracing master clock or follow the tracks of same reference source, make master/backup clock output frequency unanimity with master clock;
Master/backup clock is differed judgement, be equipped with the adjustment of clock output phase, make the main clock phase alignment according to master/backup clock phase difference.
2, the phase alignment method of master/backup clock according to claim 1, it is characterized in that: when clock and master clock are followed the tracks of same reference source fully, according to described master/backup clock phase difference the phase demodulation value that is equipped with clock and reference source is compensated, the adjustment of clock output phase is not fully influenced be equipped with the locking of clock the reference source frequency.
3, the phase alignment method of master/backup clock according to claim 1 and 2, it is characterized in that: be equipped with clock and pass through phase discriminator, signal processor and direct synthesizer (DDS) are followed the tracks of master clock or are followed the tracks of same reference source with master clock, described phase discriminator compares the phase difference between DDS output clock and master clock or the reference source, this phase difference is carried out digitlization, differing after the digitlization sent into and carried out Digital Signal Processing in the signal processor, data after signal processor will be handled are converted to frequency control word and output to DDS, be converted into the clock of corresponding frequencies by DDS, making master clock or reference source and DDS output clock is a steady state value at the phase difference of phase discriminator input port, makes output clock frequency locking master clock or reference source.
4, the phase alignment method of master/backup clock according to claim 3, it is characterized in that: employing differs decision circuitry master/backup clock is differed judgement, master/backup clock differed report described signal processor, revise the phase control words of DDS by signal processor, adjust clock output phase fully, make the main clock phase alignment.
5, the phase alignment method of master/backup clock according to claim 3, it is characterized in that: employing differs decision circuitry master/backup clock is differed judgement, master/backup clock differed report described signal processor, by the time-delay of signal processor, make the phase alignment of master/backup clock by the control valve foot control system delay chip of delay chip.
6, the phase alignment method of master/backup clock according to claim 3 is characterized in that: the adjustment amount of main clock phase alignment can be the phase difference of master/backup clock or the stepping amount of fixed step size or variable step.
7, the phase alignment method of master/backup clock according to claim 3 is characterized in that: described signal processor adopts digital signal processor (DSP) or microprocessor or programmable logic device to realize.
8, the phase alignment method of master/backup clock according to claim 3, it is characterized in that: when clock and master clock are followed the tracks of same reference source fully, under free oscillation or maintenance pattern, master/backup clock works in free oscillation or the maintenance pattern of oneself separately, the active and standby phase alignment part of master clock is not worked, the active and standby phase alignment that is equipped with clock is partly worked, and guarantees to be equipped with the clock output phase and aligns with the master clock output phase all the time.
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| WO2007000111A1 (en) * | 2005-06-27 | 2007-01-04 | Huawei Technologies Co., Ltd. | Device for clock phase alignment between main and backup clock board, method and clock board thereof |
| WO2008125041A1 (en) * | 2007-04-13 | 2008-10-23 | Huawei Technologies Co., Ltd. | Method and device for controlling main-backup inversion |
| WO2009082909A1 (en) * | 2007-12-14 | 2009-07-09 | Huawei Technologies Co., Ltd. | Method for realizing time master-standby protection and time master-standby protection device |
| CN101162959B (en) * | 2007-10-19 | 2011-08-24 | 中兴通讯股份有限公司 | Clock master-slave phase difference automatic measurement and compensation process |
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| CN114499501B (en) * | 2022-04-19 | 2022-08-26 | 成都市克莱微波科技有限公司 | Frequency source dynamic control method, control device and system |
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