CN101162959B - Clock master-slave phase difference automatic measurement and compensation process - Google Patents
Clock master-slave phase difference automatic measurement and compensation process Download PDFInfo
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- CN101162959B CN101162959B CN2007101650223A CN200710165022A CN101162959B CN 101162959 B CN101162959 B CN 101162959B CN 2007101650223 A CN2007101650223 A CN 2007101650223A CN 200710165022 A CN200710165022 A CN 200710165022A CN 101162959 B CN101162959 B CN 101162959B
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Abstract
The invention discloses a method of automatic detection and compensation of the main/standby phase diversity of clocks. The method comprises the following steps: a detection step, a main clock unit at main status and a standby clock unit at standby status, provided with redundant layout, powered on, the standby clock unit automatically detects the phase difference of the main clock unit in real time. A compensation step, the standby clock unit is processed with the phase compensation according to the phase difference to enable the output phase of the main/standby clocks to be synchronous. According to the invention, the automatic detection of the phase diversity and the compensation of the output phase of the standby clock unit can be reached by layout and software configuration without any extra part. The invention can enable the phase of the output ends of the main/standby clock units to be consistent, thereby guaranteeing the phase continuity when main/standby switching. The consistency of the main/standby output phase guarantees the least effect on the system when main/standby switching and no slip code/bit error of service card created because of clock units switching.
Description
Technical field
The present invention relates to a kind of network service Clock Synchronization Technology, more particularly, is a kind of synchronous master/backup clock that is used for, and realizes the processing method of end-to-end phase position automatic measuring of active and standby output and compensation.
Background technology
Communication equipment generally adopts the mode of master-slave redundancy to improve the reliability of system, and clock is a very important part for communication service, therefore generally also adopts active and standby working method in system design.In synchronous digital communications network, realizing by clock unit synchronously between each network element node in the net.Each network element node configuration is two active and standby each other clock units, realize that clock active/standby smoothly switches, service board can not given birth to error code because of the clock wave movable property, and the continuous index of the phase place of master/backup clock unit has been proposed requirement, the discontinuous index of phase place during G.812 following table shows.
| MTIE (nanosecond) | Measuring Time τ (second) |
| 60 | τ≤0.001 |
| 120 | 0.001＜τ≤4 |
| 240 | τ＞4 |
Content as shown in Table 1, when G.812 code requirement is switched in the master/backup clock unit, less than 60 nanoseconds, less than 120 nanoseconds, active and standby output phase difference accumulative total phase change is less than 240 nanoseconds in 4 seconds observation times in 0.001 second observation time for active and standby output phase difference.Visual communication system has proposed strict demand to accurate synchronised clock, to guarantee the steady operation of system.
The clock synchronization mode of extensive use at present is that HMS hierarchical master-slave is synchronous.In case main clock unit with state breaks down, the clock unit of stand-by state substitutes main clock unit with state immediately and provides synchronised clock output for communication equipment.The master/backup clock unit switches will guarantee phase continuity as far as possible, otherwise will exert an influence to business, as producing error code or professional hit.In order to satisfy the demand, should consider that at first two clock units keep synchronously, the clock unit that necessarily requires to be in stand-by state compensates accurately for the various delays that produce in the system.
Handling on the master/backup clock working method, mainly contain two kinds of implementations: a kind of is the active and standby outside reference of following the tracks of simultaneously, another kind is that main clock unit with state is followed the tracks of the external clock benchmark, and the clock unit of stand-by state is followed the tracks of main clock unit output with state.The present invention is based on second kind of scheme, guarantee active and standby homology, make the output frequency unanimity of master/backup clock.And keep the consistency of active and standby output phase, and different implementation methods is arranged, differ decision circuitry etc. as use.Application number is to have disclosed in the application for a patent for invention of CN03157802.0 (publication number is CN1592134A) to adopt to differ decision circuitry master/backup clock is differed judgement, by phase discriminator master/backup clock is differed judgement, be equipped with the adjustment of clock output phase according to master/backup clock phase difference, make the main clock phase alignment; In signal processor, phase discriminator output phase demodulation value is compensated, the adjustment of clock output phase is not fully influenced be equipped with the locking of clock the reference source phase place according to described master/backup clock phase difference.But above-mentioned patent application also needs to dispose devices such as phase discriminator, has the defective of circuit complexity, cost height, complicated operation.
Summary of the invention
In view of above-mentioned technical problem, the object of the present invention is to provide clock master-slave phase difference automatic measurement and compensation method in a kind of communication system, it need not extra device, reaches automatic Measurement Phase difference by wiring and software arrangements, the effect of compensation standby clock unit output phase.
Clock master-slave phase difference automatic measurement according to a first aspect of the invention and compensation method, this method may further comprise the steps: measuring process, after being provided with the main active clock unit with state of being in of redundant wiring and powering on the standby clock unit that is in stand-by state, the standby clock unit is automatically measured the phase difference of master/backup clock in real time; Compensation process carries out phase compensation according to phase difference to the standby clock unit, so that the output phase of master/backup clock is synchronous.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, before described measuring process, comprise design procedure, described design procedure is used for described active clock unit and described standby clock unit are designed, comprise following process: when design described active clock unit and described standby clock unit, design of feedback input on described active clock unit and described standby clock unit makes the delay of described active clock unit and the unit kinetic measurement of described standby clock equal phase delay between described active clock unit and the described standby clock unit by described redundant wiring; On described active clock unit and described standby clock unit, dispose active and standby synchronous passage respectively, output synchronizing clock signals and frame synchronizing signal on described active clock unit; On described standby clock unit, utilize the first passage T0 of synchronizer clock source module to carry out the synchronous input of described master/backup clock, the synchronizing signal that preferential locking is transmitted from described active clock unit.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, described measuring process comprises following process: the setting of measuring passage, in the feedback input of this unit of the described standby clock of the second channel T4 positive lock unit of the described synchronizer clock of standby clock unit by using source module, this feedback input is used for measuring specially the feedback line delay of described active clock unit and described standby clock unit; Utilize the manual offset modulation function of described synchronizer clock source module,, be configured to the skew of input and output the phase difference of the described master/backup clock that calculates after measuring.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, in described compensation process, when the main and standby relation of described active clock unit and described standby clock unit changes, if described standby clock unit does not carry out under the situation of described measuring process, repeat following process: after described active clock unit and described standby clock unit power on, after finishing, main and standby competition determines main and standby relation, according to active and standby locking strategy, described active clock unit and described standby clock unit are set the priority of input separately respectively; Described active clock unit is made as not lockable with active and standby synchronous interlocking clock priority, described standby clock unit is made as described active and standby synchronous interlocking clock priority the highest, to reach described active clock unit locking outside reference, described standby clock unit locks the purpose of described active clock unit output; Described active clock unit and the difference of described standby clock unit are provided with, and enable to build the phase function on described active clock unit, forbid the phase deviation function; Forbidding is built the phase function on described standby clock unit, enables the phase deviation function, closes automatic phase compensation, forces manual phase compensation, so that the output phase of described master/backup clock is synchronous; First passage T0 in described standby clock unit enters lock-out state, and locking be the described active and standby synchronous interlocking clock of described active clock unit output the time, the feedback signal that the described standby clock of the second channel T4 steady lock unit of described standby clock unit produces, to add that fixing backboard cabling Time delay measurement value obtains active and standby output phase difference the backboard cabling time-delay of whole measurement loop between described active clock unit and described standby clock unit, preserve described phase difference, described phase difference process is calculated the skew that is configured to synchronizer clock source module, to adjust the output phase of spare module.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, in described compensation process, when the main and standby relation of described active clock unit and described standby clock unit changes, if described standby clock unit has carried out described measuring process, then only repeat following process: described active clock unit and the difference of described standby clock unit are provided with, on described active clock unit, enable to build the phase function, forbid the phase deviation function; Forbidding is built the phase function on described standby clock unit, enables the phase deviation function, closes automatic phase compensation, forces manual phase compensation, so that the output phase of described master/backup clock is synchronous.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, in described redundant wiring, the transmission circuit of the active and standby synchronous interlocking clock of the described standby clock unit of stand-by state locking comprises first circuit, second circuit, tertiary circuit, the 4th circuit; This plate loopback feedback signal of described standby clock unit comprises the 5th circuit, the 6th circuit, the 7th circuit, the 8th circuit, wherein, make on track lengths described the 4th circuit=described the 5th circuit, described tertiary circuit=described the 6th circuit, described second circuit=described the 7th circuit, described first circuit=described the 8th circuit by connecting up.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, when described active clock unit and described standby clock unit are imported in this plate of measurement loopback feedback signal, process two-stage clock driver spare between described active clock unit and described standby clock unit.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, the first passage T0 of described standby clock unit is used to lock synchronised clock output; The second channel T4 of described standby clock unit is used to simulate the time-delay phase measurement.
In above-mentioned clock master-slave phase difference automatic measurement and compensation method, described first passage T0 comprises digital phase-locked loop and analog phase-locked look.Described second channel T4 comprises digital phase-locked loop and analog phase-locked look.
The characteristics of this patent are in design, on single master/backup clock unit, adopt the active and standby synchronous transmission circuit of redundant wiring simulation, configuration SETS (Synchronous EquipmentTiming Source, synchronizer clock source) the T4 passage of module detects and differs, and utilizes the offset functions adjustment output of SETS module.Need not extra device, can reach automatic Measurement Phase difference, the effect of compensation standby clock unit output phase by wiring and software arrangements.
According to the present invention, can make the standby clock unit that is in stand-by state, can be because the summation of the phase difference that various factorss such as veneer cabling, process driving element, backboard transmission, phase-locked chip self phase delay cause between the automatic measurement in the back that powers on is active and standby.
By the method for this automatic measurement and compensation of phase, make master/backup clock unit output phase place unanimity, the phase continuity when guaranteeing masterslave switchover.The consistency of active and standby output phase when having guaranteed that the master/backup clock unit is switched, to the minimum influence of system, can not switched because of clock unit and cause service board slip/error code.
Other features and advantages of the present invention will be set forth in the following description, and, partly from specification, become apparent, perhaps understand by implementing the present invention.Purpose of the present invention and other advantages can realize and obtain by specifically noted structure in the specification of being write, claims and accompanying drawing.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of specification, is used from explanation the present invention with embodiments of the invention one, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the flow chart of first embodiment of the invention;
Fig. 2 is wiring and the synchronous schematic diagram of importing, feeding back input;
Fig. 3 is the schematic diagram of the T0/T4 passage of SETS module;
Fig. 4 measures and the main state schematic flow sheet of using of compensation;
Fig. 5 measures and compensation stand-by state schematic flow sheet.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
Fig. 1 shows the flow chart of first embodiment of the invention, comprise measuring process S10 and compensation process S12, in measuring process S10, after being provided with the main active clock unit with state of being in of redundant wiring and powering on the standby clock unit that is in stand-by state, the standby clock unit is automatically measured the phase difference of master/backup clock in real time; In compensation process S12, according to phase difference the standby clock unit is carried out phase compensation, so that the output phase of master/backup clock is synchronous.
The back real-time automatic measuring that powers in the master/backup clock unit goes out active and standby phase difference, and carries out the output phase compensation of standby clock unit according to this difference, to reach the synchronous purpose of master/backup clock output frequency and output phase.The clock master-slave phase difference automatic measurement of present embodiment and the method for compensation also comprise design procedure between measuring process.
Wherein, design procedure comprises following process:
Design is during clock unit, and design of feedback input on the master/backup clock unit by the redundancy wiring, makes the delay of described clock unit kinetic measurement equal the phase delay between active and standby Unit two.
Dispose active and standby synchronous passage respectively on active and standby two unit, (main clock unit with state) goes up output synchronizing clock signals and frame synchronizing signal in the active clock unit.(synchronizer clock source: Synchronous Equipment Timing Source) the T0 passage of module carries out active and standby synchronised clock input, the synchronizing signal that preferential locking is transmitted from the active clock unit to utilize SETS on standby clock unit (clock unit of stand-by state).The benefit of doing like this is main clock unit locking outside reference with state, and active and standby homology is guaranteed in the main output with the state timer unit of clock unit locking of stand-by state.
Measuring process comprises following process:
Measure the setting of passage, the feedback input of this unit of second channel (T4) the positive lock standby clock unit of standby clock unit by using SETS module, this feedback input is used for measuring specially the feedback line delay of high master/backup clock unit.
Utilize the manual offset modulation function of SETS module,, be configured to the skew of input and output the phase difference of the master/backup clock that calculates after measuring.
Utilize present embodiment to measure master-slave phase difference automatically, and the compensation process that carries out the phase compensation of standby clock unit may further comprise the steps:
Steps A, the master/backup clock unit powers on, and determines main and standby relation after main and standby competition is finished, and according to active and standby locking strategy, the master/backup clock unit is set the priority of input separately respectively; The active clock unit is made as not lockable with active and standby synchronous interlocking clock priority, the standby clock unit is made as active and standby synchronous interlocking clock priority the highest, to reach active clock unit locking outside reference, the purpose of standby clock unit locking active clock unit output.
Step B, the difference of master/backup clock unit is provided with, and enables PBO (Phase build-out builds the phase function) function on the active clock unit, forbids Phase Offset (phase deviation) offset functions, with better adaptation circuit input, provides energy level and smooth output; Forbidding PBO function is enabled Phase Offset offset functions on the standby clock unit.Close automatic phase compensation, force manual phase compensation, be not subjected to the influence of SETS inside modules automatic phase adjustment algorithm, synchronous to reach active and standby output phase.
Step C treats that the T0 of standby clock unit enters lock-out state, and locking is the active and standby synchronous interlocking clock of active clock unit output; The feedback signal that this unit of T4 steady lock produces.Whole measurement loop in all being included in, adds that fixing backboard cabling Time delay measurement value obtains active and standby output phase difference except the time-delay of the backboard cabling between active and standby.Preserve the phase difference that records this moment, through calculating the skew that is configured to the SETS module, to adjust the output phase of spare module.
Because phase delay need not be measured in real time by the decision of hardware physical characteristic, after the configuration module skew, the clock unit that is in stand-by state no longer calculates phase difference.Change until main and standby relation, if as the clock unit of stand-by state do not carry out this measuring process before this, then repeating step A, step B, step C postpone a repeating step B if measured after the master/backup clock unit powers on.
The present invention utilizes means such as active and standby synchronised clock/synchronizing signal, T4 loopback feedback are measured, redundancy connects up, active and standby difference is provided with identical to reach output frequency, the effect that output phase is synchronous.Fig. 2 is wiring and the synchronous schematic diagram of importing, feeding back input, concrete enforcement as shown in Figure 2, i.e. active and standby synchronous interlocking clock transfer line route first circuit 101 of clock unit of stand-by state locking, second circuit 102, tertiary circuit 103, the 4th circuit 104 are formed.The standby clock unit feedback of stand-by state is measured input, and promptly standby clock unit this plate loopback feedback signal of stand-by state is made up of the 5th circuit 105, the 6th circuit 106, the 7th circuit 107, the 8th circuit 108.Make on track lengths the feasible 4 part 104=105 that constitute this plate loopback passage, 103=106,102=107,101=108 by connecting up.When measuring the input of this plate loopback feedback signal, on clock unit, have a mind to through two-stage clock driver spare.By such design, the path of the active and standby mutual biography clock of imitation transfers back to the SETS module then on the master/backup clock unit, comes the Measurement Phase time-delay by T4.Make full use of SETS module T0/T4 two passes, and these phase position adjusting functions of input and output PBO, Phase Offset, to reach the synchronous purpose of master/backup clock unit output phase.
The processing method of whole phase automatic compensating comprises design and measures two parts:
One, design part
Between active clock unit 109 and the standby clock unit 111, transmit synchronised clock and frame synchronizing signal among Fig. 2 through active and standby synchronised clock interconnect circuit.Interconnect circuit is made up of first circuit 101, second circuit 102, tertiary circuit 103, the 4th circuit 104 and two-stage clock driver spare.In addition, backboard 110 is between two-stage clock driver spare.
Constitute five circuits, 105, the six circuits, 106, the seven circuits, 107, the eight circuits 108 of 4 parts of this plate loopback passage, on length of arrangement wire, make 104=105,103=106,102=107,101=108.By the redundancy wiring and through two-stage clock driver spare, reach the effect that single clock unit is simulated active and standby mutual biography circuit.
Fig. 3 has represented the schematic diagram that concerns of two passage T0/T4 in the SETS module.The present invention uses the T0 passage locking synchronised clock output of standby clock unit, uses the T4 passage to simulate the time-delay phase measurement.The 201st, the digital phase-locked loop of T4 passage, the 202nd, the analog phase-locked look of T4 passage, 201 and 202 have constituted the T4 passage jointly.The 203rd, the digital phase-locked loop of T0 passage, the 204th, the analog phase-locked look of T0 passage, 203 and 204 have constituted the T4 passage jointly.
Two, measure portion
Fig. 4 show clock unit power on obtain main with the flow chart behind the state.
Step S301 finishes main and standby competition or masterslave switchover after the clock unit powers on, main and standby relation determines that according to active and standby locking strategy, the master/backup clock unit is set the priority of input separately respectively.Configuring external benchmark priority on the active clock unit is made as active and standby interlocking synchronised clock unavailable.
Step S302, the difference of master/backup clock unit is provided with.Be on the main clock unit and enable the PBO function, forbid Phase Offset offset functions,, provide energy level and smooth output with better adaptation circuit input with state.
After configuration is finished, transfer stand-by state to up to masterslave switchover takes place, the dependent phase compensation is provided with no longer and changes.
Fig. 5 shows clock unit and powers on and enter flow chart behind the stand-by state.
Step S401 finishes main and standby competition or masterslave switchover after the master/backup clock unit powers on, main and standby relation determines that according to active and standby locking strategy, the master/backup clock unit is set the priority of input separately respectively.The active and standby interlocking synchronised clock of configuration is made as limit priority on the standby clock unit.
Step S402, the difference of master/backup clock unit is provided with.Be in forbidding PBO function on the clock unit of stand-by state, enable Phase Offset offset functions.Close automatic phase compensation, force manual phase compensation, to reach active and standby phase locked purpose.
Step S403 is in the clock unit of stand-by state, treats that T0 passage DPLL 203 enters lock-out state, and locking is mainly to export active and standby synchronous interlocking clock with the clock unit of state; The feedback signal that this unit of T4 passage DPLL 201 steady lock produces.Whole measurement loop is except the time-delay of the backboard cabling between active and standby, in all being included in.
Step S404, the phase difference of kinetic measurement add that fixing backboard cabling Time delay measurement value obtains the phase difference of active and standby output.Preserve the phase difference that records this moment, through calculating the skew that is configured to the SETS module, to adjust the output phase of spare module.
After configuration is finished, transfer the main state of using to up to masterslave switchover takes place, the dependent phase compensation is provided with no longer and changes.
Because phase delay is by the decision of hardware physical characteristic, need not measure in real time, after the configuration module skew, the clock unit that is in stand-by state no longer calculates phase difference.Change until main and standby relation, if do not carry out this measuring process, then repeating step S401, S402, S403, S404 before this as the clock unit of stand-by state.Only need to postpone repeating step S401, S402 if measured after clock unit powers on.If step S403, S404 finish on clock unit before this, each result who measures is consistent substantially for single clock unit, there is no need all to carry out step S403 at every turn, and S404 is to improve system effectiveness.
In order to reach the purpose of master/backup clock unit phase compensation, need when standby clock unit output clock, compensate the path delay of the clock process of active clock unit output in the prior art.At the SETS module of different model, in order to obtain phase compensation value, manually with the phase difference value of the active and standby output signal of oscilloscope measurement, phase compensation is carried out in configuration skew afterwards respectively.This compensation is relevant with the clock input/output driver spare of selecting for use, SETS module, and the material variation of device (the different suppliers that comprise material batch or identical code) may cause compensated differences.
Compared with prior art, the present invention adopts automatic measurement and compensation, treat to treat after the clock unit powers on that the locking of active and standby synchronizing signal is stable and this unit feedback signal locking is stable, the advantage of real-time automatic measuring phase difference do not need to be manual intervention, does not relate to because of empirical value causing human error.The present invention utilizes existing equipment just to reach the standby clock unit output phase actual effect of compensation automatically by the appropriate configuration of software.
Should be understood that above-mentioned description at the specific embodiment of the invention is comparatively detailed, but can not therefore be interpreted as the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (9)
1. clock master-slave phase difference automatic measurement and compensation method is characterized in that, may further comprise the steps:
Measuring process, after being provided with the main active clock unit with state of being in of redundant wiring and powering on the standby clock unit that is in stand-by state, described standby clock unit is automatically measured the phase difference of master/backup clock in real time;
Compensation process carries out phase compensation according to described phase difference to described standby clock unit, so that the output phase of described master/backup clock is synchronous;
Wherein, comprised design procedure before described measuring process, described design procedure is used for described active clock unit and described standby clock unit are designed, and comprises following process:
When design described active clock unit and described standby clock unit, design of feedback input on described active clock unit and described standby clock unit makes the delay of described active clock unit and the unit kinetic measurement of described standby clock equal phase delay between described active clock unit and the described standby clock unit by described redundant wiring;
On described active clock unit and described standby clock unit, dispose active and standby synchronous passage respectively, output synchronizing clock signals and frame synchronizing signal on described active clock unit; On described standby clock unit, utilize the first passage (T0) of synchronizer clock source module to carry out the synchronous input of described master/backup clock, the synchronizing signal that preferential locking is transmitted from described active clock unit.
2. clock master-slave phase difference automatic measurement according to claim 1 and compensation method is characterized in that:
Described measuring process comprises following process:
Measure the setting of passage, in this unit feedback input of the described standby clock of second channel (T4) the positive lock unit of the described synchronizer clock of described standby clock unit by using source module, this feedback input is used for measuring specially the feedback line delay of described active clock unit and described standby clock unit;
Utilize the manual offset modulation function of described synchronizer clock source module,, be configured to the skew of input and output the phase difference of the described master/backup clock that calculates after measuring.
3. clock master-slave phase difference automatic measurement according to claim 2 and compensation method is characterized in that:
In described compensation process, when the main and standby relation of described active clock unit and described standby clock unit changes, if described standby clock unit does not carry out repeating following process under the situation of described measuring process:
After described active clock unit and described standby clock unit power on, determine main and standby relation after main and standby competition is finished, according to active and standby locking strategy, described active clock unit and described standby clock unit are set the priority of input separately respectively; Described active clock unit is made as not lockable with active and standby synchronous interlocking clock priority, described standby clock unit is made as described active and standby synchronous interlocking clock priority the highest, to reach described active clock unit locking outside reference, described standby clock unit locks the purpose of described active clock unit output;
Described active clock unit and the difference of described standby clock unit are provided with, and enable to build the phase function on described active clock unit, forbid the phase deviation function; Forbidding is built the phase function on described standby clock unit, enables the phase deviation function, closes automatic phase compensation, forces manual phase compensation, so that the output phase of described master/backup clock is synchronous;
First passage (T0) in described standby clock unit enters lock-out state, and locking be the described active and standby synchronous interlocking clock of described active clock unit output the time, the feedback signal that the described standby clock of second channel (T4) the steady lock unit of described standby clock unit produces, to add that fixing backboard cabling Time delay measurement value obtains active and standby output phase difference the backboard cabling time-delay of whole measurement loop between described active clock unit and described standby clock unit, preserve described phase difference, described phase difference process is calculated the skew that is configured to synchronizer clock source module, to adjust the output phase of spare module.
4. clock master-slave phase difference automatic measurement according to claim 2 and compensation method is characterized in that:
In described compensation process, when the main and standby relation of described active clock unit and described standby clock unit changes,, then only repeat following process if described standby clock unit has carried out described measuring process:
Described active clock unit and the difference of described standby clock unit are provided with, and enable to build the phase function on described active clock unit, forbid the phase deviation function; Forbidding is built the phase function on described standby clock unit, enables the phase deviation function, closes automatic phase compensation, forces manual phase compensation, so that the output phase of described master/backup clock is synchronous.
5. according to each described clock master-slave phase difference automatic measurement and compensation method in the claim 1 to 4, it is characterized in that:
In described redundant wiring, the transmission circuit of the active and standby synchronous interlocking clock of the described standby clock unit of stand-by state locking comprises first circuit (101), second circuit (102), tertiary circuit (103), the 4th circuit (104); This plate loopback feedback signal of described standby clock unit comprises the 5th circuit (105), the 6th circuit (106), the 7th circuit (107), the 8th circuit (108),
Wherein, make on track lengths described the 4th circuit (104)=described the 5th circuit (105), described tertiary circuit (103)=described the 6th circuit (106), described second circuit (102)=described the 7th circuit (107), described first circuit (101)=described the 8th circuit (108) by connecting up.
6. clock master-slave phase difference automatic measurement according to claim 5 and compensation method is characterized in that:
When described active clock unit and described standby clock unit are imported in this plate of measurement loopback feedback signal, process two-stage clock driver spare between described active clock unit and described standby clock unit.
7. clock master-slave phase difference automatic measurement according to claim 6 and compensation method is characterized in that:
The first passage (T0) of described standby clock unit is used to lock synchronised clock output;
The second channel (T4) of described standby clock unit is used to simulate the time-delay phase measurement.
8. clock master-slave phase difference automatic measurement according to claim 7 and compensation method is characterized in that:
Described first passage (T0) comprises digital phase-locked loop (203) and analog phase-locked look (204).
9. clock master-slave phase difference automatic measurement according to claim 7 and compensation method is characterized in that:
Described second channel (T4) comprises digital phase-locked loop (201) and analog phase-locked look (202).
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| CN102694616B (en) * | 2012-06-11 | 2014-11-26 | 福建星网锐捷网络有限公司 | Clock detection circuit, clock circuit and clock exception detection method |
| WO2014075260A1 (en) * | 2012-11-15 | 2014-05-22 | 华为技术有限公司 | Time delay compensation method and apparatus |
| CN104980245A (en) * | 2015-07-01 | 2015-10-14 | 大唐电信（成都）信息技术有限公司 | Redundancy protection output apparatus and method of frequency timing output signal of synchronized clock equipment |
| CN106658626B (en) * | 2015-10-29 | 2020-12-22 | 中兴通讯股份有限公司 | Clock switching method, device and base station |
| CN106656392A (en) * | 2016-12-26 | 2017-05-10 | 广东大普通信技术有限公司 | Clock reference seamless switching method and device |
| CN110119331B (en) * | 2018-02-07 | 2021-10-01 | 华为技术有限公司 | Clock switching method and device, server and clock system |
| CN110660429B (en) * | 2018-06-29 | 2021-09-14 | 华为技术有限公司 | Storage system and storage control device |
| CN112436914B (en) * | 2019-08-26 | 2022-08-30 | 烽火通信科技股份有限公司 | Method and system for protecting master and slave 5G ultrahigh-precision clocks |
| CN111082887B (en) * | 2019-12-03 | 2022-03-18 | 锐捷网络股份有限公司 | System, method, device, equipment and medium for signal transmission delay compensation |
| CN112583512B (en) * | 2020-12-10 | 2023-04-11 | 北京航星机器制造有限公司 | Time synchronization device and method |
| CN114124616B (en) * | 2022-01-25 | 2022-05-27 | 浙江中控研究院有限公司 | Clock synchronization optimization method based on EPA bus structure |
| CN115021857B (en) * | 2022-08-08 | 2022-12-16 | 中汽创智科技有限公司 | Clock synchronization method and device, electronic equipment and storage medium |
| CN115865079B (en) * | 2022-11-22 | 2023-08-01 | 复旦大学 | High-precision phase difference measuring device and method for main clock link and standby clock link |
| CN117097432B (en) * | 2023-10-18 | 2024-01-02 | 成都立思方信息技术有限公司 | Clock synchronization method, device and medium of distributed high-speed signal receiving and transmitting system |
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| CN1155339A (en) * | 1994-07-13 | 1997-07-23 | 诺基亚电信公司 | Method and system for automatic compensation of line delay in a clock distribution system |
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| CN1658546A (en) * | 2004-02-18 | 2005-08-24 | 华为技术有限公司 | Method for implemention of master-spare clock phase alignment in communication equipment |
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