CN112583512B - Time synchronization device and method - Google Patents
Time synchronization device and method Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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Abstract
A time synchronization apparatus and method, the apparatus comprising: a master clock module for generating a local master clock; the synchronization module is used for carrying out data communication with the superior main equipment and acquiring recovered clock information; sending the time synchronization information in the communication data to an information processing module; the backup module is used for backing up the main clock and storing the time synchronization information sent by the information processing module; the clock detection module is used for detecting whether the main clock module and the synchronization module have faults or not and sending corresponding clock switching control signals to the clock switching module according to the detection result; the clock switching module is used for switching clocks and sending a switched system clock signal and a control signal to the information processing module; the information processing module is used for starting the synchronization module and adjusting the system time of the equipment to synchronize the time of the equipment with the time of the superior main equipment; and sending the time synchronization information to a backup module or acquiring a plurality of groups of time synchronization information stored by the backup module.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a time synchronization apparatus and method.
Background
A conventional communication equipment system generally includes a plurality of communication function modules, each of which is independent of each other and communicates with each other, and each of which includes an independent clock system. In order to realize a multitask scene based on the time sequence, all time systems in the equipment system are unified to realize the time synchronization of the whole system.
In a time synchronization communication system based on a network interface, the equipment of the current level recovers a clock frequency signal of superior equipment from network data, and switches the local clock frequency into the recovered clock signal to complete clock frequency synchronization of master and slave equipment; on the basis, the time stamps of the two sides are exchanged, the time phase difference is obtained, and the clock phase of the slave equipment is adjusted, so that the time synchronization of the master equipment and the slave equipment can be realized. It can be seen that in the application of time synchronization, stable and reliable clock signal switching is the basis of time synchronization.
When a local system clock fails, such as a clock source is damaged, aged, or has a circuit fault, or network communication is abnormal, time synchronization between a master device and a slave device cannot be realized.
Disclosure of Invention
In view of the foregoing analysis, embodiments of the present invention provide a time synchronization apparatus and method, so as to solve the problem that the time synchronization between a master device and a slave device cannot be realized when a local system clock fails.
In one aspect, an embodiment of the present invention provides a time synchronization apparatus, including:
a master clock module for generating a local master clock;
the synchronization module is started by the information processing module and is used for carrying out data communication with the superior main equipment to acquire recovered clock information; sending the time synchronization information in the communication data to an information processing module;
the backup module is used for backing up the master clock and storing the time synchronization information sent by the information processing module;
the clock detection module is used for detecting whether the main clock module and the synchronization module have faults or not and sending corresponding clock switching control signals to the clock switching module according to the detection result;
the clock switching module is used for carrying out corresponding clock switching according to the clock switching control signal and sending a switched system clock signal and a control signal to the information processing module;
the information processing module is used for starting the synchronization module according to the system clock signal; adjusting the system time of the equipment according to the time synchronization information to synchronize the time of the equipment with the time of the superior main equipment; and sending the time synchronization information to a backup module or acquiring a plurality of groups of time synchronization information stored by the backup module according to the control signal. .
Based on a further improvement of the above method, the clock switching control signals include a main clock enable signal Sclk _ en, a recovery clock enable signal Rclk _ en, and a backup clock enable signal Mclk _ en.
Further, the clock detection module sends a corresponding clock switching control signal to the clock switching module according to the detection result, the clock switching module performs corresponding clock switching according to the clock switching control signal, and sends a switched system clock signal and a switched control signal to the information processing module, including: when both the master clock module and the synchronization module have no fault, the clock switching control signal sent by the clock detection module is Sclk _ en = H, rclk _ en = H, mclk _ en = L, the clock switching module switches the system clock into the recovered clock, and sends the recovered clock signal and the control signal M _ start = H to the information processing module.
Further, the clock detection module sends a corresponding clock switching control signal to the clock switching module according to the detection result, the clock switching module performs corresponding clock switching according to the clock switching control signal, and sends the switched system clock signal and the control signal to the information processing module, and the method further includes: when only the main clock module fails, the clock switching control signal sent by the clock detection module is Sclk _ en = L, rclk _ en = H, mclk _ en = H, the clock switching module switches the system clock into the backup clock, and sends the backup clock signal and the control signal M _ start = H to the information processing module.
Further, the clock detection module sends a corresponding clock switching control signal to the clock switching module according to the detection result, the clock switching module performs corresponding clock switching according to the clock switching control signal, and sends the switched system clock signal and the control signal to the information processing module, and the method further includes: when only the synchronization module fails, the clock switching control signal sent by the clock detection module is Sclk _ en = H, rclk _ en = L, mclk _ en = L, the clock switching module switches the system clock to the master clock, and sends the master clock signal and the control signal M _ start = L to the information processing module.
Furthermore, the clock detection module sends a corresponding clock switching control signal to the clock switching module according to the detection result, the clock switching module performs corresponding clock switching according to the clock switching control signal, and sends the switched system clock signal and the control signal to the information processing module, and the method further includes: when the main clock module and the synchronization module both have faults, the clock switching control signal sent by the clock detection module is Sclk _ en = L, rclk _ en = L, mclk _ en = H, the clock switching module switches the system clock to the backup clock, and sends the backup clock signal and the control signal M _ start = L to the information processing module.
Further, the information processing module starts the synchronization module according to the system clock signal, including starting the synchronization module when the system clock signal is a main clock signal or a backup clock signal.
Further, when the control signal is M _ start = H, the information processing module sends the time synchronization information to the backup module; and when the control signal is M _ start = L, acquiring the time synchronization information stored by the backup module.
Further, adjusting the system time of the device according to the time synchronization information to synchronize the time of the device with the time of the superior master device includes:
when the synchronization module has no fault, adjusting the system time of the equipment according to the latest time synchronization information to complete the time synchronization of the equipment and the superior main equipment;
when the synchronization module fails, the system time of the equipment is adjusted according to the plurality of groups of time synchronization information stored in the backup module, and the time synchronization between the equipment and the superior main equipment is continued.
In another aspect, an embodiment of the present invention provides a time synchronization method, including:
setting a backup clock according to the local master clock information;
time synchronization is carried out with the superior main equipment, and time synchronization information in the time synchronization process is stored;
detecting whether a local master clock and a network interface have faults in real time;
when the local master clock fails, switching a system clock into a backup clock, and performing time synchronization with the superior master device;
when the network interface is in fault, switching a system clock into a local main clock, adjusting the system time of the equipment according to the stored multiple groups of time synchronization information, and continuing the time synchronization of the equipment and the superior main equipment;
when the local main clock and the network interface simultaneously fail, the system clock is switched to a backup clock, the system time of the local equipment is adjusted according to the stored multiple groups of time synchronization information, and the time synchronization of the local equipment and the superior main equipment is continued.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. the backup module provides clock backup for the system, and switches the system clock into the backup clock when the main clock fails to ensure the normal operation of the system;
2. the backup module stores the synchronous time information in the dynamic time synchronization process, and when the network synchronization module fails, the system time of the equipment is adjusted through the stored multiple groups of time synchronization information, so that the time synchronization of the equipment and other equipment in the later stage is ensured, and the time synchronization precision of the system is continued to a certain extent.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings, in which like reference numerals refer to like parts throughout, are for the purpose of illustrating particular embodiments only and are not to be considered limiting of the invention.
FIG. 1 is a block diagram of a time synchronization apparatus according to an embodiment of the present invention;
fig. 2 is a flowchart of a time synchronization method according to an embodiment of the present invention.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.
Example one
A specific embodiment of the present invention discloses a time synchronization apparatus, as shown in fig. 1, including:
and the master clock module is used for generating a local master clock.
Specifically, the master clock module is connected with the clock detection module, and the master clock module sends a master clock flag signal to the clock detection module to indicate whether the master clock is valid; the master clock module is also connected with the clock switching module, and when the master clock is effective, the master clock module sends a master clock signal to the clock switching module.
The synchronization module is started by the information processing module and is used for carrying out data communication with the superior main equipment to acquire recovered clock information; and sending the time synchronization information in the communication data to the information processing module.
Specifically, the synchronization module is connected to the clock detection module, and sends a recovered clock flag signal to the clock detection module, which is used to indicate whether the synchronization module has a fault; the synchronization module is also connected with the clock switching module, and when the synchronization module has no fault, the synchronization module acquires recovered clock information after performing data communication with the upper-level main equipment and sends a recovered clock signal to the clock switching module; the synchronization module is also connected with the information processing module and sends time synchronization information sent and received in data communication with the superior main equipment to the information processing module, and the time synchronization information comprises recovered clock frequency information and sent and received timestamp information.
And the backup module is used for backing up the main clock and storing the time synchronization information sent by the information processing module.
The backup module comprises a microprocessor, a memory and a backup clock, wherein the memory is used for storing time synchronization information, the microprocessor is connected with the memory and the backup clock, and is connected with the clock detection module and used for sending a backup clock mark signal to the clock detection module to indicate whether the backup clock is started or not and starting the backup clock according to the control of the clock detection module; the microprocessor is also connected with the clock switching module, and sends a backup clock signal to the clock switching module after the backup clock is started; the microprocessor is also connected with the information processing module, and is used for acquiring the time synchronization information sent by the information processing module, writing the time synchronization information into the memory, or reading the time synchronization information stored by the memory and sending the time synchronization information to the information processing module. In order to facilitate data transmission, the microprocessor and the information processing module are connected by a serial bus interface. The initial parameters of the backup clock are kept consistent with the parameters of the master clock.
And the clock detection module is used for detecting whether the main clock module and the synchronization module have faults or not and sending corresponding clock switching control signals to the clock switching module according to the detection result.
And the clock switching module is used for carrying out corresponding clock switching according to the clock switching control signal and sending the switched system clock signal and the control signal to the information processing module.
The information processing module is used for starting the synchronization module according to the system clock signal; adjusting the system time of the equipment according to the time synchronization information to synchronize the time of the equipment with the time of the superior main equipment; and sending the time synchronization information to a backup module or acquiring a plurality of groups of time synchronization information stored by the backup module according to the control signal.
Specifically, according to different detection results such as whether the main clock is valid, whether the recovery clock is valid, whether the backup clock is started, and the like, the clock switching control signal sent by the clock detection module to the clock switching module includes a main clock enable signal Sclk _ en, a recovery clock enable signal Rclk _ en, and a backup clock enable signal Mclk _ en. The main clock enable signal Sclk _ en, the recovery clock enable signal Rclk _ en and the backup clock enable signal Mclk _ en have H, L states, H indicates that the clock enable signal is valid, and L indicates that the clock enable signal is invalid.
Specifically, when both the master clock module and the synchronization module have no fault, the clock switching control signal sent by the clock detection module is Sclk _ en = H, rclk _ en = H, mclk _ en = L, which indicates that the master clock is valid, the recovery clock is valid, the backup clock is not started, the clock switching module switches the system clock into the recovery clock, and sends the recovery clock signal and the control signal M _ start = H to the information processing module, which indicates that the information processing module is controlled to send time synchronization information to the backup module.
Specifically, when only the master clock module fails, the clock switching control signal sent by the clock detection module is Sclk _ en = L, rclk _ en = H, mclk _ en = H, which indicates that the master clock enable signal is invalid, the recovered clock enable signal is valid, the backup clock is started, the clock switching module switches the system clock to the backup clock, and sends the backup clock signal and the control signal M _ start = H to the information processing module, which indicates that the information processing module is controlled to send the time synchronization information to the backup module.
Specifically, when only the synchronization module fails, the clock switching control signal sent by the clock detection module is Sclk _ en = H, rclk _ en = L, mclk _ en = L, which indicates that the master clock enable signal is valid, the recovered clock enable signal is invalid, the backup clock is not started, the clock switching module switches the system clock to the master clock, and sends the master clock signal and the control signal M _ start = L to the information processing module, which indicates that the control information processing module acquires the stored time synchronization information from the backup module.
Specifically, when both the master clock module and the synchronization module fail, the clock switching control signal sent by the clock detection module is Sclk _ en = L, rclk _ en = L, mclk _ en = H, which indicates that the master clock enable signal is invalid, the recovered clock enable signal is invalid, the backup clock is started, the clock switching module switches the system clock to the backup clock, and sends the backup clock signal and the control signal M _ start = L to the information processing module, which indicates that the information processing module is controlled to acquire the stored time synchronization information from the backup module.
Specifically, the clock switching module sends the switched system clock to the information processing module, and when the system clock signal sent by the clock switching module is a primary clock signal or a backup clock signal, that is, it indicates that the system clock of the current device is not a recovered clock acquired from network communication, the information processing module starts the synchronization module to perform time synchronization.
Specifically, the clock switching module sends a control signal to the information processing module according to a clock switching control signal sent by the clock detection module, and the control information processing module sends time synchronization information to the backup module or reads stored time synchronization information from the backup module.
Specifically, when the recovery clock enable signal Rclk _ en is valid, the clock switching module sends a control signal M _ start = H, which indicates that the information processing module sends the time synchronization information to the backup module; when the recovery clock enable signal Rclk _ en is invalid, the clock switching module sends a control signal M _ start = L, which indicates that the information processing module acquires the time synchronization information stored by the backup module.
Specifically, the information processing module adjusts the system time of the device according to the time synchronization information to synchronize the time of the device with the time of the superior master device, and the method includes:
when the synchronization module has no fault, calculating the phase difference between the equipment and the superior main equipment according to the latest time synchronization information sent by the synchronization module, and adjusting the system time of the equipment according to the phase difference to finish the time synchronization of the equipment and the superior main equipment;
when the synchronization module fails, the system time of the device is adjusted according to the multiple sets of time synchronization information stored in the backup module, the time synchronization between the device and the superior master device is continued, specifically, the system clock frequency of the device is adjusted according to the stored recovery clock frequency, the system time of the device and the system time of the superior master device have the same frequency, the average phase difference between the device and the superior master device is calculated according to the stored multiple sets of timestamp information, the system time of the device is adjusted according to the average phase difference, and the time synchronization between the device and the superior master device is continued. Based on the influence of factors such as circuit, device, environment, the phase place of this equipment and higher level owner equipment is trembled in the minizone, through solving the average value to the multiunit time stamp data that draws, can provide more reliable time stamp information for this equipment under the condition that the real-time network communication data can't be acquireed to the net gape module trouble to the time synchronization of this equipment and higher level owner equipment lasts.
The principle and implementation process of the time synchronization apparatus of the present embodiment are specifically described below with reference to several implementation scenarios.
Condition of normal operation
1) When the time synchronizer is started, the main clock module is started preferentially, the main clock module sends a main clock signal Sclk to the clock switching module, and sends a main clock flag signal Sclk _ flag = H to the clock detection module, which indicates that the main clock is valid, and at this time, the synchronization module and the backup clock are not started, so that the recovery clock flag signal and the backup clock flag are both invalid, and therefore, the recovery clock flag signal sent by the synchronization module to the clock detection module is Rclk _ flag = L, which indicates that the recovery clock is invalid, and the backup clock flag signal sent by the backup module to the clock detection module is Mclk _ flag = L, which indicates that the backup clock is not started;
2) The main clock mark signal, the recovery clock mark signal and the backup clock mark signal detected by the clock detection module are respectively as follows: sclk _ flag = H, rclk _ flag = L, mclk _ flag = L, which indicates that the main clock is valid, the recovered clock is invalid, and the backup clock is not started, and then the clock switching control signal sent by the clock detection module to the clock switching module is: sclk _ en = H, rclk _ en = L, mclk _ en = L, indicating that the primary clock enable signal is active, the recovery clock enable signal is inactive, and the backup clock is not activated. Because the main clock is valid at this time, the backup clock is not started, and the clock detection module sends a control signal M _ back = L to the backup module, which indicates that the backup clock is not started;
3) The clock switching module switches the system clock to the master clock according to the clock switching control signal Sclk _ en = H, rclk _ en = L, mclk _ en = L, and sends the master clock signal clk = Sclk to the information processing module.
4) The information processing module starts the synchronization module to start time synchronization communication with the superior master device according to the received master clock signal, and the time synchronization may adopt an existing time synchronization protocol, for example, IEEE1588 protocol.
5) When the synchronization module works normally, the synchronization module communicates with a main network interface of the superior device, exchanges timestamp messages with the network interface of the superior device to recover a network clock, sends a recovered clock signal clk = Rclk to the clock switching module, and sends a recovered clock flag signal Rclk _ flag = H to the clock detection module, so that the recovered clock is valid; the synchronization module sends the recovered clock frequency information and the timestamp information exchanged with the superior master device to the information processing module;
6) The main clock mark signal, the recovery clock mark signal and the backup clock mark signal detected by the clock detection module are respectively as follows: sclk _ flag = H, rclk _ flag = H, mclk _ flag = L, which indicates that the main clock is valid, the recovered clock is valid, and the backup clock is not started, and then the clock switching control signal sent to the clock switching module is: the method comprises the following steps that (1) a Sclk _ en = H, rclk _ en = H, mclk _ en = L, a main clock enabling signal is effective, a recovery clock enabling signal is effective, a backup clock is not started, the main clock is effective at the moment, the backup clock is not started, and a clock detection module sends a control signal M _ back = L to a backup module to indicate that the backup clock is not started;
7) The clock switching module switches the system clock into a recovered clock Rclk according to a clock switching control signal Sclk _ en = H, rclk _ en = H, mclk _ en = L, and sends the recovered clock signal clk = Rclk to the information processing module; meanwhile, the clock switching module outputs a control signal M _ start = H to the information processing module, and the control signal M _ start = H indicates that the information processing module is controlled to send time synchronization information to the backup module;
8) The method comprises the steps that a recovery clock signal received by an information processing module calculates the phase difference delta t between the system time of the equipment and the system time of superior main equipment according to a formula (1) and the latest time synchronization timestamp information sent by a synchronization module, and adjusts the system time of the equipment according to the phase difference to enable the system time of the equipment to be consistent with the system time phase of the superior main equipment, so that the time synchronization of the equipment and the superior main equipment is completed; and the information processing module writes the recovered clock frequency information and the time synchronization timestamp information sent by the synchronization module into the backup module through the serial bus according to the control signal M _ start = H.
Wherein, T 1 The time when the synchronization module of the device initiates a time synchronization request message to the superior master device is based on the system time of the device; t is 2 The time when the superior master device receives the time synchronization request message is based on the system time of the superior master device; t is 3 The time when the superior master device sends the synchronous response message to the device is based on the system time of the superior master device; t is 4 The time when the device receives the synchronous response message is based on the system time of the device.
A first fault condition: network port fault
1) When the network interface fails and no network data exists or a network recovery clock cannot be obtained, the synchronization module sends a recovery clock flag signal Rclk _ flag = L to the clock detection module, which indicates that the recovery clock is invalid, and at this time, the synchronization module cannot exchange timestamp messages with the network interface of the superior master device;
2) The main clock mark signal, the recovery clock mark signal and the backup clock mark signal detected by the clock detection module are respectively as follows: sclk _ flag = H, rclk _ flag = L, mclk _ flag = L, which indicates that the main clock is valid, the recovered clock is invalid, and the backup clock is not started, and then the clock switching control signal sent by the clock detection module to the clock switching module is: sclk _ en = H, rclk _ en = L, mclk _ en = L, which indicates that the master clock enable signal is valid, the recovery clock enable signal is invalid, and the backup clock is not started;
3) The clock switching module switches the system clock into a master clock Sclk according to a clock switching control signal Sclk _ en = H, rclk _ en = L, mclk _ en = L, and sends a master clock signal clk = Sclk to the information processing module;
4) The information processing module starts a synchronization module according to the received main clock signal, the synchronization module cannot normally work due to network interface failure, a recovered clock is invalid, and the synchronization module continuously sends a recovered clock invalid flag signal Rclk _ flag = L to the clock detection module; the clock detection module continuously sends a clock switching control signal Sclk _ en = H, rclk _ en = L, mclk _ en = L to the clock switching module, which indicates that the main clock is valid, the recovery clock is invalid, and the backup clock is not started;
5) The clock switching module continuously receives a switching signal Sclk _ en = H, rclk _ en = L, mclk _ en = L in a certain time range, and judges that the synchronization module is in failure, at this time, a control signal M _ start = L is output to the information processing module to indicate that the information processing module acquires time synchronization information stored by the backup module, the information processing module reads n (n is more than or equal to 3) groups of time synchronization information stored in the backup module through a serial bus, frequency division or frequency multiplication is performed on the system clock frequency according to recovery clock frequency information in the time synchronization information, so that the system clock and the recovery clock in normal operation have the same frequency, the system time of the device is enabled to have the same frequency as that of the superior main device, an average phase difference Deltat between the system time of the device and the system time of the superior main device is calculated based on a formula (2) according to multiple groups of time stamp information in the time synchronization information, and the average phase difference of the system time of the device and the superior main device is adjusted according to enable the system time phase of the superior main device to be consistent.
Wherein, T i1 The time when the synchronization module of the device initiates a time synchronization request message to the superior master device in the ith time synchronization is based on the system time of the device; t is i2 The time when the superior master device receives the time synchronization request message in the ith time synchronization is based on the system time of the superior master device; t is i3 The time when the superior master device sends the synchronous response message to the device in the ith time synchronization is based on the system time of the superior master device; t is a unit of i4 For reception by the apparatus in the ith time synchronizationAnd the time of synchronizing the response message is based on the system time of the equipment.
And (2) fault condition two: master clock failure
1) When the master clock module fails, the output master clock signal is invalid, and the master clock module sends a master clock flag signal Sclk _ flag = L to the clock detection module to indicate that the master clock is invalid;
2) The main clock mark signal, the recovery clock mark signal and the backup clock mark signal detected by the clock detection module are respectively as follows: sclk _ flag = L, rclk _ flag = H, mclk _ flag = L, which indicates that the main clock is invalid, the recovered clock is valid, and the backup clock is not started, and because the main clock module fails, the synchronization module cannot normally operate, and therefore, the fast recovered clock signal is also invalid, the recovered clock flag signal sent by the synchronization module to the clock detection module is Rclk _ flag = L, which indicates that the recovered clock is invalid, and the main clock flag signal, the recovered clock flag signal, and the backup clock flag signal detected by the clock detection module are Sclk _ flag = L, rclk _ flag = L, mclk _ flag = L, which indicates that the main clock is invalid, the recovered clock is invalid, and the backup clock is not started, and because the main clock is invalid and the backup clock is not started at this time, the clock detection module sends a control signal M _ back = H to the backup module for starting the backup clock;
3) The backup module starts a backup clock according to the control signal M _ back = H, sends a backup clock flag signal Mclk _ flag = H to the clock detection module, indicates that the backup clock is started, and sends a backup clock signal Mclk to the clock switching module;
4) The main clock mark signal, the recovery clock mark signal and the backup clock mark signal detected by the clock detection module are respectively as follows: the clock detection module sends a clock switching control signal to the clock switching module, wherein the clock switching control signal is Sclk _ en = L, rclk _ en = L, mclk _ en = H, and indicates that the main clock enable signal is invalid, the recovery clock enable signal is invalid, and the backup clock is started;
5) The clock switching module switches a system clock into a backup clock Mclk according to a clock switching control signal Sclk _ en = L, rclk _ en = L, mclk _ en = H, and sends the backup clock signal clk = Mclk to the information processing module;
6) The information processing module starts a synchronization module to start time synchronization communication with the superior master device according to the received backup clock signal, and the time synchronization can adopt the existing time synchronization protocol, such as an IEEE1588 protocol;
7) When the synchronization module works normally, the synchronization module communicates with a main network interface of the superior device, exchanges timestamp messages with the network interface of the superior device to recover a network clock, sends a recovered clock signal clk = Rclk to the clock switching module, and sends a recovered clock flag signal Rclk _ flag = H to the clock detection module, so that the recovered clock is valid; the synchronization module sends the recovered clock frequency information and the timestamp information exchanged with the superior master device to the information processing module;
8) The main clock mark signal, the recovery clock mark signal and the backup clock mark signal detected by the clock detection module are respectively as follows: sclk _ flag = L, rclk _ flag = H, mclk _ flag = H, which indicates that the main clock is invalid, the recovered clock is valid, the backup clock is started, and the clock switching control signal sent by the clock detection module to the clock switching module is: sclk _ en = L, rclk _ en = H, mclk _ en = H, which indicates that the main clock enable signal is invalid, the recovery clock enable signal is valid, and the backup clock is started;
9) The clock switching module switches the system clock into a recovered clock Rclk according to a clock switching control signal Sclk _ en = L, rclk _ en = H, mclk _ en = H, and sends the recovered clock signal clk = Rclk to the information processing module; meanwhile, the clock switching module outputs a control signal M _ start = H to the information processing module, and the control signal M _ start = H indicates that the information processing module is controlled to send time synchronization information to the backup module;
10 The recovery clock signal received by the information processing module, according to the latest time synchronization timestamp information sent by the synchronization module, calculating the phase difference delta t between the equipment and the superior master equipment according to the formula (1), and adjusting the system time of the equipment according to the phase difference to make the system time of the equipment consistent with the system time phase of the superior master equipment, so as to complete the time synchronization between the equipment and the superior master equipment; and the information processing module writes the recovered clock frequency information and the time synchronization timestamp information sent by the synchronization module into the backup module through the serial bus according to the control signal M _ start = H.
And (3) failure three: failure of both master clock and network port
1) When the main clock module and the network interface module both have faults, the output main clock signal and the network recovery clock signal are invalid, the main clock flag signal sent to the clock detection module by the main clock module is Sclk _ flag = L to indicate that the main clock is invalid, and the recovery clock flag signal sent to the clock detection module by the synchronization module is Rclk _ flag = L to indicate that the recovery clock is invalid;
2) The clock detection module detects that a main clock flag signal, a recovery clock flag signal and a backup clock flag signal are respectively Sclk _ flag = L, rclk _ flag = L, mclk _ flag = L, which indicates that the main clock is invalid, the recovery clock is invalid and the backup clock is not started;
3) The backup module starts a backup clock according to the control signal M _ back = H, sends a backup clock flag signal Mclk _ flag = H to the clock detection module, indicates that the backup clock is started, and sends a backup clock signal Mclk to the clock switching module;
4) The main clock mark signal, the recovery clock mark signal and the backup clock mark signal detected by the clock detection module are respectively as follows: if the clock detection module sends a clock switching control signal to the clock switching module, which is Sclk _ en = L, rclk _ en = L, mclk _ en = H, to indicate that the main clock enable signal is invalid, the recovery clock enable signal is invalid, and the backup clock is started, the Sclk _ flag = L, rclk _ flag = L, mclk _ flag = H;
5) The clock switching module switches the system clock into a backup clock Mclk according to a clock switching control signal Sclk _ en = L, rclk _ en = L, mclk _ en = H, and sends the backup clock signal clk = Mclk to the information processing module;
6) The information processing module starts a synchronization module according to the received backup clock signal, the synchronization module cannot normally work due to the fault of a network interface, a recovered clock is invalid, and the synchronization module continuously sends a recovered clock invalid flag signal Rclk _ flag = L to the clock detection module; the clock detection module continuously sends a clock switching control signal Sclk _ en = L, rclk _ en = L, mclk _ en = H to the clock switching module;
7) The clock switching module continuously receives a clock switching control signal Sclk _ en = L, rclk _ en = L, mclk _ en = H in a certain time range, and judges that the synchronization module is in fault, and at the moment, outputs a control signal M _ start = L to the information processing module to indicate that the information processing module is controlled to acquire time synchronization information stored by the backup module;
8) The information processing module reads n (n is more than or equal to 3) groups of time synchronization information stored in the backup module through a serial bus according to the control signal M _ start = L, frequency division or frequency multiplication is carried out on the system clock frequency according to recovery clock frequency information in the time synchronization information, so that the system clock and a recovery clock in normal work have the same frequency, the system time of the equipment and the system time of superior main equipment have the same frequency, the average phase difference delta t between the system time of the equipment and the system time of the superior main equipment is calculated according to a formula (2) according to a plurality of groups of time stamp information in the time synchronization information, the system time of the equipment is adjusted according to the average phase difference, the system time phase of the equipment and the system time phase of the superior main equipment are consistent, and the time synchronization of the equipment and the superior main equipment is continued.
Compared with the prior art, the time synchronization device provided by the embodiment has the following advantages:
1. the backup module of the embodiment provides clock backup for the system, and switches the system clock into the backup clock when the main clock fails to work, so as to ensure the normal operation of the system;
2. the backup module of this embodiment stores the synchronization time information in the dynamic time synchronization process, and when the network synchronization module fails, the backup module adjusts the system clock frequency of the local device by reading the stored recovery clock frequency information during normal operation and multiple sets of time synchronization data, so that the system clock of the local device has the same frequency as that of the superior master device, calculates the average phase difference between the local device and the superior master device, and adjusts the system time of the local device, thereby ensuring the time synchronization between the local device and other devices at the posterior level, and extending the time synchronization accuracy of the system to a certain extent.
Example two
A specific embodiment of the present invention discloses a time synchronization method, as shown in fig. 2, including:
s1, setting a backup clock according to local master clock information, wherein the specific setting process is as shown in embodiment I and is not repeated here.
And S2, performing time synchronization with the superior master device, and storing time synchronization information in the time synchronization process, wherein the principle and process of time synchronization with the superior master device are specifically referred to as first embodiment, and are not repeated here.
And S3, detecting whether the local master clock and the network interface are in fault in real time, wherein the specific detection mode is described in the first embodiment, and is not repeated here.
And S4, when the local master clock fails, switching the system clock into a backup clock, and performing time synchronization with the superior master device, wherein the specific process of performing clock switching and time synchronization refers to the first embodiment, and is not repeated here.
And S5, when the network interface fails, switching the system clock to a local master clock, adjusting the system time of the device according to the stored multiple groups of time synchronization information, and continuing the time synchronization between the device and a superior master device.
And S6, when the local master clock and the network interface simultaneously fail, switching the system clock into a backup clock, adjusting the system time of the local device according to the stored multiple groups of time synchronization information, continuing the time synchronization of the local device and the superior master device, wherein the specific process of clock switching and time synchronization refers to the first embodiment, which is not repeated here.
Those skilled in the art will appreciate that all or part of the processes for implementing the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, for instructing the relevant hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (8)
1. A time synchronization apparatus, comprising:
a master clock module for generating a local master clock;
the synchronization module is started by the information processing module and is used for carrying out data communication with the superior main equipment to acquire recovered clock information; sending time synchronization information in the communication data to an information processing module;
the backup module is used for backing up the main clock and storing the time synchronization information sent by the information processing module;
the clock detection module is used for detecting whether the main clock module and the synchronization module have faults or not and sending corresponding clock switching control signals to the clock switching module according to the detection result;
the clock switching module is used for carrying out corresponding clock switching according to the clock switching control signal and sending a switched system clock signal and a control signal to the information processing module;
the information processing module is used for starting the synchronization module according to the system clock signal; adjusting the system time of the equipment according to the time synchronization information to synchronize the time of the equipment with the time of the superior main equipment; according to the control signal, sending the time synchronization information to a backup module or acquiring a plurality of groups of time synchronization information stored by the backup module;
the master clock module is connected with the clock detection module and sends a master clock mark signal to the clock detection module to indicate whether the master clock is effective or not; the master clock module is also connected with the clock switching module, and when the master clock is effective, the master clock module sends a master clock signal to the clock switching module;
the clock switching control signals comprise a main clock enabling signal Sclk _ en, a recovery clock enabling signal Rclk _ en and a backup clock enabling signal Mclk _ en;
when the main clock module and the synchronization module both have faults, the clock switching control signal sent by the clock detection module is Sclk _ en = L, rclk _ en = L, mclk _ en = H, the clock switching module switches the system clock to the backup clock, and sends the backup clock signal and the control signal M _ start = L to the information processing module.
2. The apparatus according to claim 1, wherein the clock detecting module sends a corresponding clock switching control signal to the clock switching module according to the detection result, and the clock switching module performs corresponding clock switching according to the clock switching control signal, and sends the switched system clock signal and the control signal to the information processing module, and the apparatus comprises: when both the master clock module and the synchronization module have no fault, the clock switching control signal sent by the clock detection module is Sclk _ en = H, rclk _ en = H, mclk _ en = L, the clock switching module switches the system clock into the recovered clock, and sends the recovered clock signal and the control signal M _ start = H to the information processing module.
3. The apparatus according to claim 1, wherein the clock detection module sends a corresponding clock switching control signal to the clock switching module according to the detection result, and the clock switching module performs corresponding clock switching according to the clock switching control signal, and sends the switched system clock signal and the control signal to the information processing module, further comprising: when only the main clock module fails, the clock switching control signal sent by the clock detection module is Sclk _ en = L, rclk _ en = H, mclk _ en = H, the clock switching module switches the system clock into the backup clock, and sends the backup clock signal and the control signal M _ start = H to the information processing module.
4. The apparatus according to claim 1, wherein the clock detection module sends a corresponding clock switching control signal to the clock switching module according to the detection result, and the clock switching module performs corresponding clock switching according to the clock switching control signal, and sends the switched system clock signal and the control signal to the information processing module, further comprising: when only the synchronization module fails, the clock switching control signal sent by the clock detection module is Sclk _ en = H, rclk _ en = L, mclk _ en = L, the clock switching module switches the system clock to the master clock, and sends the master clock signal and the control signal M _ start = L to the information processing module.
5. The time synchronizer of any one of claims 2-4, wherein the information processing module activates the synchronization module based on the system clock signal, including activating the synchronization module when the system clock signal is a master clock signal or a backup clock signal.
6. The time synchronizer of any one of claims 2-4, wherein when the control signal is M _ start = H, the information processing module sends the time synchronization information to the backup module; and when the control signal is M _ start = L, acquiring the time synchronization information stored by the backup module.
7. The apparatus according to claim 1, wherein the adjusting of the system time of the local device based on the time synchronization information to synchronize the time of the local device with the time of the upper level master device includes:
when the synchronization module has no fault, adjusting the system time of the equipment according to the latest time synchronization information to complete the time synchronization of the equipment and the superior main equipment;
when the synchronization module fails, the system time of the equipment is adjusted according to the plurality of groups of time synchronization information stored in the backup module, and the time synchronization between the equipment and the superior main equipment is continued.
8. A time synchronization method applied to the time synchronization apparatus of claim 1, the method comprising:
setting a backup clock according to local master clock information;
time synchronization is carried out with the superior main equipment, and time synchronization information in the time synchronization process is stored;
detecting whether a local master clock and a network interface have faults in real time;
when the local master clock fails, switching a system clock into a backup clock, and carrying out time synchronization with a superior master device;
when the network interface is in fault, switching a system clock into a local main clock, adjusting the system time of the equipment according to the stored multiple groups of time synchronization information, and continuing the time synchronization of the equipment and the superior main equipment;
and when the local main clock and the network interface simultaneously fail, switching the system clock into a backup clock, adjusting the system time of the equipment according to the stored multiple groups of time synchronization information, and continuing the time synchronization of the equipment and the superior main equipment.
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| CN115190577B (en) * | 2022-05-11 | 2023-10-13 | 四川创智联恒科技有限公司 | ORAN system time sequence synchronization mutual backup method |
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