CN112436914B - Method and system for protecting master and slave 5G ultrahigh-precision clocks - Google Patents
Method and system for protecting master and slave 5G ultrahigh-precision clocks Download PDFInfo
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
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- H—ELECTRICITY
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- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
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- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
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Abstract
The invention discloses a method and a system for protecting a master clock and a slave clock of 5G ultrahigh precision, which relate to the technical field of communication. At a time delay feedback receiving end, a preset learning algorithm is matched to further predict the next phase difference, phase compensation is carried out in advance at the current standby single disk, high-precision phase synchronization between the main single disk and the standby single disk is realized, the phase difference is less than 1ns, and the problems of overlarge short-term phase jump index, service jump seconds and the like in the dynamic state of main and standby switching are solved.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a method and a system for protecting a master 5G ultrahigh-precision clock.
Background
IEEE (Institute of Electrical and Electronics Engineers ) organizes to complete the revision of 1588V2 version in 2007, IEEE 1588 is a Precision clock synchronization Protocol standard of a network measurement and control system, and Precision can reach microsecond level by using a PTP (Precision Time Protocol) Protocol. The purpose of this standard is to accurately synchronize the measurement with a separate, independently running clock in the control system. The generation of the fifth generation mobile communication technology further improves the synchronization indexes of time and clock, such as the precision requirement of the time stamp, which is reduced from 8ns in the 4G era to 4ns or even smaller.
As shown in fig. 1, currently, most communication devices adopt a primary-standby protection strategy, and when a primary single disk fails, a primary single disk can be quickly switched to a standby single disk, while main services should not be affected.
The prior method has the following defects:
in the field of clock synchronization, when the master and the slave are switched, if two master control devices give reference clocks to a downstream single disk and phase difference exists, phase jump of the clocks can be caused, a downstream phase-locked loop is caused, and longer time is needed for locking the reference clocks.
In the time synchronization field, if the phases of the timestamps of the main and standby devices are not aligned, the timestamps are staggered after the main and standby switches. For the 5G environment, in the field of securities or banks and other occasions where a high-precision time server is needed, if a main/standby protection scheme exists, the timestamps of main/standby single disks are not aligned in high-precision phase when switching between main/standby, and the timestamps are misplaced, so that two parties processing the same transaction have second skip at the current time.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method and a system for protecting a master clock and a slave clock of a 5G ultrahigh-precision clock, which ensure the dynamic stability of a time synchronization system and avoid the phenomena of clock phase jump and service disk time jump second caused by master and slave switching.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: a master and slave protection method for a 5G ultrahigh-precision clock comprises the following steps:
during wiring, the wiring lengths of the measurement sending circuit and the measurement feedback circuit are set to be equal;
after the system distinguishes the main single disk and the standby single disk, the phase difference between a measurement sending line and a measurement feedback line is calculated at the current main single disk, the phase difference is divided by 2 to obtain one-way time delay, and the one-way time delay is sent to the current standby single disk;
and storing the one-way time delay received by the current standby single disk into the FPGA, calculating the time delay change trend by adopting a preset learning algorithm, calculating the next time delay according to the time delay change trend, and compensating the next time delay to the output clock of the standby single disk in advance.
On the basis of the scheme, a preset learning algorithm is adopted to calculate the time delay change trend, and the next time delay is calculated according to the time delay change trend, and the method specifically comprises the following steps:
obtaining the (n-2) th unidirectional time delay, the (n-1) th unidirectional time delay and the nth unidirectional time delay, wherein n is an integer larger than 2;
calculating the time delay change trend to be the difference value between the (n-1) th unidirectional time delay and the (n-2) th unidirectional time delay;
and (4) calculating the (n + 1) th unidirectional delay according to the delay variation trend, wherein the (n + 1) th unidirectional delay is equal to the nth unidirectional delay + (the difference between the (n-1) th unidirectional delay and the (n-2) th unidirectional delay).
On the basis of the scheme, the measurement sending circuit is the sum of the routing length of the clock bus from the current main single disk to the backplane bus, the routing length of the backplane bus and the routing length of the clock bus from the backplane bus to the current standby single disk;
the measurement feedback line is the sum of the clock bus line length from the current standby single disk to the backplane bus, the line length of the backplane bus and the length of the clock bus line length from the backplane bus to the current main single disk.
On the basis of the scheme, the method for calculating the phase difference between the measurement sending line and the measurement feedback line at the current main single disk specifically comprises the following steps
And inputting the feedback input clock of the measurement bus and the sending clock of the measurement bus into the phase discrimination unit, and calculating the phase difference.
On the basis of the scheme, the method further comprises the following steps: compensating the next time delay to the output clock of the standby single disk in advance, judging whether the main/standby switching occurs, if so, after the main/standby single disks are distinguished by the system, calculating the time delay by the switched main/standby single disks; if not, the current main single disk and the current standby single disk are continuously adopted to set the calculation time delay.
The invention also provides a 5G ultrahigh-precision clock master-slave protection system, which comprises:
a trace length setting module for: setting the equal wiring lengths of the measurement sending circuit and the measurement feedback circuit through wiring software;
a delay calculation module to: after the system distinguishes the main single disk and the standby single disk, the phase difference between a measurement sending line and a measurement feedback line is calculated at the current main single disk, the phase difference is divided by 2 to obtain one-way time delay, and the one-way time delay is sent to the current standby single disk;
a delay compensation module to: and storing the one-way time delay received by the current standby single disk into the FPGA, calculating the time delay change trend by adopting a preset learning algorithm, calculating the next time delay according to the time delay change trend, and compensating the next time delay to the output clock of the standby single disk in advance.
On the basis of the scheme, the time delay compensation module calculates the time delay change trend by adopting a preset learning algorithm, and calculates the next time delay according to the time delay change trend, and the method specifically comprises the following steps:
obtaining the (n-2) th unidirectional time delay, the (n-1) th unidirectional time delay and the nth unidirectional time delay, wherein n is an integer larger than 2;
calculating the time delay change trend to be the difference value of the (n-1) th one-way time delay and the (n-2) th one-way time delay;
and (4) calculating the (n + 1) th unidirectional delay according to the delay variation trend, wherein the (n + 1) th unidirectional delay is equal to the nth unidirectional delay + (the difference between the (n-1) th unidirectional delay and the (n-2) th unidirectional delay).
On the basis of the scheme, the measurement sending line is the sum of the clock bus routing length from the current main single disk to the backplane bus, the routing length of the backplane bus and the length of the clock bus routing length from the backplane bus to the current standby single disk;
the measurement feedback line is the sum of the clock bus line length from the current standby single disk to the backplane bus, the line length of the backplane bus and the length of the clock bus line length from the backplane bus to the current main single disk.
On the basis of the above scheme, the time delay calculation module calculates the phase difference between the measurement transmission line and the measurement feedback line at the current master single disk, and specifically includes the following steps
And inputting the feedback input clock of the measurement bus and the sending clock of the measurement bus into the phase discrimination unit, and calculating the phase difference.
On the basis of the above scheme, the delay calculation module is further configured to: the time delay compensation module compensates the next time delay to the output clock of the standby single disk in advance, judges whether the master-slave switching occurs, if yes, calculates the time delay by the switched master single disk and standby single disk after the master-slave single disk is distinguished by the system; if not, the current main single disk and the current standby single disk are continuously adopted to set the calculation time delay.
Compared with the prior art, the invention has the advantages that:
in a TC (Transparent clock) model of 1588V2 of equipment, the invention sets equal routing lengths of a measurement sending circuit and a measurement feedback circuit during wiring so as to obtain accurate unilateral line delay. At a time delay feedback receiving end, a preset learning algorithm is matched to further predict the next phase difference, phase compensation is carried out in advance at the current standby single disk, high-precision phase synchronization between the main single disk and the standby single disk is realized, the phase difference is less than 1ns, and the problems of overlarge short-term phase jump index, service jump seconds and the like in the dynamic state of main and standby switching are solved.
Drawings
Fig. 1 is a main/standby system architecture of a communication device in the background art;
fig. 2 is a schematic diagram illustrating a timestamp processing principle of IEEE 1588V2 according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the TC model defined by IEEE 1588V2 according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a line delay measurement bus according to an embodiment of the present invention;
fig. 5 is a schematic flowchart of a 5G master/slave ultra-high-precision clock protection method according to an embodiment of the present invention;
fig. 6 is a schematic diagram of line delay measurement of a 5G ultrahigh-precision clock master/slave protection method according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a principle that learning algorithm is applied to advance compensation at the standby main control disk side in the 5G ultrahigh-precision clock main/standby protection method according to the embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
In the embodiment of the invention, in the TC model of 1588V2 of equipment, the lengths of the routing of a measurement sending line and a measurement feedback line are set to be equal during wiring so as to obtain accurate unilateral line delay. At a time delay feedback receiving end, a preset learning algorithm is matched to further predict the next phase difference, phase compensation is carried out in advance at the current standby single disk, high-precision phase synchronization between the main single disk and the standby single disk is realized, the phase difference is less than 1ns, and the problems of overlarge short-term phase jump index, service jump seconds and the like in the dynamic state of main and standby switching are solved.
Referring to fig. 2, the 1588V2 timestamp is processed at point a, the NTP timestamp is processed at point C, and the uncertain delay of a-C causes the error of NTP (Network Time Protocol) to reach tens of milliseconds, so that compared with NTP, 1588V2 greatly improves the accuracy of Time information recovery.
As shown in fig. 3, the TC model calculates the residence time introduced by the intermediate network device, so as to implement accurate time synchronization between the master and the slave, and process the master-slave timestamp phase difference, that is, process in the TC model.
The embodiment of the invention provides a 5G ultrahigh-precision clock master-slave protection method, which comprises the following steps:
during wiring, the wiring lengths of the measurement sending circuit and the measurement feedback circuit are set to be equal;
after the system distinguishes the main single disk and the standby single disk, the phase difference between a measurement sending line and a measurement feedback line is calculated at the current main single disk, the phase difference is divided by 2 to obtain one-way time delay, and the one-way time delay is sent to the current standby single disk;
the one-way time delay received by the current standby single disk is stored in an FPGA (Field Programmable Gate Array), a preset learning algorithm is adopted to calculate the time delay change trend, the next time delay is calculated according to the time delay change trend, and the next time delay is compensated to the output clock of the standby single disk in advance.
As a preferred embodiment, a preset learning algorithm is adopted to calculate a time delay variation trend, and the next time delay is calculated according to the time delay variation trend, which specifically includes the following steps:
obtaining the (n-2) th unidirectional time delay, the (n-1) th unidirectional time delay and the nth unidirectional time delay, wherein n is an integer larger than 2;
calculating the time delay change trend to be the difference value of the (n-1) th one-way time delay and the (n-2) th one-way time delay;
and (4) calculating the (n + 1) th unidirectional delay according to the delay variation trend, wherein the (n + 1) th unidirectional delay is equal to the nth unidirectional delay + (the difference between the (n-1) th unidirectional delay and the (n-2) th unidirectional delay).
As a preferred embodiment, the measurement transmission line is the sum of the routing length of the clock bus from the current master single disk to the backplane bus, the routing length of the backplane bus, and the routing length of the clock bus from the backplane bus to the current spare single disk;
the measurement feedback line is the sum of the clock bus line length from the current standby single disk to the backplane bus, the line length of the backplane bus and the length of the clock bus line length from the backplane bus to the current main single disk.
As a preferred embodiment, the method for calculating the phase difference between the measurement sending line and the measurement feedback line at the current master single disk specifically includes the following steps:
and inputting the feedback input clock of the measurement bus and the sending clock of the measurement bus into the phase discrimination unit, and calculating the phase difference.
As a preferred embodiment, the method further comprises the steps of: compensating the next time delay to the output clock of the standby single disk in advance, judging whether the main/standby switching occurs, if so, after the main/standby single disks are distinguished by the system, calculating the time delay by the switched main/standby single disks; if not, the current main single disk and the current standby single disk are continuously adopted to set the calculation time delay.
As shown in fig. 4, when wiring, the lengths of the measurement transmission lines and the measurement feedback lines are set to be equal, and the specific implementation manner is as follows:
when A is the main disc:
measuring a transmission line: the A disc sends a measurement clock to a backplane bus 1 through L1 and sends the measurement clock to a B (standby disc) through L2 routing;
a measurement feedback line: the B disk feeds back the clock to the backplane bus 2 through L3 and feeds back to A (main disk) through L4 routing;
when B is the main disk:
measuring a transmission line: the B disk sends a measurement clock to the backplane bus 2 through L3 and sends the measurement clock to A (spare disk) through L4 routing;
a measurement feedback line: the A disk feeds back the clock to the backplane bus 1 through L1 and feeds back to the B (main disk) through L2 routing;
the (L1+ L2+ backplane bus 1) trace length (L3+ L4+ backplane bus 2) is required
The actual compensation is the single edge delay between the a and B disks, which is 1/2 times the loop delay measured in the above figure.
A specific implementation manner of the active/standby 5G ultrahigh-precision clock protection method according to the embodiment of the present invention is as shown in fig. 5, and specifically includes the following steps:
firstly, after the system is powered on, waiting for the system to distinguish the main and standby disks, waiting for the clock state of the standby disk to LOCK the main disk, and feeding back a LOCK state indication.
Secondly, at the current main single disk, as shown in fig. 5, a feedback input clock (MES _ FB in the figure) of the measurement bus and a sending clock (MES _ TX in the figure) of the measurement bus are input into the phase discrimination unit for comparison, and the phase discrimination unit can achieve the accuracy of 1ps at present. The deviation of the phase difference actually obtained should be within 5ps, taking into account the capacitive factors at the various interfaces.
The phase deviation at this time includes a full path deviation: routing delay, transceiver delay, backplane connector delay. And the receiving and transmitting directions are bidirectional, and on the premise of mirror image processing in the receiving and transmitting directions, the deviation in the second step can be directly divided by 2 to obtain unidirectional time delay, namely the phase difference between the two single disks. And sending the deviation to the standby disk through a communication bus between the main disk and the standby disk.
And fourthly, at the moment, the sight line is transferred to the spare disc side, the phase deviation sent from the back plate is stored in a spare single-board FPGA, a learning algorithm is added into the FPGA, and as shown in the figure 6, for example, if the n-2 measurement time delay is 3ns, the n-1 time delay is 3.2ns, and the n measurement time delay is 3.4ns, the n +1 time delay is judged to be 3.6ns in advance, and the n +1 time delay is written into a phase control register of the spare disc in advance to compensate the deviation in advance. The accuracy of the final compensation output depends on the frequency of a local VCO (Voltage-controlled oscillator), for example, if a PLL chip uses a 4GHz VCO, the adjustment step value of the output delay is 0.25ns per step. The example of the delay shown in fig. 6 is an application of reference clock synchronization of timestamps in the TC model 1588v2, so that the 1pps timestamps between the master and slave are also phase aligned.
And fifthly, according to the above, the final synchronization precision also depends on three points:
1. the VCO frequency point of a PLL (Phase Locked Loop) chip is usually around 3GHz at present, and can reach an adjustment accuracy of 0.33 ns;
2. as shown in fig. 7, the symmetry of the line delay measurement path further shows the accuracy of equal length of the traces (which can be controlled to ± 10 mils and can be ignored at present), and the characteristic of the deviation (part to part skew) between the devices of the transceivers between the host and the spare disks, taking the MLVDS transceiver SN65MLVD040 of TI as an example, the part to part skew can be up to 0.3 ns.
3. The accuracy that the learning algorithm can reach is theoretically the time delay index that can be measured actually, and further optimization. If 3ns is measured, the actual precision is 3 +/-0.2 ns, and the accuracy can be optimized to be 3 +/-0.1 ns through a learning algorithm.
The embodiment of the invention provides a 5G ultrahigh-precision clock master-slave protection system, which comprises:
a trace length setting module for: setting the equal wiring lengths of the measurement sending circuit and the measurement feedback circuit through wiring software;
a latency calculation module to: after the system distinguishes the main single disk and the standby single disk, the phase difference between a measurement sending line and a measurement feedback line is calculated at the current main single disk, the phase difference is divided by 2 to obtain one-way time delay, and the one-way time delay is sent to the current standby single disk;
a delay compensation module to: and storing the one-way time delay received by the current standby single disk into the FPGA, calculating the time delay change trend by adopting a preset learning algorithm, calculating the next time delay according to the time delay change trend, and compensating the next time delay to the output clock of the standby single disk in advance.
As a preferred embodiment, the delay compensation module calculates a delay variation trend by using a preset learning algorithm, and calculates the next time delay according to the delay variation trend, specifically including the following steps:
obtaining the (n-2) th unidirectional time delay, the (n-1) th unidirectional time delay and the nth unidirectional time delay, wherein n is an integer larger than 2;
calculating the time delay change trend to be the difference value of the (n-1) th one-way time delay and the (n-2) th one-way time delay;
and (4) calculating the (n + 1) th unidirectional delay according to the delay variation trend, wherein the (n + 1) th unidirectional delay is the nth unidirectional delay + (the difference between the (n-1) th unidirectional delay and the (n-2) th unidirectional delay).
As a preferred embodiment, the measurement sending line is the sum of the clock bus routing length from the current master single disk to the backplane bus, the routing length of the backplane bus, and the length of the clock bus routing length from the backplane bus to the current standby single disk;
the measurement feedback line is the sum of the clock bus line length from the current standby single disk to the backplane bus, the line length of the backplane bus and the length of the clock bus line length from the backplane bus to the current main single disk.
As a preferred embodiment, the time delay calculating module calculates the phase difference between the measurement sending line and the measurement feedback line at the current master single disk, and specifically includes the following steps
And inputting the feedback input clock of the measurement bus and the sending clock of the measurement bus into the phase discrimination unit, and calculating the phase difference.
As a preferred embodiment, the time delay calculation module is further configured to: the time delay compensation module compensates the next time delay to the output clock of the standby single disk in advance, judges whether the main/standby switching occurs, and calculates the time delay by the switched main single disk and standby single disk after the system distinguishes the main/standby single disk if the main/standby switching occurs; if not, the current main single disk and the current standby single disk are continuously adopted to set the calculation time delay.
Based on the same inventive concept, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements all or part of method steps of a 5G ultra-high precision clock active/standby protection method.
The invention realizes all or part of the processes in the 5G ultrahigh-precision clock master-slave protection method, and can also be completed by instructing related hardware through a computer program, wherein the computer program can be stored in a computer readable storage medium, and the steps of the method embodiments can be realized when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program running on the processor, and the processor implements all or part of method steps in the 5G ultrahigh-precision clock active/standby protection method when executing the computer program.
The processor may be a Central Processing Unit (CP U), or may be other general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the computer device and the various interfaces and lines connecting the various parts of the overall computer device.
The memory may be used to store computer programs and/or modules, and the processor may implement various functions of the computer device by executing or executing the computer programs and/or modules stored in the memory, as well as by invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, video data, etc.) created according to the use of the cellular phone, etc. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, server, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), servers and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A master and slave protection method for a 5G ultrahigh-precision clock is characterized by comprising the following steps:
during wiring, the wiring lengths of the measurement sending circuit and the measurement feedback circuit are set to be equal;
after the system distinguishes the main single disk and the standby single disk, the phase difference between a measurement sending line and a measurement feedback line is calculated at the current main single disk, the phase difference is divided by 2 to obtain one-way time delay, and the one-way time delay is sent to the current standby single disk;
storing the one-way time delay received by the current standby single disk into the FPGA, calculating a time delay change trend by adopting a preset learning algorithm, calculating the next time delay according to the time delay change trend, and compensating the next time delay to an output clock of the standby single disk in advance;
calculating the phase difference between a measurement sending line and a measurement feedback line at the current main single disk, which specifically comprises the following steps:
and inputting the feedback input clock of the measurement bus and the sending clock of the measurement bus into the phase discrimination unit, and calculating the phase difference.
2. The method of claim 1, wherein a predetermined learning algorithm is used to calculate a time delay variation trend, and a next time delay is calculated according to the time delay variation trend, and the method specifically comprises the following steps:
obtaining the (n-2) th unidirectional time delay, the (n-1) th unidirectional time delay and the nth unidirectional time delay, wherein n is an integer larger than 2;
calculating the time delay change trend to be the difference value between the (n-1) th unidirectional time delay and the (n-2) th unidirectional time delay;
and (4) calculating the (n + 1) th unidirectional time delay according to the time delay change trend, wherein the (n + 1) th unidirectional time delay = the (n-1) th unidirectional time delay + (the difference between the (n-1) th unidirectional time delay and the (n-2) th unidirectional time delay).
3. The method of claim 1, wherein the measurement transmission line is a sum of a clock bus routing length from a current master single disk to a backplane bus, a routing length of the backplane bus, and a length of a clock bus routing length from the backplane bus to a current standby single disk;
the measurement feedback line is the sum of the clock bus line length from the current standby single disk to the backplane bus, the line length of the backplane bus and the length of the clock bus line length from the backplane bus to the current main single disk.
4. The method of claim 1, further comprising the steps of: compensating the next time delay to the output clock of the standby single disk in advance, judging whether the main/standby switching occurs, if so, after the main/standby single disks are distinguished by the system, calculating the time delay by the switched main/standby single disks; if not, the current main single disk and the current standby single disk are continuously adopted to set the calculation time delay.
5. A5G ultrahigh precision clock active-standby protection system is characterized by comprising:
a trace length setting module for: setting equal wiring lengths of a measurement sending circuit and a measurement feedback circuit through wiring software;
a delay calculation module to: after the system distinguishes the master single disk and the standby single disk, calculating the phase difference between a measurement sending line and a measurement feedback line at the current master single disk, dividing the phase difference by 2 to obtain one-way time delay, and sending the one-way time delay to the current standby single disk;
a delay compensation module to: storing the one-way time delay received by the current standby single disk into the FPGA, calculating the time delay change trend by adopting a preset learning algorithm, calculating the next time delay according to the time delay change trend, and compensating the next time delay to the output clock of the standby single disk in advance;
the time delay calculation module calculates the phase difference between the measurement transmission line and the measurement feedback line at the current main single disk, and specifically comprises the following steps
And inputting the feedback input clock of the measurement bus and the sending clock of the measurement bus into the phase discrimination unit, and calculating the phase difference.
6. The system of claim 5, wherein the delay compensation module calculates a delay variation trend by using a preset learning algorithm, and calculates the next delay according to the delay variation trend, specifically comprising the following steps:
acquiring the (n-2) th unidirectional time delay, the (n-1) th unidirectional time delay and the nth unidirectional time delay, wherein n is an integer greater than 2;
calculating the time delay change trend to be the difference value of the (n-1) th one-way time delay and the (n-2) th one-way time delay;
and (4) calculating the (n + 1) th unidirectional time delay according to the time delay change trend, wherein the (n + 1) th unidirectional time delay = the (n-1) th unidirectional time delay + (the difference between the (n-1) th unidirectional time delay and the (n-2) th unidirectional time delay).
7. The system of claim 5, wherein the measurement transmission line is a sum of a clock bus routing length from a current master single disk to a backplane bus, a routing length of the backplane bus, and a length of a clock bus routing length from the backplane bus to a current standby single disk;
the measurement feedback line is the sum of the clock bus line length from the current standby single disk to the backplane bus, the line length of the backplane bus and the length of the clock bus line length from the backplane bus to the current main single disk.
8. The system of claim 5, wherein the delay calculation module is further to: the time delay compensation module compensates the next time delay to the output clock of the standby single disk in advance, judges whether the main/standby switching occurs, and calculates the time delay by the switched main single disk and standby single disk after the system distinguishes the main/standby single disk if the main/standby switching occurs; if not, the current main single disk and the current standby single disk are continuously adopted to set the calculation time delay.
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