CN102833062B - Intelligent substation IEEE1588 master-salve clock synchronization message setting means and system - Google Patents
Intelligent substation IEEE1588 master-salve clock synchronization message setting means and system Download PDFInfo
- Publication number
- CN102833062B CN102833062B CN201210359710.4A CN201210359710A CN102833062B CN 102833062 B CN102833062 B CN 102833062B CN 201210359710 A CN201210359710 A CN 201210359710A CN 102833062 B CN102833062 B CN 102833062B
- Authority
- CN
- China
- Prior art keywords
- clock
- message
- time
- master
- record
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The open intelligent substation IEEE1588 master-salve clock synchronization message setting means of the present invention and system, the method comprises: create master clock message, and sent to from clock with broadcast mode by the delivery time timestamp t1 of this message; Record the t2 time of reception of described master clock message; The described TT2 absolute time of reception receiving described master clock message from clock of record; Create and send to master clock in point-to-point mode from clock response message, and record the delivery time timestamp t3 of this message; Record is described sends the described absolute delivery time TT3 from clock response message from clock; Record master clock obtains the acquisition moment t4 of this message; Computing time deviation, and according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error; Utilize described time deviation and described asymmetric error to the time complexity curve carried out from clock.The present invention, can eliminate the impact of asymmetric error, precision during raising master-salve clock pair.
Description
Technical field
Technology when the present invention relates to Network Synchronization pair, particularly relates to intelligent substation IEEE1588 master-salve clock synchronization message setting means and system.
Background technology
At present, intelligent substation is based on networked communication, and its maximum characteristic and advantage is information sharing.High accuracy data is synchronously the important prerequisite and the base attribute that realize information sharing, is just becoming the key problem of intelligent substation technology and is receiving much concern.But when existing intelligent substation data syn-chronization adopts IRIG-B code pair usually, special optic fibre point-to-point link, unidirectional transmission synchronizing signal, reliability is low, and runs counter to the network information transmission means of intelligent substation.Therefore, correct when when adopting one more accurate synchronous protocol pair, mode carries out synchronous pair, during IEEE1588 technology pair, mode and intelligent substation match based on the Network Transmitting mode of IEC61850, and synchronization accuracy reaches submicrosecond, can meet the requirement of intelligent substation data syn-chronization.
IEEE1588 technology is a kind of accurate time synchronization protocol, is called for short PTP protocol, adopts master-salve clock scheme, carry out coding to the time to transmit, the generation of time stamp is completed by the protocol layer near physical layer, utilizes symmetry and the Time delay measurement technology of network link, realizes the synchronous of master-salve clock time.But important hypothesis during synchronous couple of IEEE1588 is that transmission path is symmetrical back and forth for master-salve clock, i.e. its transmission delay δ back and forth
1=δ
2, and in fact transmission delay δ
1and δ
2generally unequal, cause the asymmetric error producing transmission delay.The influencing factor of IEEE1588 asymmetric error mainly comprises: transmission path difference and network state difference.
(1) transmission path difference: containing timestamp message by master clock to from clock and by from clock to master clock likely through different paths, so back and forth transmission path the number of switches of process not identical with linkage length, the transmission delay δ that message experiences
1and δ
2also be just difficult to equal;
(2) network state difference: communication network running status is dynamic, to run switch processes time delay corresponding to shape not different for difference in the same time, and the loading condition of running status and network is closely related.Therefore, even if transmission path is symmetrical back and forth, network state is different, transmission delay δ
1and δ
2also be difficult to equal.
So, because network operation state may bring synchronous asymmetric error with the difference of transmission path, probabilistic inherent shortcoming when there is network pair during IEEE1588 couple.Under the data syn-chronization that intelligent substation is high requires, this problem more highlights and receives much concern.
Summary of the invention
Based on this, be necessary for the problems referred to above, a kind of intelligent substation IEEE1588 master-salve clock synchronization message setting means and system are provided, can quantitative analysis network state difference with master-salve clock synchronization signal transmission path difference on the impact of the synchronous asymmetric error of IEEE1588, and for improve master-salve clock synchronization pair time precision reference frame is provided.
A kind of intelligent substation IEEE1588 master-salve clock synchronization message setting means, comprising:
Create master clock message, and the delivery time timestamp t1 of this message is sent to from clock with broadcast mode;
Receive described master clock message and described timestamp t1, record the t2 time of reception of described master clock message;
Using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record;
Create and send to master clock in point-to-point mode from clock response message, and record the delivery time timestamp t3 of this message;
Using described network clocking as benchmark, record is described sends the described absolute delivery time TT3 from clock response message from clock;
Obtain described from clock response message, record master clock obtains the acquisition moment t4 of this message;
According to timestamp t1, the time of reception t2, timestamp t3 and obtain moment t4 deviation computing time, computing formula is: T=((t2-t1)-(t4-t3)) * 0.5, and wherein T is time deviation; And according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error, computing formula is: delay_offset=((t4-TT3)-(TT2-t1)) * 0.5, and wherein delay_offset is described asymmetric error; ;
Utilize the time complexity curve that described time deviation and described asymmetric error carry out from clock.
Correspondingly, system during a kind of intelligent substation IEEE1588 master-salve clock synchronization message pair, comprising:
Master clock transmitting element, for creating master clock message, and sends the delivery time timestamp t1 of this message to from clock with broadcast mode;
From clock receiving element, for receiving described master clock message and described timestamp t1, record the t2 time of reception of described master clock message;
With described from time receive the network clocking unit that clock unit is connected, for using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record;
With described from time receive that clock unit is connected from clock transmitting element, send to master clock in point-to-point mode from clock response message for creating, and record the delivery time timestamp t3 of this message;
Described network clocking unit is also connected from clock transmitting element with described, for using described network clocking as benchmark, sends the described absolute delivery time TT3 from clock response message described in record from clock;
Master clock receiving element, described from clock response message for obtaining, record master clock obtains the acquisition moment t4 of this message;
Described network clocking unit comprises deviation computing unit and error calculation unit, wherein, described deviation computing unit be used for according to timestamp t1, the time of reception t2, timestamp t3 and obtain moment t4 deviation computing time, computing formula is: T=((t2-t1)-(t4-t3)) * 0.5, and wherein T is time deviation; Described error calculation unit be used for according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error, computing formula is: delay_offset=((t4-TT3)-(TT2-t1)) * 0.5, and wherein delay_offset is described asymmetric error;
With described deviation computing unit and described error calculation unit be connected respectively from clock amending unit, the time complexity curve carrying out from clock for utilizing described time deviation and described asymmetric error.
Implement the present invention, there is following beneficial effect:
The present invention is by the message switching transmission between master-salve clock, calculate deviation time, and in conjunction with network clocking, quantitative analysis is carried out to the transmission delay between master-salve clock, thus obtain network state difference with master-salve clock synchronization signal transmission path difference to the impact of the synchronous asymmetric error of IEEE1588, correct when realizing intelligent substation master-salve clock synchronization pair, precision during raising master-salve clock synchronization pair.
Accompanying drawing explanation
Fig. 1 is the flow chart of a kind of intelligent substation IEEE1588 of the present invention master-salve clock synchronization message setting means;
Fig. 2 is the principle schematic of master-salve clock synchronization process of the present invention;
Fig. 3 is the Application Example schematic diagram of a kind of intelligent substation IEEE1588 of the present invention master-salve clock synchronization message setting means;
The schematic diagram of system when Fig. 4 is a kind of intelligent substation IEEE1588 master-salve clock synchronization message pair of the present invention;
Systematic difference embodiment schematic diagram when Fig. 5 is the present invention's one intelligent substation IEEE1588 master-salve clock synchronization message pair.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
A kind of intelligent substation IEEE1588 master-salve clock synchronization message setting means and the system of invention are based on IEEE1588 accurate time synchronization protocol, the protocol define four kinds of sync messages: sync message Sync, follow message Follow_Up, postpone request message Delay_Req, Delay Feedback message Delay_Resp and a fabric anomaly message Management massage.Sync message comprises timestamp, and therefore also referred to as event message, and administrative message does not comprise timestamp, is also referred to as universal information.Mainly modeling is carried out to four kinds of sync messages in actual design application, and administrative message does not relate to, and is not discussed at this.The feature that IEEE1588 sync message has is as follows:
1) Sync sends from master clock node with broadcast mode, needs to mark its time departure at master clock Nodes, is marking its time of advent from clock node.
2) Delay_Req is in point-to-point mode from respectively sending from clock node, needs to mark its time departure at each from clock node, marks its time of advent at master clock Nodes.
3) Follow_Up sends from master clock node with broadcast mode; Delay_Resp sends from master clock in point-to-point mode.These two messages do not need to carry out time mark.
The transmitting procedure of network packet needs communication protocol stack successively to be encapsulated by packet, finally MAC layer formed mac frame then pass to physical layer, physical layer again by data-driven for the level signal met required for network medium sends.Udp protocol define packet through first time encapsulation after again through the encapsulation of ip protocol layer, be finally packaged into the frame structure of MAC form in MAC layer, for the transmission of data.When accepting UDP message bag, communication protocol stack then needs successively upwards to be transmitted by the mac frame received, and successively peels off encapsulation, finally arrives application.And IEEE1588 sync message follows three layer protocols, mac frame can only be detected, its data link layer encapsulation and analytic message MAC Address.
According to IEEE1588 agreement, sync message all has same header format, and in its form, 0 ~ 13 byte is the frame head form of mac frame, and 14 ~ 33 bytes are IP message top-of-form, and 34 ~ 41 bytes are UDP message top-of-form.MessageType: if Sync/Delay_Req message, value is herein 0x01; If Follow_UP/Delay_Resp message, value is herein 0x02.SequenceI: message transmits Sequence Number, the sequenceId value that its value sends by the port last time message of the same race adds one.Control value can be used as the foundation distinguishing type of message, if Sync message, is worth for PTP_SYNC_MESSAGE; If Delay_Req message, be worth for PTP_DELAY_REQ_MESSAGE; If Follow_Up message, be worth for PTP_FOLLOWUP_MESSAGE; If Delay_Resp message, be worth for PTP_DELAY_RESP_MESSAGE.For four kinds of sync messages, its message format content is as follows:
1) Sync message and Delay_Req message
Sync message is identical with Delay_Req message structure content, and wherein, originTimestamp is the estimated time of local clock treatment S ync or Delay_Req message, and namely message time stamp point is through the time of clock time stamp point of popping; EpochNumber is number synchronizing cycle; CurrentUTCOffset is current UT side-play amount; 94 ~ 118 bytes are for illustration of the Clock properties of the highest master clock and port attribute; SyncInterval value determines clock synchronous interval.
2) Follow_Up message
The sequenceId of the Sync message that the associatedSequenceId value in Follow_Up message is followed for Follow_Up; PreciseOriginTimestamp value leaves the precise time of node for Sync message that Follow_Up follows.
3) Delay_Resp message
This value of delayReceiptTimestamp in Delay_Resp message structure represents the relevant precise time of Delay_Resp message time stamp when the clock time that pushes on stabs some, by the local clock timing of the port of transmission association message; The Clock properties of source clock in the Delay_Req message that 90 ~ 98 byte representations are associated with Delay_Resp, wherein the requestingSourceSequenceId value sequenceId value of Delay_Req message of replying for Delay_Resp.
Fig. 1 is the flow chart of a kind of intelligent substation IEEE1588 of the present invention master-salve clock synchronization message setting means, comprising:
S101: create master clock message, and the delivery time timestamp t1 of this message is sent to from clock with broadcast mode;
S102: receive described master clock message and described timestamp t1, record the t2 time of reception of described master clock message;
S103: using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record;
S104: create and send to master clock in point-to-point mode from clock response message, and the delivery time timestamp t3 recording this message;
S105: using described network clocking as benchmark, record is described sends the described absolute delivery time TT3 from clock response message from clock;
S106: obtain described from clock response message, record master clock obtains the acquisition moment t4 of this message;
S107: according to timestamp t1, the time of reception t2, timestamp t3 and obtain moment t4 deviation computing time, and according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error;
S108: utilize described time deviation and described asymmetric error to the time complexity curve carried out from clock.
First, the present invention creates master clock message Sync, arranges the information such as packet format, transmission cycle, and sends to from clock.Also the delivery time timestamp t1 of this message is placed in follow_up bag, sends to from clock with broadcast mode.
Then, receive the follow_up message of master clock from clock, obtain the delivery time t1 of master clock message, and obtain the t2 time of reception of master clock message Sync with the form of beating timestamp.Wherein, using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record, it is the absolute time of reception without master-salve clock time deviation.Again and, create from clock and the information such as packet format, transmission cycle is set from clock response message Delay_req sends to master clock, and record the delivery time timestamp t3 of this message.Using described network clocking as benchmark, then record is described from the described absolute delivery time TT3 from clock response message of clock transmission, and it is the absolute transmitting time without master-salve clock time deviation.
Finally, master clock obtains Delay_Req message and records the acquisition moment t4 of this message, continues point-to-point mode t4 to be placed in Delay_Resp message and to send from clock to target.After acquisition t1, t2, t3, t4, TT2, TT3, just can calculate according to preset formula and correct master-salve clock deviation offset and asymmetric error delay_offset.
It should be added that, in the middle of a simulating scenes, the present invention can adopt OPNET Modeler communication software to carry out modeling, realizes above-mentioned network clocking, and calculates the function of clock jitter, asymmetric error writing time, research actual conditions.And in the middle of practical application scene, the present invention can adopt the switch be connected between master-salve clock to be achieved.
The Precision Time Protocol (Precision TimeProtocol) that described network clocking adopts IEEE 1588 to define.
What the present invention adopted IEEE 1588 to define realizes the synchronous agreement of high precision clock---Precision Time Protocol (Precision Time Protocol), in OPNET Modeler software, modeling is carried out to intelligent substation master-salve clock, be connected by network between clock, and by clock the most accurate in network with synchronously other clocks all of the mode based on message transmissions, quantitative analysis network state difference and master-salve clock synchronization signal transmission path difference, on the impact of the synchronous asymmetric error of IEEE1588, realize master-salve clock synchronization and correct.
Except selecting above-mentioned agreement, agreement when the present invention can also adopt traditional NTP/SNTP couple.But these traditional agreements need carry out agreement explanation in the application, can increase system loading.So, the Precision Time Protocol (Precision Time Protocol) that the preferred embodiments of the present invention adopt IEEE 1588 to define.
Fig. 2 is the Application Example schematic diagram of a kind of intelligent substation IEEE1588 of the present invention master-salve clock synchronization message setting means.Below in conjunction with Fig. 2, explanation is launched to embodiments of the present invention.
S201: create master clock pair time message, between described master clock and described network clocking, transmit this message, carry out master clock pair time;
S202: create master clock message, and the delivery time timestamp t1 of this message is sent to from clock with broadcast mode;
S203: receive described master clock message and described timestamp t1, before message is made an explanation, read the time of advent of this message in data link layer, record the t2 time of reception of described master clock message;
S204: using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record;
S205: create and send to master clock in point-to-point mode from clock response message, and the delivery time timestamp t3 recording this message;
S206: using described network clocking as benchmark, record is described sends the described absolute delivery time TT3 from clock response message from clock;
S207: from clock response message and described timestamp t3 described in obtaining, before message is made an explanation, read the time of advent of this message in data link layer, the described acquisition moment t4 from clock response message of record;
S208: according to timestamp t1, the time of reception t2, timestamp t3 and obtain moment t4 deviation computing time, and according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error;
S209: utilize the time complexity curve that described time deviation and described asymmetric error carry out from clock.
In the middle of the network application scene of reality, during for Network Synchronization pair, although the message that master-salve clock carrys out transmission back sometimes carries out at same link, but the message sent and the message transmission in a switch of reception are not equal, may occur that sending message does not need when going out switch to arrange very long queue, but the message that receives is through that a queuing process for a long time just exports, transmission delay δ back and forth so will be caused
1and δ
2and it is unequal.So, can by the concept of boundary clock, between adjacent two-stage clock, when realizing master-salve clock synchronization pair.As shown in Figure 2, boundary clock just refers to that the master clock Master of each grade of clock to upper level is from clock Slave, for clock Slave, master clock Master is then served as next stage, realizes in the switch Switch of network clocking then between adjacent two-stage clock.
Create master clock pair time message, between described master clock and described network clocking, transmit this message, carry out master clock pair time.In Fig. 2, the network clocking of switch and master clock are a pair master-salve clock relations, the sync message alignment time is sent between them, because every a pair master-salve clock is all linear speed transmit message, so transmission delay is equal back and forth, when so just can arrive accurate pair to master clock, and then, make aiming at master clock from clock of cascade at different levels by multistage debugging.
But may occur two problems again, the first, along with the switch of cascade increases, the time overhead of protocol analysis also can increase simultaneously.When IEEE1588 master-salve clock pair in process, except reception and sending datagram, also in data link layer encapsulation and analytic message MAC Address, need fill with packets fields to application layer protocol parsing to complete IEEE1588 message data link layer.Improvement project of the present invention is, before making an explanation, reads the time of advent of this message in data link layer to message.Particularly, at data link layer outlet joining day stamp labeling function op_pk_stamp (pkptr) and function reading op_pk_stamp_time_get (pkptr), reduce the time cost of the protocol analysis of application layer.
Another one problem is, even if although between every a pair master-salve clock pair time very accurate, and can not be 100% accurately, if switch has a lot of cascade, by deviation accumulation, will finally cause the error be not allowed to.Therefore improvement project is proposed:
Receive this message after master clock sends described master clock message, from clock before, when described master clock message is by switch, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, according to the time difference correction t2 described time of reception of turnover time;
Send from clock described from after clock response message, before master clock receives this message, when described from clock response message by switch time, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, the time difference according to the turnover time revises described acquisition moment t4.
As shown in Figure 2, then the time difference calculating turnover port by the mode of beating timestamp to turnover message adds to revise inside territory and goes, often through a switch, network clocking all can record a time difference, thus can according to time difference corrected received moment t2, t4 of turnover time.
In IEEE1588 agreement master-salve clock model, consider network state and the dynamic otherness of transmission path simultaneously, by master-salve clock back and forth transmission delay unequal premised on, realize the time deviation offset of master-salve clock and the calculating of asymmetric error delay_offse and calibration function, improve IEEE1588 synchronization accuracy.
Fig. 3 is the principle schematic of master-salve clock synchronization process of the present invention.Below in conjunction with Fig. 3, realize principle and computational process is described to of the present invention.
Suppose that master clock and the time deviation from clock are offset, i.e. offset=t
slave-t
master, send synchronization request message to master clock from clock when local moment t1, master clock receives synchronization request message, if the propagation delay time from clock to master clock is δ when local moment t2
1, then
t
2＝t
1+offset+δ
1(1)
Master clock sends sync message when t3 to from clock, receives sync message, if master clock is δ to the propagation delay time from clock from clock when local moment t4
2, then
t
4＝t
3-offset+δ
2(2)
Asymmetric error factor in when considering synchronous pair, i.e. δ
1and δ
2unequal, solve time deviation offset and revise, Δ t is asymmetric error, obtains:
Below in conjunction with above-mentioned principle, concrete computational process is described, suppose that master clock t1=12:00 sends message to from clock, receive from clock absolute time TT2=12:05, i.e. its transmission time T1=5min, but the free deviation 10min of master-salve clock exists, therefore is t2=12:15 from clock time of reception;
Message is sent to master clock at absolute time TT3=12:10 from clock, namely its delivery time due to free deviation is t3=12:20, master clock receives at t4=12:19, then from clock transfer to master clock, used 9min (can find out transmission back time difference); Under computational process:
If there is not the time deviation of asymmetric error:
T＝((t2-t1)-(t4-t3))*0.5＝((12:15-12:00)-(12:19-12:20))*0.5＝(15-(-1))*0.5＝8；
The time jitter of asymmetric error:
delay_offset＝((t4-TT3)-(TT2-t1))*0.5＝((12:19-12:10)-(12:05-12:00))*0.5＝(9-5)*0.5＝2；
Time deviation correction:
offset＝offset-T-delay_offset＝10-8-2＝0；
In OPNET Modeler communication simulation software, absolute time refers to the time of analogue system, because simulation software is all a unified standard time, the time that master-salve clock timestamp obtains is all absolute time in fact, but the clock jitter offset from clock setting, add that clock jitter is as the receipts sending and receiving time from clock, exists clock jitter with master-salve clock in simulating actual conditions from the absolute time of clock.And in actual scene, switch serves as network clocking, the Precision Time Protocol (Precision Time Protocol) that its absolute time defines based on IEEE 1588.
The schematic diagram of system when Fig. 4 is a kind of intelligent substation IEEE1588 master-salve clock synchronization message pair of the present invention, comprising:
Master clock transmitting element, for creating master clock message, and sends the delivery time timestamp t1 of this message to from clock with broadcast mode;
From clock receiving element, for receiving described master clock message and described timestamp t1, record the t2 time of reception of described master clock message;
With described from time receive the network clocking unit that clock unit is connected, for using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record;
With described from time receive that clock unit is connected from clock transmitting element, send to master clock in point-to-point mode from clock response message for creating, and record the delivery time timestamp t3 of this message;
Described network clocking unit is also connected from clock transmitting element with described, for using described network clocking as benchmark, sends the described absolute delivery time TT3 from clock response message described in record from clock;
Master clock receiving element, described from clock response message for obtaining, record master clock obtains the acquisition moment t4 of this message;
Described network clocking unit comprises deviation computing unit and error calculation unit, wherein, described deviation computing unit be used for according to timestamp t1, the time of reception t2, timestamp t3 and obtain moment t4 deviation computing time; Described error calculation unit be used for according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error;
With described deviation computing unit and described error calculation unit be connected respectively from clock amending unit, the time complexity curve carrying out from clock for utilizing described time deviation and described asymmetric error.
Fig. 4 and Fig. 1 is corresponding, the operational mode of unit and identical in method in figure.
Systematic difference embodiment schematic diagram when Fig. 5 is the present invention's one intelligent substation IEEE1588 master-salve clock synchronization message pair.
As shown in Figure 5, wherein, described network clocking unit also comprises:
Agreement selected cell, for the Precision Time Protocol (Precision TimeProtocol) adopting IEEE 1588 to define.
The unit during master clock pair be connected with described master clock transmitting element, message during for creating master clock pair, transmits this message between described master clock and described network clocking, carry out master clock pair time.
Wherein in the middle of an embodiment, the present invention also comprises:
With the described time of reception reading unit be connected from clock receiving element, before master clock message is made an explanation, read the time of advent of this message in data link layer;
The acquisition time reading unit be connected with described master clock receiving element, for before making an explanation from clock response message, reads the time of advent of this message in data link layer.
Wherein in the middle of an embodiment, described network clocking unit, also comprises:
The timestamp indexing unit 1 be connected with described time of reception reading unit, for when described master clock message is by switch, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, according to the time difference correction t2 described time of reception of turnover time; And/or,
Timestamp indexing unit 2 is also connected with described acquisition time reading unit, also for described from clock response message by switch time, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, the time difference according to the turnover time revises described acquisition moment t4.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. an intelligent substation IEEE1588 master-salve clock synchronization message setting means, is characterized in that, comprising:
Create master clock message, and the delivery time timestamp t1 of this message is sent to from clock with broadcast mode;
Receive described master clock message and described timestamp t1, record the t2 time of reception of described master clock message;
Using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record;
Create and send to master clock in point-to-point mode from clock response message, and record the delivery time timestamp t3 of this message;
Using described network clocking as benchmark, record is described sends the described absolute delivery time TT3 from clock response message from clock;
Obtain described from clock response message, record master clock obtains the acquisition moment t4 of this message;
According to timestamp t1, the time of reception t2, timestamp t3 and obtain moment t4 deviation computing time, computing formula is: T=((t2-t1)-(t4-t3)) * 0.5, and wherein T is time deviation; And according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error, computing formula is: delay_offset=((t4-TT3)-(TT2-t1)) * 0.5, and wherein delay_offset is described asymmetric error;
Utilize the time complexity curve that described time deviation and described asymmetric error carry out from clock.
2. intelligent substation IEEE1588 master-salve clock synchronization message setting means according to claim 1, is characterized in that: the Precision Time Protocol (PrecisionTime Protocol) that described network clocking adopts IEEE 1588 to define.
3. intelligent substation IEEE1588 master-salve clock synchronization message setting means according to claim 1 and 2, is characterized in that, before creating the step of master clock message, comprising:
Create master clock pair time message, between described master clock and described network clocking, transmit this message, carry out master clock pair time.
4. intelligent substation IEEE1588 master-salve clock synchronization message setting means according to claim 1 and 2, it is characterized in that, record described master clock message the time of reception t2 step in, and record master clock obtain in the step of acquisition moment t4 of this message, also comprise:
Before message is made an explanation, read the time of advent of this message in data link layer.
5. intelligent substation IEEE1588 master-salve clock synchronization message setting means according to claim 4, is characterized in that:
Receive this message after master clock sends described master clock message, from clock before, when described master clock message is by switch, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, according to the time difference correction t2 described time of reception of turnover time; And/or,
Send from clock described from after clock response message, before master clock receives this message, when described from clock response message by switch time, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, the time difference according to the turnover time revises described acquisition moment t4.
6. system during intelligent substation IEEE1588 master-salve clock synchronization message pair, is characterized in that, comprising:
Master clock transmitting element, for creating master clock message, and sends the delivery time timestamp t1 of this message to from clock with broadcast mode;
From clock receiving element, for receiving described master clock message and described timestamp t1, record the t2 time of reception of described master clock message;
With described from time receive the network clocking unit that clock unit is connected, for using network clocking as benchmark, the described TT2 absolute time of reception receiving described master clock message from clock of record;
With described from time receive that clock unit is connected from clock transmitting element, send to master clock in point-to-point mode from clock response message for creating, and record the delivery time timestamp t3 of this message;
Described network clocking unit is also connected from clock transmitting element with described, for using described network clocking as benchmark, sends the described absolute delivery time TT3 from clock response message described in record from clock;
Master clock receiving element, described from clock response message for obtaining, record master clock obtains the acquisition moment t4 of this message;
Described network clocking unit comprises deviation computing unit and error calculation unit, wherein, described deviation computing unit be used for according to timestamp t1, the time of reception t2, timestamp t3 and obtain moment t4 deviation computing time, computing formula is: T=((t2-t1)-(t4-t3)) * 0.5, and wherein T is time deviation; Described error calculation unit be used for according to timestamp t1, definitely the time of reception TT2, absolute delivery time TT3 and obtain moment t4 and calculate asymmetric error, computing formula is: delay_offset=((t4-TT3)-(TT2-t1)) * 0.5, and wherein delay_offset is described asymmetric error;
With described deviation computing unit and described error calculation unit be connected respectively from clock amending unit, the time complexity curve carrying out from clock for utilizing described time deviation and described asymmetric error.
7. system during intelligent substation IEEE1588 master-salve clock synchronization message pair according to claim 6, is characterized in that, described network clocking unit, also comprises:
Agreement selected cell, for the Precision Time Protocol (Precision TimeProtocol) adopting IEEE 1588 to define.
8. system during intelligent substation IEEE1588 master-salve clock synchronization message pair according to claim 6 or 7, it is characterized in that, described network clocking unit, also comprises:
The unit during master clock pair be connected with described master clock transmitting element, message during for creating master clock pair, transmits this message between described master clock and described network clocking, carry out master clock pair time.
9. system during intelligent substation IEEE1588 master-salve clock synchronization message pair according to claim 6 or 7, is characterized in that, also comprise:
With the described time of reception reading unit be connected from clock receiving element, before master clock message is made an explanation, read the time of advent of this message in data link layer;
The acquisition time reading unit be connected with described master clock receiving element, for before making an explanation from clock response message, reads the time of advent of this message in data link layer.
10. system during intelligent substation IEEE1588 master-salve clock synchronization message pair according to claim 9, is characterized in that, described network clocking unit, also comprises:
The timestamp indexing unit be connected with described time of reception reading unit, for when described master clock message is by switch, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, according to the time difference correction t2 described time of reception of turnover time; And/or,
Described timestamp indexing unit is also connected with described acquisition time reading unit, also for described from clock response message by switch time, using described network clocking as benchmark, record the time that this message passes in and out the port of described switch, the time difference according to the turnover time revises described acquisition moment t4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210359710.4A CN102833062B (en) | 2012-09-25 | 2012-09-25 | Intelligent substation IEEE1588 master-salve clock synchronization message setting means and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210359710.4A CN102833062B (en) | 2012-09-25 | 2012-09-25 | Intelligent substation IEEE1588 master-salve clock synchronization message setting means and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102833062A CN102833062A (en) | 2012-12-19 |
| CN102833062B true CN102833062B (en) | 2015-08-12 |
Family
ID=47336042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210359710.4A Active CN102833062B (en) | 2012-09-25 | 2012-09-25 | Intelligent substation IEEE1588 master-salve clock synchronization message setting means and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102833062B (en) |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103532230B (en) * | 2013-09-30 | 2016-04-13 | 国家电网公司 | Synchro system during intelligent distribution network IEEE1588 school based on the tangent access ring of Industrial Ethernet |
| CN103546268B (en) * | 2013-10-15 | 2016-08-10 | 瑞斯康达科技发展股份有限公司 | The compensation method of a kind of system time and equipment |
| CN103595588A (en) * | 2013-11-26 | 2014-02-19 | 北京奥普维尔科技有限公司 | Method for accurately measuring asynchronous Ethernet circuit time delay |
| CN103929263B (en) * | 2014-04-30 | 2016-10-26 | 北京华力创通科技股份有限公司 | Network communication method |
| CN104202137A (en) * | 2014-07-09 | 2014-12-10 | 北京东土科技股份有限公司 | IEEE1588 clock synchronization method, system and device based on E1 link |
| CN104836654B (en) * | 2015-04-15 | 2018-06-22 | 浙江大学 | A kind of clock synchronizing method based on Ethernet POWERLINK |
| CN104850526A (en) * | 2015-06-10 | 2015-08-19 | 首都师范大学 | Method for time synchronization in dynamically reconfigurable high-speed serial bus |
| CN105141406A (en) * | 2015-09-29 | 2015-12-09 | 北京润科通用技术有限公司 | Time synchronization method, time synchronization apparatus and simulation system |
| EP3166242A1 (en) * | 2015-11-05 | 2017-05-10 | Robert Bosch Gmbh | Clock synchronization monitoring in an ethernet-based network |
| CN105450384A (en) * | 2015-12-10 | 2016-03-30 | 中国能源建设集团广东省电力设计研究院有限公司 | Synchronous clock time synchronization apparatus for communication module |
| CN105554870A (en) * | 2015-12-21 | 2016-05-04 | 海能达通信股份有限公司 | Uplink synchronization method and mobile terminal |
| CN106027193B (en) * | 2016-07-07 | 2019-06-18 | 广州市国飞信息科技有限公司 | For the clock synchronizing method of time calibration in network system, module, equipment and system |
| CN106130681B (en) * | 2016-07-25 | 2019-03-08 | 广州市国飞信息科技有限公司 | For the high-accuracy clock synchronization method of time dissemination system, module, equipment and system |
| CN106451763B (en) * | 2016-08-23 | 2019-03-19 | 江苏方天电力技术有限公司 | A kind of intelligent substation station level bus network system without global synchronization system |
| EP3553994B1 (en) | 2016-12-30 | 2023-05-31 | Huawei Technologies Co., Ltd. | Method for exchanging time synchronisation message, and network device |
| CN108667543B (en) * | 2017-03-29 | 2019-12-13 | 华为技术有限公司 | Clock processing method, access network equipment and terminal equipment |
| CN109218007B (en) * | 2017-07-03 | 2022-11-01 | 中兴通讯股份有限公司 | Path selection method, device and storage medium |
| CN107483402B (en) * | 2017-07-12 | 2019-12-06 | 瑞斯康达科技发展股份有限公司 | Clock synchronization method and equipment |
| CN109068384A (en) * | 2018-08-23 | 2018-12-21 | 平安科技（深圳）有限公司 | A kind of method for synchronizing time and system |
| CN111385048B (en) * | 2018-12-29 | 2023-06-30 | 中兴通讯股份有限公司 | Time synchronization method and system |
| CN109873693A (en) * | 2019-02-12 | 2019-06-11 | 广东电网有限责任公司 | A kind of substation's clock synchronization situation cognitive method |
| JP6612006B1 (en) * | 2019-03-18 | 2019-11-27 | 三菱電機株式会社 | Time synchronization apparatus, communication system, time synchronization method, and time synchronization program |
| CN110113793A (en) * | 2019-04-04 | 2019-08-09 | 北京邮电大学 | A kind of rear 5G forward pass net method for synchronizing time and device based on depth enhancing study |
| CN110267200A (en) * | 2019-06-27 | 2019-09-20 | 合肥更鼓电子科技有限公司 | A kind of base station positioning method based on precise synchronization network |
| CN112436914B (en) * | 2019-08-26 | 2022-08-30 | 烽火通信科技股份有限公司 | Method and system for protecting master and slave 5G ultrahigh-precision clocks |
| CN111601189B (en) * | 2020-04-30 | 2022-01-25 | 云南电网有限责任公司迪庆供电局 | Accurate time synchronization method and system applied to cable distance measuring device |
| CN111708296A (en) * | 2020-06-16 | 2020-09-25 | 山东省计算中心（国家超级计算济南中心） | Synchronous control and data voting method based on two-channel safety PLC |
| CN112039719B (en) * | 2020-07-20 | 2022-07-12 | 河北汉光重工有限责任公司 | PTP clock synchronization precision testing method for linux system |
| CN112235067B (en) * | 2020-09-24 | 2022-03-25 | 烽火通信科技股份有限公司 | Centralized 1588 time synchronization method and time synchronization system |
| CN114553351B (en) * | 2020-11-24 | 2023-12-08 | 华为技术有限公司 | Time synchronization method, control device, equipment and storage medium |
| CN113037415A (en) * | 2021-02-25 | 2021-06-25 | 上海赫千电子科技有限公司 | TSN (time delay network) clock synchronization method, system and equipment based on vehicle-mounted Ethernet transmission |
| CN113687590B (en) * | 2021-08-10 | 2023-03-10 | 青岛小鸟看看科技有限公司 | Time synchronization method and system for head and handle in VR system |
| CN113645686B (en) * | 2021-08-12 | 2023-12-22 | 中国人民解放军国防科技大学 | Wireless self-organizing network time synchronization method with motion compensation |
| WO2023060390A1 (en) * | 2021-10-11 | 2023-04-20 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and network device for ptp clock synchronization |
| EP4209885A4 (en) * | 2021-11-13 | 2024-01-10 | Kingfar Int Inc | Clock crystal oscillator synchronization method, apparatus and system |
| CN114401067A (en) * | 2021-12-24 | 2022-04-26 | 浙江中控技术股份有限公司 | Time synchronization method for ring network communication, programmable gate array and ring network communication system |
| CN114124616B (en) * | 2022-01-25 | 2022-05-27 | 浙江中控研究院有限公司 | Clock synchronization optimization method based on EPA bus structure |
| CN115833985A (en) * | 2022-11-16 | 2023-03-21 | 中国联合网络通信集团有限公司 | Time synchronization method, device, communication terminal and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101729180A (en) * | 2008-10-21 | 2010-06-09 | 华为技术有限公司 | Method and system for synchronizing precision clocks, and precision clock frequency/time synchronizing device |
| CN101795020A (en) * | 2010-02-08 | 2010-08-04 | 四方华能电网控制系统有限公司 | Automatic time-tick synchronization system of intelligent electronic equipment of transformer substation |
| CN101834712A (en) * | 2010-04-19 | 2010-09-15 | 浙江大学 | Method for realizing accurate time synchronization by utilizing IEEE1588 protocol |
| CN101902292A (en) * | 2009-12-30 | 2010-12-01 | 西安大唐电信有限公司 | UTC high-precision time synchronization method based on optical transmission network |
| CN102006157A (en) * | 2010-11-26 | 2011-04-06 | 中兴通讯股份有限公司 | Time synchronization method and system |
-
2012
- 2012-09-25 CN CN201210359710.4A patent/CN102833062B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101729180A (en) * | 2008-10-21 | 2010-06-09 | 华为技术有限公司 | Method and system for synchronizing precision clocks, and precision clock frequency/time synchronizing device |
| CN101902292A (en) * | 2009-12-30 | 2010-12-01 | 西安大唐电信有限公司 | UTC high-precision time synchronization method based on optical transmission network |
| CN101795020A (en) * | 2010-02-08 | 2010-08-04 | 四方华能电网控制系统有限公司 | Automatic time-tick synchronization system of intelligent electronic equipment of transformer substation |
| CN101834712A (en) * | 2010-04-19 | 2010-09-15 | 浙江大学 | Method for realizing accurate time synchronization by utilizing IEEE1588 protocol |
| CN102006157A (en) * | 2010-11-26 | 2011-04-06 | 中兴通讯股份有限公司 | Time synchronization method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102833062A (en) | 2012-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102833062B (en) | Intelligent substation IEEE1588 master-salve clock synchronization message setting means and system | |
| CN103929293B (en) | Asymmetrically-delayed time synchronization method and system | |
| CN104737490B (en) | Communicator, communication system and method for synchronizing time | |
| CN104507156B (en) | For the time synchronization improved method based on IEEE 1588PTP mechanism of wireless network | |
| CN101425891B (en) | Time synchronization method, system and customer terminal | |
| EP2506470B1 (en) | Method, apparatus and system for time distribution in a telecommunications network | |
| CN101951312B (en) | E1 link-based bidirectional time-frequency synchronous transmission method and master-slave device | |
| CN101425865B (en) | Method and system for synchronizing clock of transmission network as well as subordinate clock side entity | |
| WO2017107261A1 (en) | Time synchronization error compensation method for ptp-based multi-hop wireless backhaul networks | |
| US20100074383A1 (en) | Timestamping method and apparatus for precise network synchronization | |
| CN102843620B (en) | A kind of OTN Apparatus and method for realizing time synchronized and transmit | |
| CN105846941B (en) | Clock transparent transmission device and method based on 1588 standards of IEEE | |
| CN105450384A (en) | Synchronous clock time synchronization apparatus for communication module | |
| US20220140929A1 (en) | Packet Processing Method and Network Device | |
| CN103138887B (en) | A kind of processing method and system of 1588 event message | |
| CN104754722B (en) | A kind of method for synchronizing time towards stratification heterogeneous network | |
| CN102299788A (en) | Method and device for controlling automatic transmission of IEEE1558 (Institute of Electrical and Electronic Engineers 1558) protocol message | |
| CN106506107B (en) | A kind of ntp server time service implementation method based on hardware timestamping | |
| CN105577349A (en) | Airborne network IEEE1588 protocol master-slave clock port synchronization method | |
| CN207939521U (en) | A kind of clock synchronization apparatus towards digital transformer substation debugging | |
| CN105978652B (en) | Equipment, system and method at synchronous pair of Redundant Ethernet | |
| CN103647614A (en) | Method for reliably improving time synchronization precision based on IEEE1588 protocol | |
| CN103117829A (en) | Method or device for time synchronization and compensation between asymmetrical networks | |
| CN108429596B (en) | A kind of ethernet mac module realization device and implementation method for IEEE 1588v2 agreement | |
| CN102957489B (en) | Clock synchronization method and master-slave clock entity |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |