CN104202137A - IEEE1588 clock synchronization method, system and device based on E1 link - Google Patents
IEEE1588 clock synchronization method, system and device based on E1 link Download PDFInfo
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- CN104202137A CN104202137A CN201410326095.6A CN201410326095A CN104202137A CN 104202137 A CN104202137 A CN 104202137A CN 201410326095 A CN201410326095 A CN 201410326095A CN 104202137 A CN104202137 A CN 104202137A
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Abstract
The invention provides an IEEE1588 clock synchronization method, system and device based on an E1 link, and aims to increase the clock synchronization accuracy. In the method, second conversion equipment which keeps clock synchronization with slave clock equipment determines link delay from first conversion equipment to the second conversion equipment according to the moment t2 of each time stamp t1 in a plurality of received E1 messages, and receives link delay from the second conversion equipment to the first conversion equipment transmitted by the first conversion equipment which keeps clock synchronization with a master clock, and the determined link delay between the first conversion equipment and the second conversion equipment is used for performing clock synchronization on an own clock. In the embodiment of the invention, clock synchronization is performed through the second conversion equipment which keeps clock synchronization with a slave clock, transmitted and received synchronization messages are time-stamped on the conversion equipment, and the link delay is determined by transmitting a plurality of E1 messages carrying time stamps, so that the influence of E1 link delay jitter is avoided, and the clock synchronization accuracy is increased.
Description
Technical field
The present invention relates to Industrial Ethernet technical field, relate in particular to a kind of IEEE1588 clock synchronizing method, system and device based on E1 link.
Background technology
Fig. 1 is at SDH (Synchronous Digital Hierarchy) (Synchronous Digital Hierarchy in prior art, SDH) structure chart of the PTP message of transmission over networks Ethernet bearing, clock equipment by SDH network when from clockwork transmission PTP message, Ethernet and E1 conversion equipment on this transmission link, have been increased, clock equipment arrives Ethernet and E1 conversion equipment by this PTP message transmissions, this device is converted to E1 message by this PTP message, after SDH network, again this E1 message being converted to PTP message sends to from clockwork, thereby realize main, from between clockwork to time, the clock synchronous message process and the similar process of said process that from clockwork, send accordingly, be transferred to clock equipment.
Fig. 2 carries out the concrete structure figure of clock synchronous based on E1 link in prior art, this Fig. 2 and Fig. 1 are substantially similar, and while transmitting PTP message in SDH network, the timestamp in PTP message is that the PHY on the master and slave clockwork of turnover Ethernet stamps.Master-salve clock equipment, when carrying out clock synchronous, need to guarantee that clock equipment arrives the link delay from clockwork, with the link delay equity from clockwork to clock equipment.But, in above-mentioned Fig. 2, when message is changed between E1 link and ethernet link, the message transmission rate of Ethernet is very fast, therefore when clock sync message is converted to after Ethernet message, clock synchronous message can send immediately, and the data transmission rate of E1 link is slower, clock synchronous message is converted to after E1 message, the delivery time of this message needs to wait until could send, and each time of waiting for need to determine according to the transmission situation of current E1 link, the time of this wait is not what fix, so this time delay is also referred to as jitter time delay.
The clock equipment that causes this jitter time delay arrives the link delay from clockwork, not reciprocity with the link delay from clockwork to clock equipment, and this jitter time delay can not be separated from link delay, cause the shake of whole link delay, add the delay jitter on SDH link, make the unstable time delay of whole link reach delicate rank, thus cannot meet to time precision nanosecond needs.
Summary of the invention
In view of the above problems, the present invention has been proposed to a kind of a kind of IEEE1588 clock synchronizing method, system and device based on E1 link that overcomes the problems referred to above or address the above problem is at least in part provided.
The embodiment of the present invention provides a kind of IEEE1588 clock synchronizing method based on E1 link, the first conversion equipment and clock equipment keep clock synchronous, the second conversion equipment with from clock, keep clock synchronous, the first conversion equipment and the second conversion equipment are for realizing the conversion between Ethernet message and E1 message, and the method comprises:
The second conversion equipment is according to the moment t2 that receives each timestamp t1 in a plurality of E1 messages, determine that the first conversion equipment is to the link delay between the second conversion equipment, wherein said a plurality of E1 message is to send after the first conversion equipment receives the Sync message that clock equipment sends, and carries at least one timestamp t1 in each E1 message;
The second conversion equipment receives the second conversion equipment of the first conversion equipment transmission to the link delay of the first conversion equipment, wherein, described the second conversion equipment is to the link delay of the first conversion equipment, each the timestamp t3 carrying in a plurality of E1 messages that send according to the second conversion equipment for described the first conversion equipment, and receive that the moment t4 of the timestamp t3 of each E1 message determines;
Described the second conversion equipment makes from clockwork according to the first conversion equipment of determining and the link delay between the second conversion equipment, to the clock of self carry out to time.
Further, in order to guarantee the precision of clock synchronous, reduce the impact that jitter time delay causes clock synchronous, described the first conversion equipment sends the second conversion equipment and comprises to the link delay of the first conversion equipment:
When the second conversion equipment receives the Delay_Req message sending from clockwork, to the first conversion equipment, send a plurality of E1 messages, and add at least one timestamp t3 in each E1 message of correspondence;
The first conversion equipment is according to each moment t4 that receives the timestamp t3 in each E1 message, determine that the second conversion equipment is to the link delay of the first conversion equipment, and the second conversion equipment of determining is sent to the second conversion equipment to the link delay of the first conversion equipment.
Further, in order to guarantee the precision of clock synchronous, reduce the impact that jitter time delay causes clock synchronous, described the second conversion equipment makes from clockwork according to the first conversion equipment of determining and the link delay between the second conversion equipment, to the clock of self carry out to time comprise:
Described the second conversion equipment is according to the first conversion equipment of determining and the link delay between the second conversion equipment, clock to self is adjusted, and the clock information after adjusting is sent to from clockwork, make to adjust according to described clock information from clockwork the clock of self; Or,
Described the second conversion equipment sends to the first conversion equipment of determining and the link delay between the second conversion equipment from clockwork, makes from clockwork, according to the link delay between the first conversion equipment and the second conversion equipment, the clock of self to be adjusted.
Further, in order to guarantee the precision of clock synchronous, reduce the impact that jitter time delay causes clock synchronous, described according to the link delay between the first conversion equipment and the second conversion equipment, the clock adjustment of self is comprised:
Link delay according to the first conversion equipment of determining to the second conversion equipment, and the second conversion equipment is to the link delay of the first conversion equipment, determines average link time delay;
Link delay and average link time delay according to the first conversion equipment of determining to the second conversion equipment, determine clock equipment and from the time deviation of clockwork;
According to definite time deviation, the clock of self is adjusted.
Further, in order to improve the transmission rate of message, improve the efficiency of clock synchronous, described method also comprises:
Described the second conversion equipment and the first conversion equipment are split as a plurality of segments by clock synchronous message, are inserted in a plurality of E1 messages that carry timestamp and send; Or,
Described the second conversion equipment and the first conversion equipment are inserted into the information of other messages in a plurality of E1 messages that carry timestamp and send.
The embodiment of the present invention provides a kind of IEEE1588 clock synchronization apparatus based on E1 link, and described device comprises:
Link delay determination module, for basis, receive the moment t2 of a plurality of each timestamp t1 of E1 message, determine that the first conversion equipment is to the link delay of self, wherein said a plurality of E1 message is to send after the first conversion equipment receives the Sync message that clock equipment sends, and carries at least one timestamp t1 in each E1 message;
Receiver module, for receive that the first conversion equipment sends self to the link delay of the first conversion equipment, wherein, described self to the link delay of the first conversion equipment, each the timestamp t3 carrying in a plurality of E1 messages that send according to the second conversion equipment for described the first conversion equipment, and receive that the moment t4 of the timestamp t3 of each E1 message determines
Clock synchronization module, for making from clockwork according to the link delay between self and the second conversion equipment determined, to the clock of self carry out to time.
Further, in order to guarantee the precision of clock synchronous, reduce the impact that jitter time delay causes clock synchronous, described clock synchronization module, the first conversion equipment of determining specifically for basis and the link delay of self, clock to self is adjusted, and the clock information after adjusting is sent to from clockwork, makes to adjust according to described clock information from clockwork the clock of self; Or, the first conversion equipment of determining and the link delay of self are sent to from clockwork, make from clockwork, according to the first conversion equipment and the link delay of self, the clock of self to be adjusted.
Further, in order to guarantee the precision of clock synchronous, reduce the impact that jitter time delay causes clock synchronous, described clock synchronization module, specifically for the link delay to self according to the first conversion equipment of determining, and self is to the link delay of the first conversion equipment, determines average link time delay; Link delay and average link time delay according to the first conversion equipment of determining to self, determine clock equipment and from the time deviation of clockwork; According to definite time deviation, the clock of self is adjusted.
Further, in order to improve the transmission rate of message, improve the efficiency of clock synchronous, described device also comprises:
Sending module, sends for clock synchronous message being split as to a plurality of segments, being inserted in a plurality of E1 messages that carry timestamp; Or the information of other messages is inserted in a plurality of E1 messages that carry timestamp and is sent.
The embodiment of the present invention provides a kind of IEEE1588 clock synchronizing method based on E1 link, system and device, in the method with from clockwork, keep the second conversion equipment of clock synchronous, according to the moment t2 of each timestamp t1 in a plurality of E1 messages that receive, determine that the first conversion equipment is to the link delay between the second conversion equipment, and the second conversion equipment of the first conversion equipment transmission of reception and master clock maintenance clock synchronous is to the link delay of the first conversion equipment, according to the first conversion equipment of determining and the link delay between the second conversion equipment, make from clockwork to the clock of self carry out to time.Due in embodiments of the present invention by carrying out clock synchronous with keep the second conversion equipment of clock synchronous from clock, at conversion equipment, be that the sync message of coming in and going out is stamped timestamp, and by sending a plurality of E1 messages that carry timestamp, determine the time delay of link, thereby avoided the impact of E1 link delay shake, improved the precision of clock synchronous.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by the specific embodiment of the present invention.
Accompanying drawing explanation
By reading below detailed description of the preferred embodiment, various other advantage and benefits will become cheer and bright for those of ordinary skills.Accompanying drawing is only for the object of preferred implementation is shown, and do not think limitation of the present invention.And in whole accompanying drawing, by identical reference symbol, represent identical parts.In the accompanying drawings:
Fig. 1 is at the structure chart of the PTP message of SDH transmission over networks Ethernet bearing in prior art;
Fig. 2 carries out the concrete structure figure of clock synchronous based on E1 link in prior art;
A kind of IEEE1588 clock system structure chart based on E1 link that Fig. 3 provides for the embodiment of the present invention;
A kind of IEEE1588 clock synchronous process based on E1 link based on above-mentioned system shown in Figure 3 Organization Chart that Fig. 4 A provides for the embodiment of the present invention;
The assembling mode schematic diagram of a kind of E1 message that Fig. 4 B provides for the embodiment of the present invention;
The assembling mode schematic diagram of the another kind of E1 message that Fig. 4 C provides for the embodiment of the present invention;
A kind of IEEE1588 clock synchronous detailed process based on E1 link that Fig. 5 provides for the embodiment of the present invention;
A kind of IEEE1588 clock synchronization apparatus structure chart based on E1 link that Fig. 6 provides for the embodiment of the present invention.
Embodiment
For fear of the time delay that causes of the shake of E1 link, improved the precision of clock synchronous, the embodiment of the present invention provides a kind of IEEE1588 clock synchronizing method, system and device based on E1 link.
Exemplary embodiment of the present disclosure is described below with reference to accompanying drawings in more detail.Although shown exemplary embodiment of the present disclosure in accompanying drawing, yet should be appreciated that and can realize the disclosure and the embodiment that should do not set forth limits here with various forms.On the contrary, it is in order more thoroughly to understand the disclosure that these embodiment are provided, and can by the scope of the present disclosure complete convey to those skilled in the art.
Below in conjunction with explanation accompanying drawing, the embodiment of the present invention is described.
A kind of IEEE1588 clock system structure chart based on E1 link that Fig. 3 provides for the embodiment of the present invention, this system comprises: clock equipment 31, the first Ethernet and E1 conversion equipment 32, the second Ethernet and E1 conversion equipment 33 and from clockwork 34.Wherein, between clock equipment 31 and the first Ethernet and E1 conversion equipment 32, keep clock synchronous, the second Ethernet and E1 conversion equipment 33 and keep clock synchronous between clockwork 34.
In order to realize the time synchronized between master and slave clockwork and conversion equipment, in the first Ethernet and E1 conversion equipment 32 and the second Ethernet and E1 conversion equipment 33, be provided with high precision clock, by this high precision clock, keep the clock synchronous between conversion equipment and master and slave clockwork.
The first Ethernet and E1 conversion equipment 32 receive the Ethernet message that clock equipment 31 sends, judge whether this Ethernet message is Sync message, when definite this Ethernet message is Sync message, the first Ethernet and E1 conversion equipment 32 send a plurality of continuous E1 messages, and when sending each E1 message, in each E1 message, add at least one timestamp t1, each timestamp t1 is for adding the current time of this timestamp.
The second Ethernet and E1 conversion equipment 33 records receive the moment t2 of each timestamp t1 in each E1 message, and according to every couple of corresponding t2 and t1, determine the link delay of the first Ethernet and E1 conversion equipment 32 to second Ethernets and E1 conversion equipment 33.
In embodiments of the present invention, the first Ethernet and E1 conversion equipment 32 are sending to a plurality of E1 messages that carry timestamp after the second Ethernet and E1 conversion equipment 33, convert the Sync message receiving to a plurality of E1 messages, send to the second Ethernet and E1 conversion equipment 33, by the second Ethernet and E1 conversion equipment 33, this Sync message repeating is arrived from clockwork 34.
The second Ethernet and E1 conversion equipment 33 are when determining while receiving the Delay_Req message sending from clockwork 34, to the first Ethernet and E1 conversion equipment 32, send a plurality of continuous E1 messages, and when sending each E1 message, in each E1 message, add at least one timestamp t3, each timestamp t3 is for adding the current time of this timestamp.
The moment t4 of each timestamp t3 in each E1 message that the first Ethernet and E1 conversion equipment 32 record reception the second Ethernets and E1 conversion equipment 33 send, according to every couple of corresponding t4 and t3, determine the link delay of the second Ethernet and E1 conversion equipment 33 to first Ethernets and E1 conversion equipment 32, the first Ethernet and E1 conversion equipment 32 send to clock equipment 31 by the second Ethernet of determining and the link delay of E1 conversion equipment 33 to first Ethernets and E1 conversion equipment 32, when receiving the delay_resp message of clock equipment 31 transmissions, the second Ethernet of determining and the link delay of E1 conversion equipment 33 to first Ethernets and E1 conversion equipment 32 are sent to the second Ethernet and E1 conversion equipment 33.
The second Ethernet and E1 conversion equipment 33 make from clockwork according to the link delay of 33 of the first Ethernet of determining and E1 conversion equipment 32 and the second Ethernet and E1 conversion equipments, to the clock of self carry out to time.
The FPGA of the first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment adds timestamp in E1 message in the outlet of E1.
Concrete, in embodiments of the present invention owing to keeping clock synchronous between clockwork and the second Ethernet and E1 conversion equipment, therefore from clockwork, the clock of self is being carried out constantly, it can be the first clock adjustment to self of the second Ethernet and E1 conversion equipment, after make the clock adjustment to self from clockwork, also can be that the second Ethernet and E1 conversion equipment send to corresponding link delay information from clockwork, make the clock adjustment to self according to this link delay information from clockwork.
Described the second conversion equipment makes from clockwork according to the first conversion equipment of determining and the link delay between the second conversion equipment, to the clock of self carry out to time comprise:
Described the second conversion equipment is according to the first conversion equipment of determining and the link delay between the second conversion equipment, clock to self is adjusted, and the clock information after adjusting is sent to from clockwork, make to adjust according to described clock information from clockwork the clock of self; Or,
Described the second conversion equipment sends to the first conversion equipment of determining and the link delay between the second conversion equipment from clockwork, makes from clockwork, according to the link delay between the first conversion equipment and the second conversion equipment, the clock of self to be adjusted.
When adjusting according to link delay from clockwork the clock of self, the clock information after adjusting is sent to the second Ethernet and E1 conversion equipment, the clock information after the second Ethernet and E1 conversion equipment are adjusted according to this, adjusts the clock of self.
A kind of IEEE1588 clock synchronous process based on E1 link based on above-mentioned system shown in Figure 3 Organization Chart that Fig. 4 A provides for the embodiment of the present invention, this process comprises the following steps:
S401: the first Ethernet and E1 conversion equipment receive the Ethernet message that clock equipment sends, and judge whether this Ethernet message is Sync message, when judgment result is that while being, carries out step S402, otherwise, send after directly changing this message.
S402: the first Ethernet and E1 conversion equipment send a plurality of E1 messages, and when sending each E1 message, in this E1 message, add at least one timestamp t1, each timestamp t1 is the moment of current this timestamp of interpolation.
S403: the second Ethernet and E1 conversion equipment receive a plurality of E1 messages of the first Ethernet and the transmission of E1 conversion equipment, and according to the moment that receives timestamp t1 in each E1 message, determine the moment t2 that receives each timestamp, the second Ethernet and E1 conversion equipment, according to t2 and the t1 of a plurality of correspondences of determining, determine that the first Ethernet and E1 conversion equipment are to the link delay between the second Ethernet and E1 conversion equipment.
S404: when the second Ethernet and E1 conversion equipment receive the Ethernet message sending from clockwork, judge whether this Ethernet message is Delay_Req message, when judgment result is that while being, carry out step S405, otherwise, send after directly changing this message.
S405: the second Ethernet and E1 conversion equipment send a plurality of E1 messages, and when sending each E1 message, in this E1 message, add at least one timestamp t3, each timestamp t3 is the moment of current this timestamp of interpolation.
S406: the first Ethernet and E1 conversion equipment receive a plurality of E1 messages of the second Ethernet and the transmission of E1 conversion equipment, and according to the moment that receives timestamp t3 in each E1 message, determine the moment t4 that receives each timestamp, the first Ethernet and E1 conversion equipment, according to t4 and the t3 of a plurality of correspondences of determining, determine that the second Ethernet and E1 conversion equipment are to the link delay between the first Ethernet and E1 conversion equipment.
S407: the first Ethernet and E1 conversion equipment receive the Ethernet message that master clock sends, and judge whether this Ethernet message is Delay_Resp message, when judgment result is that while being, carries out step S408, otherwise, send after directly changing this message.
S408: the first Ethernet and E1 conversion equipment to the link delay between the first Ethernet and E1 conversion equipment, send to the second Ethernet and E1 conversion equipment by the second Ethernet of determining and E1 conversion equipment.
S409: the second Ethernet and E1 conversion equipment are according to the first conversion equipment of determining and the link delay between the second conversion equipment, clock to self is adjusted, and the clock information after adjusting is sent to from clockwork, make to adjust according to this clock information from clockwork the clock of self.
In embodiments of the present invention for when carrying out clock synchronous, reduce the shake of E1 link delay, when the first Ethernet and E1 conversion equipment and the second Ethernet and the judgement of E1 conversion equipment receive clock synchronous message, to opposite end, send a plurality of E1 messages, and carry at least one current timestamp information in each the E1 message sending, in order effectively to reduce the shake of E1 link delay, a plurality of E1 messages of transmission are preferably continuous.
Concrete, described method also comprises:
Described the second conversion equipment and the first conversion equipment are split as a plurality of segments by clock synchronous message, are inserted in a plurality of E1 messages that carry timestamp and send; Or,
Described the second conversion equipment and the first conversion equipment are inserted into the information of other messages in a plurality of E1 messages that carry timestamp and send.
Should can be used for for remaining byte of E1 message of transmitting time stamp tranmitting data register sync message, also can be used for sending other Ethernet message.
The complete E1 message sending for Ethernet and E1 conversion equipment, the length of this message is 32 bytes, but that initial first byte ST0 is used for is synchronous, can not be used for carrying any data.Therefore, each E1 message only has 31 bytes can be used for carrying data, but each timestamp needs 8 bytes.So can carry at most 3 timestamps in each E1 message, while carrying 3 timestamps in E1 message, E1 message also remains 7 bytes, while carrying 1 or 2 timestamps in E1 message, the remaining byte number of E1 message is more, therefore can adopt other data outside this E1 message transmitting time stamp, in E1 message, other bytes except timestamp are used for sending Ethernet message data in embodiments of the present invention.
For the position of timestamp in message fixed, be convenient to the time delay that link is calculated in conversion equipment identification, can adopt in embodiments of the present invention several forms to assemble E1 message.The assembling mode schematic diagram of a kind of E1 message as shown in Figure 4 B, in the figure after ST0, the continuous timestamp of putting three 8 bytes (origintimestamp), each timestamp is the time of current this timestamp of placement, and remaining 7 bytes are used for transmitting other Ethernet datas (data).
Or, the assembling mode schematic diagram of another kind of E1 message as shown in Figure 4 C, it after ST0, is the timestamp (origintimestamp) of 8 bytes, be the Ethernet data (data) of two bytes more afterwards, in addition be the timestamp (origintimestamp) of 8 bytes afterwards, be the Ethernet data (data) of two bytes more afterwards, and then be the timestamp (origintimestamp) of 8 bytes, be the Ethernet data (data) of three bytes more afterwards, thereby realize, three timestamps be encapsulated in an E1 message.
Again or, while only carrying a timestamp in E1 message, after ST0, be the timestamp of 8 bytes, 23 bytes are afterwards used for sending Ethernet message data; Or last 8 bytes of E1 message are timestamp, and remaining 23 byte is used for sending Ethernet message data etc.In the embodiment of the present invention, can also adopt other mode to assemble E1 message, as long as guarantee that the position of each timestamp in message is fixing.
Concrete, for when guaranteeing clock synchronous, improve data transmission efficiency, be somebody's turn to do for carrying the E1 message of timestamp in embodiments of the present invention, can also be for transmitting Ethernet message.While sending Ethernet message in E1 message, Ethernet message is split into a plurality of segments, each segment is inserted in E1 message and is sent.If current E1 message carries timestamp information, insert after Ethernet message, also have vacant position, spare bits is installed and is set to invalid data, for example during binary data, spare bits is set to complete 1.If current E1 message does not carry timestamp information, insert after Ethernet message, carry the position of timestamp information or carry the position of message information vacant in addition, spare bits is installed and is set to invalid data.
Work as in embodiments of the present invention the second Ethernet and E1 conversion equipment and determined each the timestamp t1 carrying in E1 message, and according to the moment t2 that receives the timestamp t1 carrying in each E1 message, can determine that the first Ethernet and E1 conversion equipment are to the link delay of the second Ethernet and E1 conversion equipment, the first Ethernet and E1 conversion equipment have been determined each the timestamp t3 carrying in E1 message, and according to the moment t4 that receives the timestamp t3 carrying in each E1 message, can determine that the second Ethernet and E1 conversion equipment are to the link delay of the first Ethernet and E1 conversion equipment.
Concrete, described definite the first conversion equipment comprises to the link delay of the second conversion equipment:
Remove several maximums and minimum value in definite a plurality of link delays, according to the mean value that removes the link delay after maximum and minimum value, determine that the first conversion equipment is to the link delay of the second conversion equipment;
Described definite the second conversion equipment comprises to the link delay of the first conversion equipment:
Remove several maximums and minimum value in definite a plurality of link delays, according to the mean value that removes the link delay after maximum and minimum value, determine that the second conversion equipment is to the link delay of the first conversion equipment.
In embodiments of the present invention owing to having carried a plurality of timestamps in E1 message, therefore the second Ethernet and E1 conversion equipment will receive a plurality of timestamps, in order effectively to reduce the impact of E1 link delay shake on clock synchronous, in embodiments of the present invention when the second Ethernet and E1 conversion equipment have determined that the first Ethernet and E1 conversion equipment are to the link delay of the second Ethernet and E1 conversion equipment, and first Ethernet and E1 conversion equipment determined that the second Ethernet and E1 conversion equipment are after the link delay of the first Ethernet and E1 conversion equipment, several maximums and minimum value in link delay are removed, remaining link delay can think substantially to reflect E1 link delay, get the mean value of remaining each link delay, be the link delay between the first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment.
After the link delay of having determined between the first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment, from clock to the clock of self carry out to time comprise:
According to the first conversion equipment of determining, to the link delay between the second conversion equipment, and the second conversion equipment is to the link delay between the first conversion equipment, determines average link time delay;
According to the first conversion equipment of determining, to the link delay between the second conversion equipment and average link time delay, determine clock equipment and from the time deviation of clockwork;
According to definite time deviation, the clock of self is adjusted.
For example, the first Ethernet and E1 conversion equipment are after determining the Sync message that receives clock equipment transmission, to the second Ethernet and E1 conversion equipment, send a plurality of E1 messages, in each E1 message, carry at least one timestamp information, in a plurality of E1 messages, carry altogether 2000 timestamp t1, in this E1 message, can carry three timestamps, can carry two timestamps, also can carry a timestamp.Work as accordingly the second Ethernet and E1 conversion equipment according to the moment that receives each timestamp, 2000 timestamp t2 have been determined, according to the difference of each t2 and t1, can determine 2000 delay1, the first Ethernet and E1 conversion equipment are to the time delay of the second Ethernet and E1 conversion equipment, in 2000 delay1, remove 20% maximum (400), 20% minimum (400), the mean value of delay1 according to remaining 60%, determines that the first Ethernet and E1 conversion equipment are to the time delay of the second Ethernet and E1 conversion equipment.
Fig. 5 is a kind of IEEE1588 clock synchronous detailed process based on E1 link that the embodiment of the present invention provides, and take to receive Sync message and describe as example, and this process comprises the following steps:
S501: the second Ethernet and E1 conversion equipment receive E1 message, judges while carrying timestamp in this E1 message, for the timestamp byte part in this E1 message, carry out step S502, other byte parts, carry out step S504.
S502: determine when this timestamp is effective, according to the moment that receives this timestamp t1, determine time of reception stamp t2.
S503: the transmitting-receiving time difference t2-t1 that determines each timestamp message, determine each delay1n, determine several maximums and minimum value in a plurality of delay1n, determine the mean value of residue delay1n, using this mean value as the first Ethernet and E1 conversion equipment to the link delay delay1 of the second Ethernet and E1 conversion equipment.
S504: E1 message is assembled into Ethernet message, and on deliver to self CPU.
S505: the CPU of the second Ethernet and E1 conversion equipment processes this message.
Due in embodiments of the present invention by carrying out clock synchronous with keep the second conversion equipment of clock synchronous from clock, at conversion equipment, be that the sync message of coming in and going out is stamped timestamp, and by sending a plurality of E1 messages, determine the time delay of link, thereby avoided the impact of E1 link delay shake, improved the precision of clock synchronous.
Below in conjunction with a specific embodiment, describe.
When the first Ethernet and E1 conversion equipment receive the Ethernet message of clock equipment transmission, according to the type of this message, judge when this message is the Sync message in clock synchronous message, FPGA in this first Ethernet and E1 conversion equipment sends a plurality of E1 messages, and in each E1 message, carry at least one timestamp t1, in a plurality of E1 messages, carry 2000 timestamp t1.And the first Ethernet and E1 conversion equipment are split as a plurality of segments by the Sync message receiving, and each segment is inserted in E1 message and is sent.
The second Ethernet and E1 conversion equipment receive each E1 message of the first Ethernet and the transmission of E1 conversion equipment, according to the position of carrying timestamp in E1 message, whether be valid data, determine whether this E1 message carries timestamp, when definite this E1 message carries timestamp, for the timestamp byte part in this message, according to the moment that receives each timestamp, by the FPGA of this second Ethernet and E1 conversion equipment, determine each time of reception stamp t2.For the Ethernet message part in this message, the second Ethernet and E1 conversion equipment are repacked this Ethernet message part, and the CPU that sends to self processes, and after the message conversion after processing afterwards, send to from clockwork.
The second Ethernet and E1 conversion equipment are poor according to every couple of transmitting-receiving timestamp t2 and t1's, determine that each first Ethernet and E1 conversion equipment are to the link delay delay1n of the second Ethernet and E1 conversion equipment, the second Ethernet and E1 conversion equipment are in 2000 delay1n that obtain, remove each 20% of minimum and maximum delay1n, determine the mean value of remaining 1200 delay1n, using this mean value as the first Ethernet and E1 conversion equipment to the link delay delay1 of the second Ethernet and E1 conversion equipment.
When the second Ethernet and E1 conversion equipment receive the Ethernet message sending from clockwork, according to the type of this message, judge when this message is the Delay_Req message in clock synchronous message, FPGA in this second Ethernet and E1 conversion equipment sends a plurality of E1 messages, and in each E1 message, carry at least one timestamp t3, in a plurality of E1 messages, carry 2000 timestamp t3.And the second Ethernet and E3 conversion equipment are split as a plurality of segments by the Delay_Req message receiving, and each segment is inserted in E1 message and is sent.
The first Ethernet and E1 conversion equipment receive each E1 message of the second Ethernet and the transmission of E1 conversion equipment, according to the position of carrying timestamp in E1 message, whether be valid data, determine whether this E1 message carries timestamp, when definite this E1 message carries timestamp, for the timestamp byte part in this message, according to the moment that receives each timestamp, by the FPGA of this first Ethernet and E1 conversion equipment, determine each time of reception stamp t4.For the Ethernet message part in this message, the first Ethernet and E1 conversion equipment are repacked this Ethernet message part, and the CPU that sends to self processes, and after the message conversion after processing afterwards, send to clock equipment.
The first Ethernet and E1 conversion equipment are poor according to every couple of transmitting-receiving timestamp t4 and t3's, determine that each second Ethernet and E1 conversion equipment are to the link delay delay2n of the first Ethernet and E1 conversion equipment, the first Ethernet and E1 conversion equipment are in 2000 delay2n that obtain, remove each 20% of minimum and maximum delay1n, determine the mean value of remaining 1200 delay1n, using this mean value as the second Ethernet and E1 conversion equipment to the link delay delay2 of the first Ethernet and E1 conversion equipment.
When the first Ethernet and E1 conversion equipment receive the Ethernet message of clock equipment transmission, according to the type of this message, judge when this message is the Delay_Resp message in clock synchronous message, this first Ethernet and E1 conversion equipment send to the second Ethernet and E1 conversion equipment by the second Ethernet of determining and E1 conversion equipment to the link delay delay2 of the first Ethernet and E1 conversion equipment.
The delay1 that the second Ethernet and E1 conversion equipment are definite according to self, and the mean value of the delay2 of the first Ethernet receiving and the transmission of E1 conversion equipment, determine the link delay delay between the first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment.
The second Ethernet and E1 conversion equipment have been determined after the link delay delay between the first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment, due to the clock of self with from the clock synchronous between clockwork, clock synchronous between the first Ethernet and E1 conversion equipment and master clock arrange, therefore clock equipment and from the time deviation between clockwork, is the time deviation between the first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment.This time deviation is the poor of delay1 and delay, i.e. poor to the link delay between the second conversion equipment and average link time delay of the first conversion equipment.Determine after this time deviation, according to this time deviation, adjust the clock of self, and the clock information after self is adjusted sends to from clockwork, make the clock of self to be adjusted according to this clock information from clockwork.
Or, the second Ethernet and E1 conversion equipment have been determined after the link delay delay between the first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment, link delay delay between this first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment is sent to from clockwork, from clockwork according to the link delay delay between this first Ethernet and E1 conversion equipment and the second Ethernet and E1 conversion equipment, clock to self is adjusted, and because the clock between clockwork and the second Ethernet and E1 conversion equipment keeps synchronous, from clockwork, the clock information adjusting is sent to the second Ethernet and E1 conversion equipment, make the second Ethernet and E1 conversion equipment according to the clock information after this adjustment, clock to self is adjusted.
A kind of IEEE1588 clock synchronization apparatus structure chart based on E1 link that Fig. 6 provides for the embodiment of the present invention, this device comprises:
Link delay determination module 61, for basis, receive the moment t2 of a plurality of each timestamp t1 of E1 message, determine that the first conversion equipment is to the link delay of self, wherein said a plurality of E1 message is to send after the first conversion equipment receives the Sync message that clock equipment sends, and carries at least one timestamp t1 in each E1 message;
Receiver module 62, for receive that the first conversion equipment sends self to the link delay of the first conversion equipment, wherein, described self to the link delay of the first conversion equipment, each the timestamp t3 carrying in a plurality of E1 messages that send according to the second conversion equipment for described the first conversion equipment, and receive that the moment t4 of the timestamp t3 of each E1 message determines;
Clock synchronization module 63, for making from clockwork according to the link delay between self and the second conversion equipment determined, to the clock of self carry out to time.
Described clock synchronization module 63, the first conversion equipment of determining specifically for basis and the link delay of self, clock to self is adjusted, and the clock information after adjusting is sent to from clockwork, makes to adjust according to described clock information from clockwork the clock of self; Or, the first conversion equipment of determining and the link delay of self are sent to from clockwork, make from clockwork, according to the first conversion equipment and the link delay of self, the clock of self to be adjusted.
Described clock synchronization module 63, specifically for the link delay to self according to the first conversion equipment of determining, and self is to the link delay of the first conversion equipment, determines average link time delay; Link delay and average link time delay according to the first conversion equipment of determining to self, determine clock equipment and from the time deviation of clockwork; According to definite time deviation, the clock of self is adjusted.
Described device also comprises:
Sending module 64, sends for clock synchronous message being split as to a plurality of segments, being inserted in a plurality of E1 messages that carry timestamp; Or the information of other messages is inserted in a plurality of E1 messages that carry timestamp and is sent.
Described link delay determination module 61, specifically for removing several maximums and the minimum value in definite a plurality of link delays, according to the mean value that removes the link delay after maximum and minimum value, determine that the first conversion equipment is to the link delay of the second conversion equipment.
The embodiment of the present invention provides a kind of IEEE1588 clock synchronizing method based on E1 link, system and device, in the method with from clockwork, keep the second conversion equipment of clock synchronous, according to the moment t2 of each timestamp t1 in a plurality of E1 messages that receive, determine that the first conversion equipment is to the link delay between the second conversion equipment, and the second conversion equipment of the first conversion equipment transmission of reception and master clock maintenance clock synchronous is to the link delay of the first conversion equipment, according to the first conversion equipment of determining and the link delay between the second conversion equipment, make from clockwork to the clock of self carry out to time.Due in embodiments of the present invention by carrying out clock synchronous with keep the second conversion equipment of clock synchronous from clock, at conversion equipment, be that the sync message of coming in and going out is stamped timestamp, and by sending a plurality of E1 messages that carry timestamp, determine the time delay of link, thereby avoided the impact of E1 link delay shake, improved the precision of clock synchronous.
The algorithm providing at this is intrinsic not relevant to any certain computer, virtual system or miscellaneous equipment with demonstration.Various general-purpose systems also can with based on using together with this teaching.According to description above, it is apparent constructing the desired structure of this type systematic.In addition, the present invention is not also for any certain programmed language.It should be understood that and can utilize various programming languages to realize content of the present invention described here, and the description of above language-specific being done is in order to disclose preferred forms of the present invention.
In the specification that provided herein, a large amount of details have been described.Yet, can understand, embodiments of the invention can not put into practice in the situation that there is no these details.In some instances, be not shown specifically known method, structure and technology, so that not fuzzy understanding of this description.
Similarly, be to be understood that, in order to simplify the disclosure and to help to understand one or more in each inventive aspect, in the above in the description of exemplary embodiment of the present invention, each feature of the present invention is grouped together into single embodiment, figure or sometimes in its description.Yet, the method for the disclosure should be construed to the following intention of reflection: the present invention for required protection requires than the more feature of feature of clearly recording in each claim.Or rather, as reflected in claims below, inventive aspect is to be less than all features of disclosed single embodiment above.Therefore, claims of following embodiment are incorporated to this embodiment thus clearly, and wherein each claim itself is as independent embodiment of the present invention.
Those skilled in the art are appreciated that and can the module in the equipment in embodiment are adaptively changed and they are arranged in one or more equipment different from this embodiment.Module in embodiment or unit or assembly can be combined into a module or unit or assembly, and can put them into a plurality of submodules or subelement or sub-component in addition.At least some in such feature and/or process or unit are mutually repelling, and can adopt any combination to combine all processes or the unit of disclosed all features in this specification (comprising claim, summary and the accompanying drawing followed) and disclosed any method like this or equipment.Unless clearly statement in addition, in this specification (comprising claim, summary and the accompanying drawing followed) disclosed each feature can be by providing identical, be equal to or the alternative features of similar object replaces.
In addition, those skilled in the art can understand, although embodiment more described herein comprise some feature rather than further feature included in other embodiment, the combination of the feature of different embodiment means within scope of the present invention and forms different embodiment.For example, in the following claims, the one of any of embodiment required for protection can be used with compound mode arbitrarily.
All parts embodiment of the present invention can realize with hardware, or realizes with the software module moved on one or more processor, or realizes with their combination.Those skilled in the art is to be understood that, can use in practice microprocessor or digital signal processor (DSP) to realize IEEE1588 clock synchronization apparatus and the system based on E1 link of passing through according to the embodiment of the present invention, the some or all functions of the some or all parts in terminal equipment and system.The present invention for example can also be embodied as, for carrying out part or all equipment or device program (, computer program and computer program) of method as described herein.Realizing program of the present invention and can be stored on computer-readable medium like this, or can there is the form of one or more signal.Such signal can be downloaded and obtain from internet website, or provides on carrier signal, or provides with any other form.
It should be noted above-described embodiment the present invention will be described rather than limit the invention, and those skilled in the art can design alternative embodiment in the situation that do not depart from the scope of claims.In the claims, any reference symbol between bracket should be configured to limitations on claims.Word " comprises " not to be got rid of existence and is not listed as element or step in the claims.Being positioned at word " " before element or " one " does not get rid of and has a plurality of such elements.The present invention can be by means of including the hardware of some different elements and realizing by means of the computer of suitably programming.In having enumerated the unit claim of some devices, several in these devices can be to carry out imbody by same hardware branch.The use of word first, second and C grade does not represent any order.Can be title by these word explanations.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. the IEEE1588 clock synchronizing method based on E1 link, it is characterized in that, the first conversion equipment and clock equipment keep clock synchronous, the second conversion equipment with from clock, keep clock synchronous, the first conversion equipment and the second conversion equipment are for realizing the conversion between Ethernet message and E1 message, and the method comprises:
The second conversion equipment is according to the moment t2 that receives each timestamp t1 in a plurality of E1 messages, determine that the first conversion equipment is to the link delay of the second conversion equipment, wherein said a plurality of E1 message is to send after the first conversion equipment receives the Sync message that clock equipment sends, and carries at least one timestamp t1 in each E1 message;
The second conversion equipment receives the second conversion equipment of the first conversion equipment transmission to the link delay of the first conversion equipment, wherein, described the second conversion equipment is to the link delay of the first conversion equipment, each the timestamp t3 carrying in a plurality of E1 messages that send according to the second conversion equipment for described the first conversion equipment, and receive that the moment t4 of the timestamp t3 of each E1 message determines;
Described the second conversion equipment makes from clockwork according to the first conversion equipment of determining and the link delay between the second conversion equipment, to the clock of self carry out to time.
2. the method for claim 1, is characterized in that, described the first conversion equipment sends the second conversion equipment and comprises to the link delay of the first conversion equipment:
When the second conversion equipment receives the Delay_Req message sending from clockwork, to the first conversion equipment, send a plurality of E1 messages, and add at least one timestamp t3 in each E1 message of correspondence;
The first conversion equipment is according to each moment t4 that receives the timestamp t3 in each E1 message, determine that the second conversion equipment is to the link delay of the first conversion equipment, and the second conversion equipment of determining is sent to the second conversion equipment to the link delay of the first conversion equipment.
3. method as claimed in claim 1 or 2, is characterized in that, described the second conversion equipment makes from clockwork according to the first conversion equipment of determining and the link delay between the second conversion equipment, to the clock of self carry out to time comprise:
Described the second conversion equipment is according to the first conversion equipment of determining and the link delay between the second conversion equipment, clock to self is adjusted, and the clock information after adjusting is sent to from clockwork, make to adjust according to described clock information from clockwork the clock of self; Or,
Described the second conversion equipment sends to the first conversion equipment of determining and the link delay between the second conversion equipment from clockwork, makes from clockwork, according to the link delay between the first conversion equipment and the second conversion equipment, the clock of self to be adjusted.
4. the method as described in claim 1 or 3, is characterized in that, described according to the link delay between the first conversion equipment and the second conversion equipment, and the clock adjustment of self is comprised:
Link delay according to the first conversion equipment of determining to the second conversion equipment, and the second conversion equipment is to the link delay of the first conversion equipment, determines average link time delay;
According to the first conversion equipment of determining, to the link delay between the second conversion equipment and average link time delay, determine clock equipment and from the time deviation of clockwork;
According to definite time deviation, the clock of self is adjusted.
5. the method for claim 1, is characterized in that, described method also comprises:
Described the second conversion equipment and the first conversion equipment are split as a plurality of segments by clock synchronous message, are inserted in each the E1 message that carries timestamp and send; Or,
Described the second conversion equipment and the first conversion equipment are inserted into the information of other messages in a plurality of E1 messages that carry timestamp and send.
6. the IEEE1588 clock synchronization apparatus based on E1 link, is characterized in that, described device comprises:
Link delay determination module, for basis, receive the moment t2 of a plurality of each timestamp t1 of E1 message, determine that the first conversion equipment is to the link delay of self, wherein said a plurality of E1 message is to send after the first conversion equipment receives the Sync message that clock equipment sends, and carries at least one timestamp t1 in each E1 message;
Receiver module, for receive that the first conversion equipment sends self to the link delay of the first conversion equipment, wherein, described self to the link delay of the first conversion equipment, each the timestamp t3 carrying in a plurality of E1 messages that send according to the second conversion equipment for described the first conversion equipment, and receive that the moment t4 of the timestamp t3 of each E1 message determines;
Clock synchronization module, for making from clockwork according to the link delay between self and the second conversion equipment determined, to the clock of self carry out to time.
7. device as claimed in claim 6, it is characterized in that, described clock synchronization module, the first conversion equipment of determining specifically for basis and the link delay of self, clock to self is adjusted, and the clock information after adjusting is sent to from clockwork, make to adjust according to described clock information from clockwork the clock of self; Or, the first conversion equipment of determining and the link delay of self are sent to from clockwork, make from clockwork, according to the first conversion equipment and the link delay of self, the clock of self to be adjusted.
8. the device as described in claim 6 or 7, is characterized in that, described clock synchronization module, and specifically for the link delay to self according to the first conversion equipment of determining, and self is to the link delay of the first conversion equipment, determines average link time delay; Link delay and average link time delay according to the first conversion equipment of determining to self, determine clock equipment and from the time deviation of clockwork; According to definite time deviation, the clock of self is adjusted.
9. device as claimed in claim 6, is characterized in that, described device also comprises:
Sending module, sends for clock synchronous message being split as to a plurality of segments, being inserted in a plurality of E1 messages that carry timestamp; Or the information of other messages is inserted in a plurality of E1 messages that carry timestamp and is sent.
10. the IEEE1588 clock system based on E1 link, it is characterized in that, described system comprises: the device as described in as arbitrary in claim 6～9, with described device keep clock synchronous from clockwork, the first conversion equipment and keep the clock equipment of clock synchronous with this first conversion equipment.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410326095.6A CN104202137A (en) | 2014-07-09 | 2014-07-09 | IEEE1588 clock synchronization method, system and device based on E1 link |
| PCT/CN2014/082620 WO2016004645A1 (en) | 2014-07-09 | 2014-07-21 | Ieee1588 clock synchronization method, system and apparatus based on e1 link |
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| CN201410326095.6A CN104202137A (en) | 2014-07-09 | 2014-07-09 | IEEE1588 clock synchronization method, system and device based on E1 link |
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| CN106385299A (en) * | 2016-09-22 | 2017-02-08 | 国家电网公司 | Master-slave clock synchronization method of maintenance service class information background flow of intelligent substation |
| CN107786319A (en) * | 2016-08-25 | 2018-03-09 | 南京中兴新软件有限责任公司 | A kind of method for synchronizing time and device |
| CN112202519A (en) * | 2020-08-26 | 2021-01-08 | 浙江双成电气有限公司 | Method for controlling message transmission delay jitter |
| CN112751641A (en) * | 2020-12-31 | 2021-05-04 | 网络通信与安全紫金山实验室 | TSN network time synchronization method, equipment and storage medium |
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| CN112202519A (en) * | 2020-08-26 | 2021-01-08 | 浙江双成电气有限公司 | Method for controlling message transmission delay jitter |
| CN112751641A (en) * | 2020-12-31 | 2021-05-04 | 网络通信与安全紫金山实验室 | TSN network time synchronization method, equipment and storage medium |
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| WO2016004645A1 (en) | 2016-01-14 |
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