CN115801176A

CN115801176A - Cross-platform clock synchronization method, device and storage medium based on PTP (precision time protocol)

Info

Publication number: CN115801176A
Application number: CN202310063248.1A
Authority: CN
Inventors: 吴勇刚; 张建光; 彭高领; 刘新龙; 钱林林; 唐程辉; 赵维; 郑文浩
Original assignee: Beijing Tasson Science and Technology Co Ltd
Current assignee: Beijing Tasson Science and Technology Co Ltd
Priority date: 2023-01-19
Filing date: 2023-01-19
Publication date: 2023-03-14

Abstract

The invention relates to the technical field of communication, and provides a cross-platform clock synchronization method, a cross-platform clock synchronization device and a cross-platform clock synchronization storage medium based on a PTP (precision time protocol), wherein the method comprises the following steps: receiving a synchronous packet sent by a main clock through a first interface to obtain first timestamp data; receiving a following packet sent by a main clock through a second interface; the following packet contains second time stamp data; sending a delay request packet to the master clock through a third interface, and acquiring third timestamp data; receiving a delay request response packet sent by a master clock through a fourth interface; the delayed request packet response contains fourth timestamp data; clock synchronization is performed with the master clock based on the first time stamp data, the second time stamp data, the third time stamp data, and the fourth time stamp data. The cross-platform clock synchronization method based on the PTP realizes the conversion of the protocol by presetting a plurality of interfaces, can be suitable for a vxworks system and a linux system, and realizes cross-platform clock synchronization.

Description

Cross-platform clock synchronization method, device and storage medium based on PTP (precision time protocol)

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method, an apparatus, and a storage medium for cross-platform clock synchronization based on a PTP protocol.

Background

Network clock synchronization technologies used in the industry include Network Time Protocol (NTP), precision Time Protocol (PTP), global Positioning System (GPS), beidou, and many dedicated devices implemented using Field Programmable Gate Array (FPGA).

The NTP transmission mode is adopted to realize clock synchronization, and the requirement of time transmission precision of ms level can be met only, which is far from sufficient for ns level time precision required by high-precision time synchronization. The GPS time synchronization system adopting the one-way channel has the advantages of stable and reliable acquisition of the synchronization signal and high precision, but has high price, great construction difficulty and high failure rate.

Compared with the traditional time service technology, the PTP has obvious advantages. It adopts bidirectional channel, the precision is ns grade, the cost is low, it can adapt to different access environment.

In the prior art, clock synchronization better than one microsecond is usually realized by special hardware or an FPGA, and then is forwarded to other devices through a serial port or a custom protocol. Although accuracy can be ensured, there are the following disadvantages: when the clock synchronization is realized through the special hardware or the FPGA, the special hardware or the FPGA is designed specially, and the problems of incompatibility and inflexible expansion and change can occur.

Disclosure of Invention

The invention provides a cross-platform clock synchronization method, a cross-platform clock synchronization device and a storage medium based on a PTP (precision time protocol), which are used for solving the defect of incompatibility when clock synchronization is carried out through special hardware or an FPGA (field programmable gate array) in the prior art and realizing cross-platform clock synchronization based on the PTP.

The invention provides a cross-platform clock synchronization method based on a PTP (precision time protocol), which is applied to a slave clock and comprises the following steps:

receiving a synchronous packet sent by a main clock through a first interface to obtain first timestamp data; the first timestamp data is the data of the network card at the receiving moment of the synchronous packet;

receiving a follow-up packet sent by the master clock through a second interface; the following packet comprises second time stamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

sending a delay request packet to the master clock through a third interface, and acquiring third timestamp data; the third timestamp data is data of the network card at the time of sending the delay request packet;

receiving a delayed request response packet sent by the master clock through a fourth interface; the delayed request packet response comprises fourth time stamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

performing clock synchronization with the master clock based on the first time stamp data, the second time stamp data, the third time stamp data, and the fourth time stamp data.

In some embodiments, said clock synchronizing with said master clock based on said first time stamp data, said second time stamp data, said third time stamp data, and said fourth time stamp data comprises:

determining target adjustment data based on the first time stamp data, the second time stamp data, the third time stamp data, and the fourth time stamp data;

and adjusting the phase and frequency of the slave clock based on the target adjustment data to perform clock synchronization with the master clock.

In some embodiments, the obtaining first timestamp data comprises:

and acquiring the first timestamp data at the network card through a timestamp acquisition interface.

In some embodiments, the obtaining first timestamp data comprises:

and acquiring the first timestamp data in a time register by reading a network card timestamp interface.

The invention provides a cross-platform clock synchronization method based on a PTP (precision time protocol), which is applied to a master clock and comprises the following steps:

sending a synchronization packet to a slave clock through a fifth interface to acquire second timestamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

transmitting a follower packet to the slave clock through a sixth transmission interface; the following packet contains the second timestamp data;

receiving a delay request packet sent by the slave clock through a seventh interface to acquire fourth timestamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

transmitting a delay request response packet to the slave clock through an eighth transmission interface; the delayed request packet reply includes the fourth timestamp data therein;

the second time stamp data and the fourth time stamp data are used for clock synchronization of the slave clock.

In some embodiments, before the sending the synchronization packet to the slave clock through the fifth interface and acquiring the second timestamp data, the method further includes:

sending a master station data message to the local area network through the synchronous declaration interface; the master station data message is used for determining the master clock.

The invention also provides a cross-platform clock synchronization device based on the PTP protocol, which comprises:

the first receiving module is used for receiving a synchronization packet sent by a main clock through a first interface and acquiring first timestamp data; the first timestamp data is data of the network card at the receiving moment of the synchronization packet;

the second receiving module is used for receiving the following packet sent by the master clock through a second interface; the following packet comprises second time stamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

the first sending module is used for sending a delay request packet to the master clock through a third interface and acquiring third timestamp data; the third timestamp data is data of the network card at the time of sending the delay request packet;

a third receiving module, configured to receive, through a fourth interface, a delay request response packet sent by the master clock; the delayed request packet response comprises fourth time stamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

a synchronization module to perform clock synchronization with the master clock based on the first timestamp data, the second timestamp data, the third timestamp data, and the fourth timestamp data.

the second sending module is used for sending a synchronization packet to the slave clock through the fifth interface to acquire second timestamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

a third sending module, configured to send a following packet to the slave clock through a sixth sending interface; the following packet contains the second timestamp data;

a fourth receiving module, configured to receive, through a seventh interface, the delay request packet sent by the slave clock, and obtain fourth timestamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

a fourth sending module, configured to send a delay request response packet to the slave clock through an eighth sending interface; the delayed request packet reply includes the fourth timestamp data therein;

The invention also provides an electronic device, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the cross-platform clock synchronization method based on the PTP protocol.

The present invention also provides a non-transitory computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements a cross-platform clock synchronization method based on a PTP protocol as in any one of the above.

The present invention also provides a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the cross-platform clock synchronization method based on PTP protocol as in any one of the above.

The cross-platform clock synchronization method, device and storage medium based on the PTP protocol, provided by the invention, realize the conversion of the protocol by presetting a plurality of interfaces, and can be suitable for vxworks systems and linux systems, so that cross-platform clock synchronization is realized, the sub-microsecond level time synchronization precision is met, the debugging is convenient, and the expansion and the change are flexible.

Drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

Fig. 1 is a schematic flowchart of a cross-platform clock synchronization method based on a PTP protocol according to an embodiment of the present invention;

FIG. 2 is a schematic design flow diagram of a synchronous control interface provided in an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a design flow of a synchronous packet processing interface according to an embodiment of the present invention;

fig. 4 is a schematic design flow diagram of a follow-up packet transmission interface according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a design flow of a follow-up packet processing interface according to an embodiment of the present invention;

fig. 6 is a schematic design flow diagram of a delay request packet sending interface according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a design flow of a deferred request packet processing interface according to an embodiment of the present invention;

fig. 8 is a schematic design flow diagram of a delayed request response packet transmission interface according to an embodiment of the present invention;

fig. 9 is a schematic design flow diagram of a delayed request response packet processing interface according to an embodiment of the present invention;

FIG. 10 is a schematic design flow diagram of an upper proportional-integral algorithm interface according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a design flow of a clock phase adjustment interface according to an embodiment of the present invention;

FIG. 12 is a schematic design flow diagram of a clock frequency adjustment interface according to an embodiment of the present invention;

FIG. 13 is a second schematic diagram illustrating a design flow of a clock phase adjustment interface according to an embodiment of the present invention;

FIG. 14 is a second schematic diagram illustrating a design flow of a clock frequency adjustment interface according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of a design flow of a clock acquisition interface according to an embodiment of the present invention;

fig. 16 is a schematic design flow diagram of an interface for acquiring a network card timestamp at a message sending time according to an embodiment of the present invention;

fig. 17 is a schematic diagram of a design flow for obtaining a network card timestamp interface at a message receiving time according to an embodiment of the present invention;

fig. 18 is a schematic design flow diagram of an interface for reading a timestamp of a network card according to an embodiment of the present invention;

fig. 19 is a schematic design flow diagram of an interface for setting a network card timestamp according to an embodiment of the present invention;

fig. 20 is a second flowchart of a cross-platform clock synchronization method based on PTP protocol according to an embodiment of the present invention;

FIG. 21 is a schematic design flow diagram of a synchronous declaration interface provided by an embodiment of the present invention;

fig. 22 is a schematic structural diagram of a cross-platform clock synchronization apparatus based on a PTP protocol according to an embodiment of the present invention;

fig. 23 is a second schematic structural diagram of a cross-platform clock synchronization apparatus based on a PTP protocol according to an embodiment of the present invention;

fig. 24 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The IEEE1588 protocol, also known as PTP protocol, can achieve sub-microsecond level time synchronization precision. A Delay Request-Response Mechanism (Delay Request-Response Mechanism) proposed by a synchronization principle of an IEEE1588 protocol has a message receiving and sending process as follows:

step 1, a master clock periodically sends out a sync message, and records the accurate sending time t1 when the sync message leaves the master clock;

step 2, the master clock encapsulates the accurate sending time t1 into a Follow _ up message and sends the Follow _ up message to the slave clock;

since the sync message cannot carry accurate message leaving time, an accurate sending timestamp t1 of the sync message is packaged in a following Follow _ up message and sent to a slave clock;

step 3, the slave clock records the accurate time reaching time t2 when the sync message reaches the slave clock;

step 4, sending a delay _ req message from the clock and recording the accurate sending time t3;

step 5, the main clock records the accurate arrival time t4 when the delay _ req message arrives at the main clock;

step 6, the master clock sends a delay _ resp message carrying accurate timestamp information t4 to the slave clock;

and 7, obtaining four accurate message receiving and sending times of t1, t2, t3 and t4 from the clock.

Calculating clock deviation and network delay:

offset: inter-clock skew (time skew between master and slave clocks);

delay: network latency (latency introduced by the transmission of messages in the network);

the slave clock can obtain the master-slave clock offset and the transmission delay through four accurate timestamp information of t1, t2, t3 and t 4:

t2 = t1+ delay + offset

t4 = t3+ delay - offset

solving the equation yields:

；

the time synchronization can be performed by correcting the local clock after the offset and delay are obtained from the clock.

Fig. 1 is a schematic flowchart of a PTP protocol-based cross-platform clock synchronization method according to an embodiment of the present invention, and referring to fig. 1, the PTP protocol-based cross-platform clock synchronization method according to an embodiment of the present invention includes:

step 101, receiving a synchronization packet sent by a master clock through a first interface to obtain first timestamp data; the first timestamp data is the data of the network card at the receiving moment of the synchronous packet;

102, receiving a follow-up packet sent by the master clock through a second interface; the following packet comprises second time stamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

103, sending a delay request packet to the master clock through a third interface, and acquiring third timestamp data; the third timestamp data is data of the network card at the time of sending the delay request packet;

step 104, receiving a delay request response packet sent by the master clock through a fourth interface; the delayed request packet response comprises fourth time stamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

step 105, performing clock synchronization with the master clock based on the first time stamp data, the second time stamp data, the third time stamp data and the fourth time stamp data.

In step 101, a synchronization packet sent by a master clock is received through a first interface, and first timestamp data is acquired.

Optionally, the master clock sends a synchronization packet to the slave clock through the synchronization control interface, fig. 2 is a schematic diagram of a design flow of the synchronization control interface provided in the embodiment of the present invention, and as shown in fig. 2, the synchronization control interface calls a driver to read hardware time, converts the hardware time into a timestamp data format, and packages the timestamp data format into a synchronization data packet and sends the synchronization data packet. If the transmission is successful, the timestamp data of the synchronous frame data is transmitted by using the following data message.

And the slave clock receives the synchronous packet sent by the master clock through a first interface, wherein the first interface can be a synchronous packet processing interface and records first timestamp data, and the first timestamp data is data of the network card at the moment of receiving the synchronous packet. Fig. 3 is a schematic diagram of a design flow of a synchronization packet processing interface according to an embodiment of the present invention, and as shown in fig. 3, when a synchronization packet message interface is received, a synchronization frame timestamp data is parsed, a timestamp is converted into a time data, and the parsed time data is used to update a clock bias and update a local time.

In step 102, a follow packet sent by the master clock is received through a second interface.

Optionally, the master clock sends a follow packet to the slave clock through a follow packet sending interface, fig. 4 is a schematic diagram of a design flow of the follow packet sending interface according to an embodiment of the present invention, as shown in fig. 4, in a 2-step system, a synchronous frame data packet cannot send a timestamp data of a data leaving network card in a carrying manner when sending the data, that is, a second timestamp data, and the second timestamp data of the network card at the time when the synchronous frame data leaves the network card is sent by the follow packet.

The slave clock receives a following packet sent by the master clock through a second interface, where the second interface may be a following packet processing interface, fig. 5 is a schematic diagram of a design flow of the following packet processing interface according to an embodiment of the present invention, and as shown in fig. 5, the following packet processing interface is received, the following inter-frame stamp data is analyzed, the second timestamp is converted into time data, the analyzed time data is used to update the PTP clock, update the clock bias, and update the local time.

In step 103, a delay request packet is sent to the master clock through a third interface, and third timestamp data is obtained.

And the slave clock sends a delay request packet to the master clock through a third interface, wherein the third interface can be a delay request packet sending interface and acquires third timestamp data, and the third timestamp data is data of the network card at the sending moment of the delay request packet. Fig. 6 is a schematic diagram of a design flow of a delay request packet sending interface according to an embodiment of the present invention, and as shown in fig. 6, an end-to-end delay measurement process is started through an end-to-end delay request packet. And converting the input parameters into a time stamp format, and packaging the time stamp format into delay request data for transmission.

Optionally, the master clock receives the delay request packet through the delay request packet processing interface, and fig. 7 is a schematic diagram of a design flow of the delay request packet processing interface according to the embodiment of the present invention, and as shown in fig. 7, receives an end-to-end delay request data packet, parses delay request timestamp data, and sends a delay request response packet.

In step 104, a delayed request acknowledgement packet sent by the master clock is received through a fourth interface.

Fig. 8 is a schematic diagram illustrating a design flow of a delay request response packet sending interface according to an embodiment of the present invention, and as shown in fig. 8, after receiving an end-to-end delay request packet, a master clock invokes a driver to read hardware time, converts the hardware time into a timestamp data format, that is, fourth timestamp data, and encapsulates the timestamp data into a delay request response packet.

A slave clock receives a delayed request response packet sent by the master clock through a fourth interface, where the fourth interface may be a delayed request response packet processing interface, fig. 9 is a schematic view of a design flow of the delayed request response packet processing interface according to the embodiment of the present invention, and as shown in fig. 9, an end-to-end delayed request response data packet is received, a delayed request timestamp data is analyzed, a fourth timestamp data is obtained, the timestamp is converted into an available timestamp data, and clock delay is updated.

In step 105, clock synchronization is performed with the master clock based on the first time stamp data, the second time stamp data, the third time stamp data, and the fourth time stamp data.

Optionally, the slave clock calculates a clock offset according to the acquired first timestamp data, second timestamp data, third timestamp data, and fourth timestamp data according to a PTP protocol, uses the clock offset as an input of a servo algorithm PID, obtains available clock offset data through a PID algorithm, adds the clock offset data to local actual time, and writes the clock offset data into a clock register, thereby updating clock delay and network delay, and performing clock synchronization with the master clock.

The cross-platform clock synchronization method based on the PTP protocol provided by the embodiment of the invention realizes the conversion of the protocol by presetting a plurality of interfaces, and can be suitable for vxworks systems and linux systems, thereby realizing cross-platform clock synchronization, meeting the sub-microsecond level time synchronization precision, being convenient for debugging and being flexible in extension and change.

determining target adjustment data based on the first, second, third, and fourth timestamp data;

Optionally, the target adjustment data may be obtained by performing calculation through a proportional-integral servo algorithm interface according to the first time stamp data, the second time stamp data, the third time stamp data, and the fourth time stamp data. Fig. 10 is a schematic design flow diagram of an interface of an upper layer proportional-integral algorithm according to an embodiment of the present invention, and as shown in fig. 10, phase data and frequency data to be adjusted are obtained by calculation using timestamp data acquired from a slave driver, and a phase and a frequency of a slave clock are approximated to a master clock through a protocol layer interface, so that stable tracking and synchronization of the phase and the frequency are realized, and a main file and an interface are designed and implemented. A proportional integral servo interface is implemented.

Optionally, when the method is applied to a vxworks system, fig. 11 is one of the design flow diagrams of the clock phase adjustment interface provided in the embodiment of the present invention, and as shown in fig. 11, the clock phase adjustment interface modifies the PTP hardware clock phase of the network card by inputting specified adjustment data, and the modification is divided into positive adjustment and negative adjustment.

Fig. 12 is a schematic diagram of a design flow of a clock frequency adjustment interface according to an embodiment of the present invention, and as shown in fig. 12, the clock frequency adjustment interface modifies a crystal oscillator frequency of a PTP hardware clock of a network card by using input specified adjustment data, and the modification is divided into positive adjustment and negative adjustment.

Optionally, when the method is applied to a linux system, fig. 13 is a second schematic design flow diagram of the clock phase adjustment interface according to the embodiment of the present invention, and as shown in fig. 13, the clock phase adjustment interface modifies the PTP hardware clock phase of the network card by using the input specified adjustment data, and the modification is divided into positive adjustment and negative adjustment.

Fig. 14 is a second schematic diagram of the design process of the clock frequency adjustment interface according to the embodiment of the present invention, and as shown in fig. 14, the clock frequency adjustment interface modifies the crystal frequency of the PTP hardware clock of the network card by using the input specified adjustment data, and the modification is divided into positive adjustment and negative adjustment.

The cross-platform clock synchronization method based on the PTP protocol provided by the embodiment of the invention can realize the clock synchronization between the network cards and the system by applying the proportional-integral servo algorithm to the network clock synchronization.

In some embodiments, the obtaining first timestamp data comprises:

Optionally, when the clock acquisition interface is applied to a vxworks system, fig. 15 is a schematic design flow diagram of the clock acquisition interface according to the embodiment of the present invention, and as shown in fig. 15, the clock acquisition interface acquires timestamp data from a network card, and in order to ensure data security, a pair of resource locks needs to be used for operation protection.

Fig. 16 is a schematic diagram of a design flow for obtaining a network card timestamp interface at a message sending time according to an embodiment of the present invention, and as shown in fig. 16, a timestamp data interface of a network card at a network data message sending time is obtained and is entered into a relevant field of the data message. When the data message with the timestamp needs to be sent, the driver can automatically set the sending timestamp control register, and the timestamp reading operation is carried out after the flag bit is judged to be effective by reading the flag bit first.

Fig. 17 is a schematic diagram of a design flow for obtaining a timestamp interface of a network card at a message receiving time according to an embodiment of the present invention, and as shown in fig. 17, a timestamp data interface of a network card at a network data receiving time is obtained, and the timestamp is entered into a relevant field of the data message. When the data message with the timestamp reaches the network interface, the driver can automatically set the receiving timestamp control register, and the timestamp reading operation is carried out after the flag bit is read and judged to be valid.

In some embodiments, the obtaining first timestamp data comprises:

Optionally, when the interface is applied to a linux system, fig. 18 is a schematic design flow diagram of the interface for reading the network card timestamp provided in the embodiment of the present invention, and as shown in fig. 18, reading the network card timestamp requires reading the system time register once, and then reading the low byte and the high byte of the time register, so as to obtain second data and nanosecond data from the read data.

Fig. 19 is a schematic diagram of a design flow of an interface for setting a network card timestamp according to an embodiment of the present invention, and as shown in fig. 19, a network card clock timestamp is set, and nanosecond data is written to a low byte address first, and then second data is written to a high byte address.

Fig. 20 is a second flowchart of the PTP protocol-based cross-platform clock synchronization method according to the embodiment of the present invention, and referring to fig. 20, the PTP protocol-based cross-platform clock synchronization method according to the embodiment of the present invention includes:

step 2001, sending a synchronization packet to a slave clock through a fifth interface to obtain second timestamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

step 2002, sending a follow-up packet to the slave clock through a sixth sending interface; the following packet contains the second timestamp data;

step 2003, receiving the delay request packet sent by the slave clock through a seventh interface, and acquiring fourth timestamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

step 2004, transmitting a delay request response packet to the slave clock through an eighth transmission interface; the delayed request packet reply includes the fourth timestamp data therein;

In step 2001, a synchronization packet is transmitted to the slave clock through the fifth interface, and the second time stamp data is acquired.

Optionally, the master clock sends a synchronization packet to the slave clock through a fifth interface, where the fifth interface may be a synchronization control interface, and fig. 2 is a schematic design flow diagram of the synchronization control interface provided in the embodiment of the present invention, and as shown in fig. 2, the synchronization control interface calls a driver to read hardware time, converts the hardware time into a timestamp data format, and packages the timestamp data format into a synchronization data packet, and then sends the synchronization data packet. If the transmission is successful, the timestamp data of the synchronous frame data is transmitted by using the following data message.

And the slave clock receives a synchronization packet sent by the master clock through a first interface, wherein the first interface can be a synchronization packet processing interface and acquires first timestamp data, and the first timestamp data is data of a network card at the moment of receiving the synchronization packet. Fig. 3 is a schematic diagram of a design flow of a synchronization packet processing interface according to an embodiment of the present invention, and as shown in fig. 3, when a synchronization packet message interface is received, a synchronization frame timestamp data is parsed, a timestamp is converted into a time data, and the parsed time data is used to update a clock bias and update a local time.

In step 2002, a follower packet is transmitted to the slave clock through a sixth transmit interface.

As shown in fig. 4, in a 2-step system, a synchronous frame data message cannot carry and send timestamp data of data leaving a network card when the data is sent, that is, second timestamp data, and the second timestamp data of the network card at the time when the synchronous frame data leaves the network card is sent by the following message.

In step 2003, a delay request packet sent by the slave clock is received through a seventh interface, and fourth timestamp data is obtained.

And the slave clock sends a delay request packet to the master clock through a third interface, wherein the third interface can be a delay request packet sending interface and acquires third timestamp data, and the third timestamp data is data of the network card at the moment of sending the delay request packet. Fig. 6 is a schematic diagram of a design flow of a delay request packet sending interface according to an embodiment of the present invention, and as shown in fig. 6, an end-to-end delay measurement process is started through an end-to-end delay request packet. And converting the input parameters into a time stamp format, and packaging the time stamp format into delay request data for sending.

Optionally, the master clock receives the delay request packet through a seventh interface, where the seventh interface may be a delay request packet processing interface, fig. 7 is a schematic design flow diagram of the delay request packet processing interface provided in the embodiment of the present invention, and as shown in fig. 7, receives an end-to-end delay request data message, parses delay request timestamp data, and sends a delay request response message.

In step 2004, a delayed request acknowledgement packet is transmitted to the slave clock through an eighth transmit interface.

As shown in fig. 8, after receiving an end-to-end delay request message, the master clock invokes a driver to read hardware time, converts the hardware time into a timestamp data format, that is, fourth timestamp data, and encapsulates the timestamp data into a delay request response packet for transmission.

In some embodiments, before the sending a synchronization packet to the slave clock through the fifth interface and acquiring the second timestamp data, the method further includes:

All Clock nodes in a PTP domain are organized together according to a certain hierarchy, and a reference time of the entire domain is an optimal Clock (GM), i.e., a highest-level Clock. Through the interaction of PTP protocol messages between clock nodes, the time of the optimal clock is finally synchronized into the whole PTP domain, and therefore, it is also called a clock source.

The optimal Clock can be statically designated through manual configuration, and can also be dynamically elected through an optimal Master Clock (BMC) protocol, wherein the process of dynamic election is as follows:

(1) And finally selecting one node as the optimal clock of the PTP domain through the information of optimal clock priority, time level, time precision and the like carried in the interactive Announce message among the clock nodes, and meanwhile, determining the master-slave relationship among the nodes and the master-slave ports on the nodes. Through the process, a loop-free and fully-connected spanning tree which takes the optimal clock as the root is established in the whole PTP domain.

(2) And then the master node sends an Announce message to the slave node periodically, and if the slave node does not receive the Announce message sent by the master node within a period of time, the slave node considers that the master node is invalid, and then the optimal clock is selected again.

Fig. 21 is a schematic design flow diagram of a synchronous declaration interface according to an embodiment of the present invention, and as shown in fig. 21, a master station data packet is sent to a local area network through the synchronous declaration interface to declare the existence of a master clock, and if there are multiple master clocks, the final master clock is determined according to the result by performing optimal master clock calculation on received data.

Optionally, the latest windows operating system already implements kernel support of PTP, and configures PTP attributes by editing a registry, where a main path of the registry is:

\HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Services\W32Time\TimeProviders\PtpClient

configuring a declaration sending interval through a variable announciterval;

1588 PTP function is Enabled by variable Enabled;

setting a delay request sending interval through a variable DelayPollInterval;

configuring a server IP address of 1588 PTP through a variable PtpMasters;

the function is initiated by using the command line approach:

C:\WINDOWS\system32>Stop-Service w32time

C:\WINDOWS\system32>Start-Service w32time

C:\WINDOWS\system32>

the invention realizes PTP protocol through vxworks of the main stream real-time operating system, linux of the main stream open source operating system and windows of the main stream commercial operating system, and meets the requirement of cross-platform and cross-system network clock synchronization.

The cross-platform clock synchronization device based on the PTP protocol provided in the present invention is described below, and the cross-platform clock synchronization device based on the PTP protocol described below and the cross-platform clock synchronization device based on the PTP protocol described above may be referred to correspondingly.

Fig. 22 is a schematic structural diagram of a cross-platform clock synchronization apparatus based on a PTP protocol according to an embodiment of the present invention, and referring to fig. 22, the cross-platform clock synchronization apparatus based on a PTP protocol according to an embodiment of the present invention includes:

a first receiving module 2210, configured to receive a synchronization packet sent by a master clock through a first interface, and obtain first timestamp data; the first timestamp data is the data of the network card at the receiving moment of the synchronous packet;

a second receiving module 2220, configured to receive, through a second interface, a following packet sent by the master clock; the following packet comprises second time stamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

a first sending module 2230, configured to send a delay request packet to the master clock through a third interface, and obtain third timestamp data; the third timestamp data is data of the network card at the time of sending the delay request packet;

a third receiving module 2240, configured to receive, through a fourth interface, a delay request response packet sent by the master clock; the delayed request packet response comprises fourth time stamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

a synchronization module 2250 configured to perform clock synchronization with the master clock based on the first timestamp data, the second timestamp data, the third timestamp data, and the fourth timestamp data.

The cross-platform clock synchronization device based on the PTP protocol provided by the embodiment of the invention realizes the conversion of the protocol by presetting a plurality of interfaces, and can be suitable for vxworks systems and linux systems, thereby realizing cross-platform clock synchronization, facilitating debugging and expanding and changing flexibly.

Optionally, the synchronization module 2250 is specifically configured to:

Optionally, the method further comprises:

and the first acquisition module is used for acquiring the first timestamp data on the network card through the timestamp acquisition interface.

Optionally, the method further comprises:

and the second acquisition module is used for acquiring the first timestamp data in a time register by reading a network card timestamp interface.

Fig. 23 is a second schematic structural diagram of a cross-platform clock synchronization device based on a PTP protocol according to an embodiment of the present invention, and referring to fig. 23, the cross-platform clock synchronization device based on a PTP protocol according to an embodiment of the present invention includes:

a second sending module 2310, configured to send a synchronization packet to the slave clock through the fifth interface, to obtain second timestamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

a third sending module 2320, configured to send a follower packet to the slave clock through a sixth sending interface; the following packet contains the second timestamp data;

a fourth receiving module 2330, configured to receive the delay request packet sent by the slave clock through a seventh interface, and obtain fourth timestamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

a fourth sending module 2340, configured to send a delay request response packet to the slave clock through an eighth sending interface; the delayed request packet reply includes the fourth timestamp data therein;

The cross-platform clock synchronization device based on the PTP protocol provided by the embodiment of the invention realizes the conversion of the protocol by presetting a plurality of interfaces, and can be suitable for vxworks systems and linux systems, thereby realizing cross-platform clock synchronization, being convenient for debugging and being flexible in expansion and change.

Optionally, the method further comprises:

a fifth sending module, configured to send the master station data packet to the local area network through the synchronous declaration interface; the master station data message is used for determining the master clock.

Fig. 24 illustrates a physical structure diagram of an electronic device, and as shown in fig. 24, the electronic device may include: a processor (processor) 2410, a communication Interface (Communications Interface) 2420, a memory (memory) 2430, and a communication bus 2440, wherein processor 2410, communication Interface 2420, and memory 2430 communicate with each other via communication bus 2440. The processor 2410 may invoke the logic instructions in memory 2430 to perform a cross-platform clock synchronization method based on the PTP protocol, the method comprising: receiving a synchronous packet sent by a main clock through a first interface to obtain first timestamp data; the first timestamp data is the data of the network card at the receiving moment of the synchronous packet; receiving a follow-up packet sent by the master clock through a second interface; the following packet comprises second time stamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet; sending a delay request packet to the master clock through a third interface, and acquiring third timestamp data; the third timestamp data is data of the network card at the time of sending the delay request packet; receiving a delayed request response packet sent by the master clock through a fourth interface; the delayed request packet response comprises fourth time stamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet; clock synchronization with the master clock based on the first, second, third, and fourth timestamp data.

In addition, the logic instructions in the memory 2430 may be implemented in software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.

In another aspect, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer readable storage medium, and when the computer program is executed by a processor, the computer can execute the PTP protocol based cross-platform clock synchronization method provided by the above methods, and the method includes: receiving a synchronous packet sent by a main clock through a first interface to obtain first timestamp data; the first timestamp data is the data of the network card at the receiving moment of the synchronous packet; receiving a follow-up packet sent by the master clock through a second interface; the following packet comprises second time stamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet; sending a delay request packet to the master clock through a third interface, and acquiring third timestamp data; the third timestamp data is data of the network card at the time of sending the delay request packet; receiving a delayed request response packet sent by the master clock through a fourth interface; the delayed request packet response comprises fourth time stamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet; clock synchronization with the master clock based on the first, second, third, and fourth timestamp data.

In yet another aspect, the present invention also provides a non-transitory computer-readable storage medium having stored thereon a computer program, which when executed by a processor, implements a PTP protocol-based cross-platform clock synchronization method provided by the above methods, the method including: receiving a synchronous packet sent by a main clock through a first interface to obtain first timestamp data; the first timestamp data is the data of the network card at the receiving moment of the synchronous packet; receiving a follow-up packet sent by the master clock through a second interface; the following packet comprises second time stamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet; sending a delay request packet to the master clock through a third interface, and acquiring third timestamp data; the third timestamp data is data of the network card at the time of sending the delay request packet; receiving a delay request response packet sent by the master clock through a fourth interface; the delayed request packet response comprises fourth timestamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet; clock synchronization with the master clock based on the first, second, third, and fourth timestamp data.

The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. Based on the understanding, the above technical solutions substantially or otherwise contributing to the prior art may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the various embodiments or some parts of the embodiments.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A cross-platform clock synchronization method based on a PTP (precision time protocol) is applied to a slave clock, and comprises the following steps:

receiving a synchronous packet sent by a main clock through a first interface to obtain first timestamp data; the first timestamp data is data of the network card at the receiving moment of the synchronization packet;

clock synchronization with the master clock based on the first, second, third, and fourth timestamp data.

2. The PTP protocol based cross-platform clock synchronization method of claim 1, wherein the clock synchronizing with the master clock based on the first time stamp data, the second time stamp data, the third time stamp data, and the fourth time stamp data comprises:

3. The PTP protocol based cross-platform clock synchronization method of claim 1, wherein the obtaining first timestamp data comprises:

4. The PTP protocol based cross-platform clock synchronization method of claim 1, wherein the obtaining first timestamp data comprises:

5. A cross-platform clock synchronization method based on a PTP (precision time protocol) is applied to a master clock, and comprises the following steps:

6. The method according to claim 5, wherein before the sending the synchronization packet to the slave clock through the fifth interface and obtaining the second timestamp data, the method further comprises:

7. A cross-platform clock synchronization device based on a PTP (precision time protocol), comprising:

the first receiving module is used for receiving a synchronization packet sent by a main clock through a first interface and acquiring first timestamp data; the first timestamp data is the data of the network card at the receiving moment of the synchronous packet;

a third receiving module, configured to receive, through a fourth interface, a delayed request response packet sent by the master clock; the delayed request packet response comprises fourth time stamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

8. A cross-platform clock synchronization device based on a PTP (precision time protocol) is characterized by comprising:

the second sending module is used for sending the synchronous packet to the slave clock through a fifth interface to acquire second timestamp data; the second timestamp data is data of the network card at the sending time of the synchronization packet;

the third sending module is used for sending a follow-up packet to the slave clock through a sixth sending interface; the following packet contains the second timestamp data;

a fourth receiving module, configured to receive the delay request packet sent by the slave clock through a seventh interface, and obtain fourth timestamp data; the fourth timestamp data is data of the network card at the receiving moment of the delay request packet;

9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the program implements the PTP protocol based cross-platform clock synchronization method of any one of claims 1 to 6.

10. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the PTP protocol based cross-platform clock synchronization method according to any one of claims 1 to 6.