CN101447861A - IEEE 1588 time synchronization system and implementation method thereof - Google Patents

IEEE 1588 time synchronization system and implementation method thereof Download PDF

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CN101447861A
CN101447861A CN 200810187676 CN200810187676A CN101447861A CN 101447861 A CN101447861 A CN 101447861A CN 200810187676 CN200810187676 CN 200810187676 CN 200810187676 A CN200810187676 A CN 200810187676A CN 101447861 A CN101447861 A CN 101447861A
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time
module
message
packet
stamp
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CN101447861B (en )
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刘立华
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中兴通讯股份有限公司
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0685Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697Synchronisation in a packet node

Abstract

The invention discloses an IEEE 1588 time synchronization system. By adding a time-stamp processing module, a time-stamp message transceiving sub module, a time-stamp message resolving sub module, a time-stamp message generating sub module, a local time recording register, and an RTC correction/time read-write module in the module are used for combining peripheral components such as a switch module, a PHY and a real-time clock (RTC) module to form a hardware system. When in use, the high precision time synchronization requested by an IEEE 1588v2 protocol can be implemented by using the modes of one-to-one or one-to-many of master-slave synchronization. The invention also discloses a method for implementing the IEEE 1588 time synchronization, which can implement the function of the time synchronization system by processing the time information of master-slave devices in real time. The invention plays an active role in promoting Ethernet construction.

Description

IEEE 1588时间同步系统及其实现方法 IEEE 1588 time synchronization system and its implementation method

技术领域 FIELD

本发明涉及电子和电气工程师协会(IEEE) 1588协议的时间同步技术,尤其涉及一种多端口正EE 1588时间同步系统及其实现方法。 The present invention relates to time synchronization Institute of Electrical and Electronics Engineers (IEEE) 1588 protocol, particularly to a multi-port positive EE 1588 time synchronization system and its implementation method.

背景技术 Background technique

IEEE 1588的全称是网络化测量和控制系统的精密时钟同步协议,通常称为精密时间协议(PTP, Precision Time Protocol )。 It stands for IEEE 1588 precision clock network measurement and control systems synchronization protocol, commonly referred to as Precision Time Protocol (PTP, Precision Time Protocol). 一般使用IEEE 1588精密时间协议的目的是在以太网中保持不同结点之间的时间同步。 General purpose use IEEE 1588 Precision Time Protocol is to keep the time between the different nodes in the synchronous Ethernet. 在工厂自动化、测量以及通信中也需要大量应用要求非常精密的时间同步,这通常会超出以标准软件方式的解决方案所能提供的范围。 In factory automation, measurement and communication also requires a lot of applications require very precise time synchronization, which is often beyond the scope of standard software solutions to the way the offer.

正EE1588标准,规定了将分散在测量和控制系统内的分离节点上独立运行的时钟同步到一个高精度和准确度的协议。 N EE1588 standard specifies the node on separate clock dispersed within a measurement and control system operate independently synchronized to a precision and accuracy of the protocol. 而这些时钟是在一个通信网络中互相通信的,按这个基本格式,该协议要形成树形的管理,使系统内的这些时钟产生一个主、从同步关系。 These clocks are in a communications network with each other, according to the basic format, the tree management protocol to be formed, so that the clocks in the system to produce a master, the synchronization relationship. 这里,所述同步包括频率同步和时间同步两个概念。 Here, the synchronization includes frequency synchronization and time synchronization concepts. 所谓频率同步即时钟同步,是指信号之间的频率或相位上保持某种严格的特定关系,其相对应的有效瞬间以同一平均速率出现,以维持通信网络中所有的设备以相同的速率运行。 I.e. the so-called frequency synchronization clock synchronization means to maintain a certain strict particular relationship between the frequency or phase signal, which corresponds to an effective moment occurs at the same average rate as to maintain the communication network all devices operating at the same rate . 而时间同步中所述的"时间,,有两种含义:时刻和时间间隔。前者是指连续流逝的时间的某一瞬间,后者是指两个瞬间时刻之间的间隙。时间同步的操作就是按照接收到的时间来调控设备内部的时钟和时刻。时间同步的调控原理与频率同步对时钟的调控原理相似,它既调控时钟的频率又调控时钟的相位,同时将时钟的相位以数值表示,即时刻。与频率同步不同的是,时间同步接受非连续的时间信息、非连续调控设备时钟,而设备时钟锁相环的调节控制是周期性的。时间同步有两个主要的功能:授时和守时。用通俗的语言描述,授时就是"对表"。通过不定期的对表动作,将本地时刻与标准时 And the time synchronization of the "time ,, has two meanings: the time interval and the former refers to a continuous instant time elapsed, which means that the gap between the two time synchronized operation time instant. It is in accordance with the received time to regulate the internal device clock and timing. time synchronization frequency regulation principle and the principle of regulation of the clock synchronization is similar to the frequency of the clock of both regulation and the regulation of the phase of the clock, while the phase of the clock is represented by the value , i.e. the time synchronization and frequency is different, the time synchronization time information to accept a non-continuous, non-continuous regulation device clock, clock phase-locked loop to adjust the control device is periodic time synchronization has two main functions: timing and punctuality. in plain language description, time service is "on the table." when the table from time to time by the action, local standard time

刻相位同步;守时就是前面提到的频率同步,保证在对表的间隙里,本地时刻 Engraved phase synchronization; is the aforementioned frequency synchronization punctuality, to ensure that the gap in the table, the local time

与标准时刻偏差不要太大。 Not too much deviation from the standard time. 时间同步的目的就是要将时间基准准确地传递到各控制点,传递并不困难,而难在要求所能达到的传递时间的精度。 To the purpose of time synchronization is transmitted accurately to the reference time of control points, transmission is not difficult, and required accuracy can be achieved in the difficult delivery time.

当前,通信网络和业务的IP化、分组化是大势所趋,但业务网尤其是移动业务对同步的要求仍必不可少,分组化后的传送网络仍需要具备完善的时钟同步能力来满足相关业务的同步需求。 Currently, communication networks and IP-based services, the packet is the trend, but especially the business network synchronization requirements for mobile services is still essential, after the transport network packetization still need to have the perfect clock synchronization capabilities to meet the related business synchronization requirements. 在无线通信的一些应用场景下,业务已IP In some application scenarios for wireless communication, business has IP

化,不再需要时分复用(TDM)接口,但是仍然需要时钟,此时需要一种时序分组(ToP, Timing over Packet)技术来实现。 Of no longer necessary time division multiplexing (TDM) interface, but still require a clock, then a need for a timing packet (ToP, Timing over Packet) technology. 所述ToP技术,是将定时信息根据一定的封装格式放入分组包中进行传送,在接收端从包中恢复时钟,通过算法和封装格式尽量规避传送过程中带来的损伤。 The ToP technique, the timing information is transmitted in packets into packets according to a certain packaging format, from the clock recovery packet at the receiving end, try to avoid damage during transport caused by the algorithm and the encapsulation format. 正EE 1588标准即是比较通用的ToP技术之一,能够较好地满足时间和相位同步的要求。 N EE 1588 standard that is one of the more common techniques of ToP, can satisfy the requirements of time and phase synchronization. 该标准经过改进可以达到非常高的精度,这在即将发布的正EE 1588 v2版本中会有相应介绍,从目前的发展来看,基于分组传送网采用IEEE 1588 v2技术进行时间传送是今后组建时间同步网的解决方案发展方向。 The improved standard can achieve very high accuracy, which will be introduced in the corresponding 1588 v2 EE version is about to release, from the current perspective of the development, packet-based transport network using IEEE 1588 v2 technology transfer time is set up next time synchronization network solutions development.

正EE 1588主从时钟同步原理如下:主钟定期发送Sync报文,随后发送Followup报文通告上个报文的实际发送时间Tl, /人钟记录Sync报文的到达时间T2;从钟在T3时刻发送Delay—Req报文,主钟记录报文到达时间T4,并将其通过响应报文Delay一Resp发送给从钟。 N EE 1588 master slave clock synchronization works as follows: the master clock periodically sends a Sync message, then sends the Followup packets advertisement actual transmission time of a packet Tl, / Zhong recording the arrival time of Sync packets T2; slave clock at T3 Delay-Req transmission time packets, packets the master clock records the arrival time T4, and passed through a Delay Resp response packet transmitted from the bell. 根据T1、 T2、 T3和T4,可以计算得到两个钟之间链路的时延和两个钟的时间偏差,据此调整从钟的时间输出,从而实现主钟和乂人钟的时间同步。 T1, T2, T3 and T4, the delay can be calculated and the time offset between the two clocks of two links according to the clock, the output from the time clock adjusted accordingly, thereby achieving the main clock and the time clock synchronization human qe . IEEE 1588v2可以同时实现频率同步和时间同步,其中时间同步能够达到亚微秒级精度,协议标准化较好,可以支持不同厂家对接,由于是通过在报文中加入时间标签来传递时间信息的,要求中间链路双向时延必须保持一致,时延不一致会引起相位测量偏差,从而对时间精度造成一定的影响,另外,时间精度还会受丢包等因素的影响。 IEEE 1588v2 possible to realize the frequency synchronization and time synchronization, time synchronization can be achieved in which the sub-microsecond accuracy, preferably standardized protocol, may support different manufacturers docking, as is to transmit the time information added by the time stamp in the packet, required intermediate link must be consistent way delay, the delay will cause inconsistent phase measurement error, resulting in some effect on the time precision, Further, the accuracy of the time of packet loss will be affected by factors like. 而且使用软件实现IEEE 1588协议栈的设置,还会因为软件处理流程和操作系统的多任务导致协议栈处理延时的4+动,因此,如果采用软件方式来实现正EE 1588v2协议将很难达到预期的传输高精度时间同步的要求。 And the use of software to set IEEE 1588 protocol stack, but also because the software processes and multitasking operating system, leading to 4+ dynamic protocol stack processing delay, and thus, if the software is the way to achieve positive EE 1588v2 protocol will be difficult to achieve the expected transmission time synchronization with high accuracy requirements. 发明内容 SUMMARY

有鉴于此,本发明的主要目的在于提供一种硬件多端口IEEE 1588时间同步系统及其实现方法,以满足IEEE 1588v2所要求的同步精度。 In view of this, the main object of the present invention is to provide a hardware multi-port IEEE 1588 time synchronization system and its implementation, to meet the IEEE 1588v2 synchronization accuracy required. 为达到上述目的,本发明的技术方案是这样实现的: To achieve the above object, the technical solution of the present invention is implemented as follows:

一种IEEE1588时间同步系统,包括交换机(Switch)模块、物理芯片(PHY) 模块、CPU管理模块以及实时时钟(RTC)模块;该系统还包括时间戳处理模块;其中: One kind IEEE1588 time synchronization system, comprising a switch (Switch) module, a physical chip (PHY) module, CPU management module and a real time clock (RTC) module; the system further comprising a time stamp processing module; wherein:

Switch模块,用于将来自多个PHY模块端口的正EE1588时间戳报文过滤后,送到时间戳处理模块; N EE1588 Switch module, for modules from the plurality of PHY ports After the time stamp packet filtering, to stamp processing module;

PHY模块,用于识别所述IEEE1588报文,并向向所述时间戳处理模块提供时间戳报文接收指示信号及时间戳报文发送指示信号; PHY module for identifying the IEEE1588 message, and to provide a signal indicative of the time stamp and the packet receiving time stamp message transmission instruction signal to the time stamp processing module;

CPU管理模块,用于管理所述时间同步系统; CPU management module for managing the time synchronization system;

RTC模块,用于提供本地时钟,根据接收到同步时钟来动态校准RTC;以 RTC module for providing a local clock to dynamically calibrate the received synchronizing clock RTC; to

and

时间戳处理模块,用于实现对IEEE 1588时间戳报文的解析,获得同步时间,以校正RTC本地实时时钟;还用于产生IEEE 1588报文、并向其他设备发送。 Stamp processing module, for implementing IEEE 1588 timestamps parse packets, time synchronization is obtained, to correct the local real time clock RTC; further for generating IEEE 1588 packet, and transmits the other device.

所述Switch模块具有多个端口,每个端口对应一个所述PHY模块。 The Switch module having a plurality of ports, each port corresponding to one of the PHY module. 所述时间戳处理模块中进一步包括时间戳报文收发子模块、时间戳报文解 The stamp processing module further includes a time stamp packet reception and transmission sub-module, a time stamp packet Solutions

析子模块、时间戳报文生成子模块、本地时间记录寄存器以及RTC校正/时间 Analysis sub-module, stamp message generation sub-module, and the local time capture register RTC calibration / time

读写模块;其中: Reader module; wherein:

时间戳报文收发子模块,用于接收或发送时间戳报文,并记录时间戳报文接收或发送的准确时间; Stamp message transceiver sub-module, for receiving or sending time stamp message, and record the exact time stamp packets sent or received packets;

时间戳报文解析子模块,用于根据时间戳报文内容及本地时间记录寄存器的记录判断时间戳类型;时间戳报文生成子模块,用于生成时间戳报文,并在所述时间戳报文中填 Parsing submodule stamp message, the register for recording a recording content according to the time stamp message, and determining the local time stamp format; stamp message generation sub-module, for generating a time stamp message, and the time stamp packet filled

入Sync、 FllowUp 、 Delay Request或Delay Response才艮文类另ll才示识; The Sync, FllowUp, Delay Request Delay Response or other generic ll Burgundy was shown only knowledge;

本地时间记录寄存器,用于记录发送/接收时间戳报文的时间;还用于同时 Local time recording register for recording transmission / reception time stamp packets; further for simultaneously

接收并处理多对时间戳报文接收指示信号和时间戳报文发送指示信号,并在 Receiving and processing the plurality of received time stamp packet signal and a stamp message indicating transmission instruction signal, and

RTC校正/时间读写子模块所提供的正确时间的作用下,向时间戳报文生成子模 RTC calibration / write action time the correct time provided by the sub-module, generating a time stamp message to the submodule

块和时间戳报文解析子模块提供所需的时间信息; Parsing block and stamp message sub-module provides time information required;

RTC校正/时间读写模块,用于校准本地RTC或读取、修改本地时间。 RTC calibration / time read-write module for calibrating the local RTC or read, modify local time. 所述时间戳处理模块中进一步包括CPU接口子模块,用于通过CPU管理 The stamp processing module further comprises a sub-CPU interface module for management by CPU

模块对所述时间戳处理模块进行读写操作。 The stamp processing module for read and write operations module.

一种采用4又利要求1所述IEEE1588时间同步系统实现时间同步的方法, And 4 using one kind of the claims 1 IEEE1588 time synchronization system implemented method for time synchronization,

将该时间同步系统分别设置在主设备和从设备中,该方法包括: The time synchronization system are provided in the master device and the slave device, the method comprising:

A、主设备通过自身内置的时间戳处理模块顺次向从设备发送Sync报文和 A, the master device through its own built-in stamp processing module sequentially sends the Sync message from the device and

FollowUp报文,所述从设备接收该Sync报文并记录接收时间为Ts2、接收该 FollowUp packet, from said receiving apparatus which receives the Sync message and the time Ts2 is recorded, the receiving

FollowUp报文并记录主设备发送Sync报文时间Tm2; FollowUp packets and recording the master sends Sync message time Tm2;

B 、所述从设备向所述主设备发送DelayRequest报文,记录发送时间为Ts3; B, the packet transmission DelayRequest, to record the transmission time Ts3 device from the master device;

所述主设备接收并解析该DelayRequest净艮文,并向所述从i殳备回复 The master device receives and parses the text DelayRequest net Burgundy, and prepare the reply from i Shu

DelayResponse才艮文,所述从i殳备记录主设备才妻收DelayRequest净艮文时间为 Gen DelayResponse was described, the recording apparatus Shu master device i wife was received packet time DelayRequest net Gen

Tm3;然后依据相应/>式计算出线路时延值Delay; TM3; delay line is then calculated based on the corresponding value Delay /> formula;

C、 所述从设备继续接收所述主设备顺次发来的Sync报文和FollowUp报文,所述从设备接收该Sync报文并记录接收时间为Ts4、接收该FollowUp报文并记录主设备发送Sync报文时间为Tm4;利用时延值Delay并按照预设的时间偏移量计算公式算出从设备与主设备之间的时间偏移量Offset,然后利用所述Offset值对从设备的本地时间进行校正。 C, the device continues to receive the master device sequentially from the packets sent by the Sync and FollowUp packet, the slave device receives the Sync message and records the time of reception Ts4, and receives the packet FollowUp master recording apparatus Sync message transmission Tm4 of time; and using preset delay value delay time offset is calculated from the calculated time offset offset between the device and the master device, and then using the offset value from the local device time to correct it.

所述步骤C之后进一步包括: After the step C further comprising:

D、 所述从设备继续接收所述主设备顺次发来的Sync报文和FollowUp报文,所述从设备接收该Sync报文并记录接收时间为Ts5、接收该FollowUp报文并记录主设备发送Sync报文时间为Tm5,然后利用公式:Offset=Ts5-Tm5- Delay; D, the device continues to receive the master device sequentially from the packets sent by the Sync and FollowUp packet, from said receiving apparatus which receives the Sync message and the recording time Ts5, and receives the packet FollowUp master recording apparatus Sync message transmission time Tm5, and then using the formula: Offset = Ts5-Tm5- Delay;

验证该Offset的值是否为零,若OffsetO,则结束主设备、从设备的时间同步校正过程;否则,返回执行步骤A。 The verification value Offset is zero, if OffsetO, the end of the main apparatus, the time from the synchronization correction process of the device; otherwise, return to step A.

其中,步骤A所述主设备的时间戳处理模块顺次向从设备发送Sync报文和FollowUp才艮文的过程为: Wherein the step of the master device A stamp processing module to process sequentially transmitted from the device and Sync message packets are FollowUp only Gen:

所述主设备的时间戳报文生成子模块产生携带有Sync报文的IEEE1588报文,通过时间戳报文收发子模块向Switch模块转发,所述Switch模块将Sync 报文通过交换作用转发给PHY模块,并由所述PHY模块向从设备发送所述含有Sync报文的IEEE1588报文;同时,所述IEEE1588报文通过PHY模块时向所述主设备的本地时间记录寄存器发送时间戳报文发送指示信号,由所述主设备的本地时间记录寄存器记录Sync报文的发送时间,所述时间戳报文生成子模块读取所述本地时间记录寄存器和RTC校正/时间读写子模块的时间信息,并在时间戳报文生成子模块中生成FollowUp报文,把Sync发送时间放到FollowUp中,通过时间戳报文收发子模块、Switch模块及PHY模块向从设备发送,并记下发送Follow Up报文的时间。 The stamp message generation sub-module generating the master device Sync packets carrying IEEE1588 packet forwarding module through the Switch sub stamp message transceiver module, the Sync Switch module forwards the packets to the PHY through the switching action module by module to the PHY device from transmitting the Sync packet contains IEEE1588 packets; Meanwhile, the IEEE1588 packet to the local time of recording the master device through the transmission PHY module registers the time stamp packets instruction signal, the local time of the master device registers the recording time of the recording Sync packet transmission, the packet time stamp generating submodule to read the local time and recording time information register RTC calibration / write time submodule and generating packets FollowUp stamp message generation sub-module, the transmission time of the Sync into FollowUp, the transmission to the slave device transmits Follow Up, and note the time stamp message by the transceiver sub-module, Switch modules and PHY modules packets.

步骤A所述从设备分别接收所述Sync报文和接收所述FollowUp报文的过程为: A step of receiving the Sync message and the receiving process of the packet FollowUp from the device, respectively:

所述从设备通过PHY模块接收到带有Sync报文或FollowUp报文类别的IEEE1588报文后,所述PHY模块向自身的本地时间记录寄存器发送时间戳报文接收指示信号,由所述本地时间记录寄存器记录相应报文的到达时间;并将所述Sync报文或FollowUp报文通过Switch模块转发给时间戳处理模块,通过时间戳报文收发子模块接收后转发给时间戳报文解析子模块判断出报文类别进行记录。 After the received packet with IEEE1588 or FollowUp Sync message packets through the PHY device from the category module, the PHY module records the time register to the own local stamp message transmission instruction signal received by said local time capture register recording the arrival time of the respective packet; Sync and the packet or packets are forwarded by Switch FollowUp module to the time stamp processing module forwards the packets to the time stamp parsing submodule stamp message by the transceiver after receiving submodule determine the categories recorded message.

步骤B所述计算线路时延值Delay的公式为: Delay=( ( Ts2-Tm2 ) + ( Ts3-Tm3 ) )/2; Step B The formula to calculate the delay value Delay line is: Delay = ((Ts2-Tm2) + (Ts3-Tm3)) / 2;

其中,Ts3为所述从设备向主设备发送DelayRequest报文的发送时间; Tm3为所述主设备接收到DelayResponse报文的时间。 Wherein, Ts3 transmitted to the slave device to the master device transmits the packet time DelayRequest; DelayResponse of Tm3 received packets to the master device.

10步骤C所述预设的时间偏移量Offset的计算公式为: 10 Step C the preset time offset Offset calculation formula is:

Offset=Ts4-Tm4- Delay; 其中,Ts4为从设备接收主设备随后发来Sync 4艮文的接收时间; Tm4为主设备发送Sync才艮文的本地时间; Delay为主设备、从设备之间的线路时延值。 Offset = Ts4-Tm4- Delay; wherein, the receiving apparatus Ts4 is then sent to the master device. 4 Gen Sync message received from a time; Tm4 of the master device before sending Sync packets Gen local time; Delay master device, the slave device between the line delay value.

所述从设备读取时间戳报文解析子模块中的时间偏移量Offset,通过RTC 校正/时间读写子模块调整PLL模块,将本地RTC的时间调整为与主设备时间同步网络一致。 The reading device from the time stamp message parsing submodule offset Offset, the correction by the RTC / PLL module adjusts the time to read and write the sub-module, the local time of RTC adjusted to match the network time synchronization master.

本发明所提供的IEEE 1588时间同步系统及其实现方法,具有以下优点: 本发明通过釆用硬件形式的时间戳处理模块,并使用该模块内的时间戳报文收发子模块、时间戳报文解析子模块、时间戳报文生成子模块、本地时间记录寄存器和RTC校正/时间读写模块对正EE1588报文中的Sync、FllowUp、Delay Request以及Delay Response报文进行实时处理,从而保证了采用本时间同步系统的设备之间的高精度时间同步。 The present invention provides the IEEE 1588 time synchronization system and its implementation method, has the following advantages: the present invention will preclude the use of hardware in the form of stamp processing module, and use the time stamp packets within the transceiver module sub-module, stamp message parsing submodule, stamp message generation sub-module, and the local time capture register RTC calibration / write module for time n EE1588 packets Sync, FllowUp, Delay Request Delay Response packets and real-time processing, thus ensuring the use of the present high-precision time between the time of the synchronization system.

另外,本发明系统中通过采用Switch模块,配合使用多个PHY模块,并保证并行处理的实时性,能够实现以多端口提供IEEE1588报文的方式对多个设备进行时间同步的校正,因而,对采用IEEE1588协议的高速以太网建设有积极的促进作用。 Further, the system of the present invention by using Switch module, with the use of a plurality of PHY modules, and to ensure real-time parallel processing, it is possible to provide a multi-port IEEE1588 packets manner plurality of synchronization time correction device, therefore, of High-speed Ethernet protocol using IEEE1588 construction has a positive role in promoting.

附图说明 BRIEF DESCRIPTION

图1为本发明实施例中IEEE 1588时间同步系统的结构示意图; 1 a schematic structural diagram IEEE 1588 time synchronization system according to the present invention;

图2为现有IEEE 1588协议传输时延的测量和完全同步的获得过程示意图; FIG 2 is a measure of propagation delay of the existing IEEE 1588 protocol and complete the process of obtaining synchronization schematic;

图3为本发明实施例IEEE 1588时间同步方法的实现过程示意图。 Figure 3 a schematic diagram of the implementation process of the IEEE 1588 time synchronization method embodiment of the present invention.

具体实施方式 detailed description

下面结合附图及本发明的实施例对本发明的方法作进一步详细的说明。 The method of the present invention will be further described in detail accompanying drawings and embodiments below in connection with the present invention. 图1为本发明实施例中IEEE 1588时间同步系统的结构示意图,如图1所示,该时间同步系统包括时间戳处理模块10,交换机(Swtich)模块11,中央处理器(CPU)管理模块12,物理层芯片(PHY)模块13以及实时时钟(RTC ) 模块14;其中,所述时间戳处理模块10中还包括CPU接口子模块100,时间戳报文收发子模块101,时间戳报文解析子模块102,时间戳报文生成子模块103,本地时间记录寄存器104以及RTC校正/时间读写模块105。 FIG 1 is a schematic structure of the IEEE 1588 time synchronization system according to the present invention, shown in Figure 1, the time synchronization system includes a time stamp processing module 10, the switch (Swtich) module 11, a central processing unit (CPU) 12 Management Module , the physical layer chips (PHY) module 13 and a real time clock (RTC) module 14; wherein said time stamp processing module 10 further includes 100, a time stamp packet reception and transmission submodule 101 CPU interface sub-module, a time stamp message parsing sub-module 102, a time stamp message generation sub-module 103, the local time capture register 104 and RTC calibration / write module 105 time.

时间戳处理模块IO,用于实现对IEEE 1588时间戳才艮文的解析,得到同步时间,以校正RTC本地实时时钟;还用于发送IEEE 1588才艮文提供给其他设备。 The IO stamp processing module, for enabling only IEEE 1588 timestamp Gen text analysis to obtain time synchronization, in order to correct local real time clock RTC; further configured to send only IEEE 1588 packets to other devices Gen. 其中: among them:

CPU接口子模块100,用于通过CPU管理模块12对所述时间戳处理模块IO进行读写操作。 CPU interface sub-module 100, for read and write operations by the CPU of the management module stamp processing module IO 12 pairs.

时间戳报文收发子模块101,用于接收或发送时间戳报文。 Stamp message transceiver sub-module 101, for sending or receiving time stamp message.

时间戳报文解析子模块102,用于根据时间戳报文内容及本地时间记录寄存器的记录判断时间戳类型;这里,所述时间戳有Delay Response报文、其他用于完成正常转发流程的报文等类型。 Stamp message parsing submodule 102, according to the recording time stamp message content and recording the local time stamp type judging register; herein, the time stamp has Delay Response message, the other for performing normal packet forwarding process Wen and other types.

时间戳报文生成子模块103,用于生成时间戳报文,并在所述时间戳报文中填入Sync、 FllowUp 、 Delay Request或Delay Response等报文类别标识; Stamp message generation sub-module 103 for generating a time stamp message, and fill Sync, FllowUp, Delay Request packet or the like Delay Response categories identified in the message timestamp;

本地时间记录寄存器104,用于记录PHY模块发送/接收时间戳报文的时间;所述本地时间记录寄存器104可以同时接收并处理多对时间戳报文接收指示信号和时间戳l艮文发送指示信号。 Local time capture register 104, the PHY module for recording transmission / reception time stamp packets; recording the local time register 104 may receive and process the received plurality of packets stamp and time stamp indication signal indicative of simultaneously sending Gen l signal. 并能够在RTC校正/时间读写子模块105 所提供的正确时间的作用下,向时间戳报文生成子模块103和时间戳报文解析子模块102提供所需的时间信息。 And can be corrected / time function correctly read time sub-module 105 provided in the RTC, the information required to provide the time stamp message generation sub-module 103 and the time stamp message parsing submodule 102.

RTC校正/时间读写模块105,用于校准本地RTC或读取、修改本地时间。 RTC calibration / time read-write module 105 for calibrating the local RTC or read, modify local time.

Swtich模块ll,用于将多个端口的时间戳报文过滤后,送到时间戳处理模块10。 Swtich module ll, a plurality of ports for the time stamp packet filtering, to stamp processing module 10.

CPU管理模块12,用于管理所述时间同步系统。 CPU 12 management module for managing the time synchronization system.

PHY模块13,用于识别正EE1588时间戳报文,提供给时间戳处理模块10。 PHY module 13, for identifying n EE1588 stamp message, provided to the time stamp processing module 10. 所述PHY模块13向所述时间戳处理模块IO提供时间戳报文接收指示信号及时间戳报文发送指示信号,具体为:PHY模块向所述时间戳处理模块IO的本地时间记录寄存器104发送时间戳报文接收指示信号或时间戳报文发送指示信号。 The PHY module 13 provides a signal indicative of a time stamp packet receiving and stamp message transmission instruction signal to the time stamp processing module IO, specifically: PHY module records the time stamp to the local time of the processing module 104 transmits the IO register stamp message signal or a time stamp indicating the received message transmission instruction signal. 这里,所述PHY模块提供的发送和接收指示信号是为了让本地时间记录器记下时间戳报文通过PHY模块的准确时间,主设备PHY模块和从设备PHY模块之间的延时才是我们要计算的延时,因为这个延时是一个固定延时,如果经过Switch模块在计算延时,那就不准确了。 Here, transmission and reception of signals indicative of the PHY module is designed to allow the local time registration means exact time stamp message by the PHY module, the master module and a delay from the PHY device between the PHY module is our to calculate the delay, because the delay is a fixed time delay, if the delay through the Switch module in the calculation, it is not accurate. 所述PHY模块13可以为单个或多个,即可以根据实际需要配置N个,N>1。 The PHY module 13 may be configured as a single i.e., according to actual needs or more of N, N> 1.

RTC模块14,用于为时间同步系统提供同步的时间。 RTC module 14 for providing time synchronization system for time synchronization.

本发明实施例的时间同步系统,首先通过PHY模块13得到IEEE 1588时间报文,提供时间戳处理模块报文到达的本地时间;然后将IEEE 1588时间报文通过Swtich模块11转发到时间戳处理模块,进行报文识别和时间的计算, 从而得到高精度的同步时间。 Time synchronization system according to an embodiment of the present invention, the PHY module 13 is firstly obtained by the IEEE 1588 time message, provides the local time stamp processing module packets arrive; then IEEE 1588 time Swtich module forwards packets to the time stamp processing module 11 , a message identifying packet and calculation time to obtain time synchronization with high accuracy.

图2为现有正EE 1588协议传输时延的测量和完全同步的获得过程示意图, 如图2所示,主钟(Master)和从钟(Slave )之间存在线路时延(Line Delay ), Tm为Master的本地时间,Ts为Slave的本地时间。 FIG 2 is a conventional measure of propagation delay of a positive EE 1588 protocol and synchronization process to obtain complete schematic diagram As shown, there delay line (Line Delay) between the master clock (Master) and slave clock (the Slave) 2, local time Master of Tm, Ts local time the Slave. 作Ii殳起始状态时Master的当前时间为1070s, Slave的当前时间为1009s。 Master Ii Shu as when the current time is the initial state of 1070s, the current time is Slave 1009s. 4姿照正EE 1588协议,Master 定时发送,如每隔2秒(可依据实际情况确定时间间隔)发送一次同步(Sync) 报文,随后发送跟随(Follow up )报文通告上个报文的实际发送时间Tmn,由Slave记录Sync l艮文的到达时间Tsn。 4 Pose as positive EE 1588 protocol, Master timing of transmission, such as every 2 seconds (may determine the time interval based on the actual situation) transmitting a synchronization (Sync) packet, and then transmits follow (Follow up) message announcement last packet actual transmission time Tmn, the arrival time Tsn Sync l Gen recording paper by the Slave. 如图2所示,Slave在Ts3时刻发送延时请求(Delay Request)报文,Master记录报文到达的时间Tm3,并将其通过延时响应(Delay Response )报文发送给Slave,计算出Master和Slave之间的线路延时Delay= ((Ts2-Tm2)+(Ts3-Tm3)) /2=0+(1082-1080)/2=ls; Slave根据后续的Follow up报文计算出Master和Slave之间的时间偏移量Offset=Ts4-Tm4-Delay=1083-1083-l=-l,然后根据时间偏移量Offset计算出应该调整的时间差值Adjust Time=Ts-Offset=Ts-(-l)=ls,据此,在下一个时间间隔Follow up报文到达的时刻对Slave进行校准,4吏时间偏移量为零,即Offset=Ts5-Tm5-1 =0,完成Master与Slave的时间同步调整过程。 2, Slave transmission delay request (Delay Request) messages at the time Ts3, Master record of Tm3 arrival time message, and sends it to a delay in response by a Slave (Delay Response) message, Master calculated delay line delay between Slave = ((Ts2-Tm2) + (Ts3-Tm3)) / 2 = 0 + (1082-1080) / 2 = ls; Slave Master calculated according to the subsequent messages and follow up time offset between the Slave offset = Ts4-Tm4-Delay = 1083-1083-l = -l, then calculate the time difference to be adjusted adjust time = Ts-offset = Ts- the time offset offset ( -l) = ls, accordingly, the next time interval Follow up time packet reaches the Slave calibrate 4 official time offset is zero, i.e., offset = Ts5-Tm5-1 = 0, the completion of the Master and Slave time synchronization adjustment process.

图3为本发明实施例中IEEE 1588时间同步方法的实现过程示意图,如图3所示,假设对端设备为主设备,从设备为从设备。 Examples implementation of IEEE 1588 time synchronization method schematic of FIG. 3 Embodiment 3 of the present invention, it is assumed the remote device based device from the slave device. 主设备和从设备中各设置有一时间戳处理模块10。 From the master device and each device is provided with a stamp processing module 10. 下面以在主设备和从设备之间互发IEEE1588报文的对从设备时间同步调整过程为例进行说明,该方法包括: Below the master and slave synchronization time adjustment process will be described as an example IEEE1588 packets sent from a cross between the devices, the method comprising:

步骤301:主设备通过以太网向从设备发送IEEE1588报文。 Step 301: the master device to transmit the Ethernet packets from the IEEE1588 device. 这里,主设备中的时间戳处理模块10与从设备中的时间戳处理模块10的结构、作用相同,只不过本实施例中假设以主设备的时间为标准。 Here, the main device stamp processing module 10 and the structure of the device from the stamp processing module 10, the same function, but this embodiment is assumed that the time the master device of the present embodiment as the standard. 所述主设备通过时间戳报文发送子模块101向Switchll模块发送IEEE 1588报文,再通过Switchll的交换后转发给自身的PHY模块13,然后通过以太网发送到从设备的PHY才莫块13。 The host device sends the time stamp packet by sending sub-module 101 to the IEEE 1588 packet Switchll module, and then forwarded to the PHY module 13 by itself after the exchange Switchll then sent via block 13 from Mo only Ethernet PHY device .

以上所述IEEE1588报文由主设备的时间戳报文生成子模块103结合主设备的RTC校正/时间读写子模块105的时间信息后生成,并且由主设备的时间戳报文生成子模块103传送给时间戳报文收发子模块101,再发送给Switch模块11。 The IEEE1588 packet above the stamp message generation sub-module 103 in conjunction with the master device the master device RTC calibration / time information 105 of the write time after generation sub-module, and the time stamp packets generated by the master device submodule 103 transmitted to the time stamp packet reception and transmission sub-module 101, and then sent to Switch module 11.

步骤302:从设备通过PHY模块13接收所述IEEE1588报文,并向Switch 模块11和时间戳处理模块10的本地时间记录寄存器104转发,然后分别执行步骤303和步骤304。 Step 302: receiving from a device through the IEEE1588 PHY packet module 13, and Switch module 11 and a local time stamp processing module 10 forwards the register 104 is recorded, respectively, and then perform steps 303 and step 304.

步骤303:所述Switch模块11接收所述正EE1588报文后通过交换转发给时间戳处理模块10的时间戳报文收发子模块101,然后执行步骤305。 Step 303: Switch the module, after receiving the positive EE1588 11 by exchanging packets forwarded to the time stamp packet reception and transmission sub-module 101 stamp processing module 10, and then step 305 is performed.

步骤304:所述本地时间记录寄存器104收到所述正EE1588报文后记录所述报文到达时间,然后执行步骤306。 Step 304: after recording the local time register 104 receives the packet records the positive EE1588 packet arrival time, and then step 306 is performed.

步骤305:由时间戳报文解析子模块102解析所述IEEE1588报文,判断是否为Sync报文,如果是,则执行步骤306;否则,执行步骤307。 Step 305: the time stamp message parsing module 102 parses the sub IEEE1588 packet, determines whether the Sync message, if yes, execute step 306; otherwise, step 307 is performed.

步骤306:通过本地时间记录寄存器104记录Sync报文及IEEE1588报文所到达的时间,记为Ts(n),其中,n > 1 。 Step 306: the register 104 and the recording time of the Sync message IEEE1588 packet arrived, denoted by Ts (n) by recording the local time, where, n> 1.

这里,所有时间戳报文在到达PHY模块或经过PHY模块发送时都要在本 Here, all of the arrival time stamp message sent through the PHY PHY module or modules should be present in

14地时间记录器中记录到达或发送的时间;当所述报文经过时间戳解析子模块并根据对报文进行解析的需要用到某个时间时,再从所述本地时间记录寄存器中获取与所述报文对应的时间信息。 Time recorder 14 to record the time of arrival or transmitted; when the elapsed time stamp packet parsing submodule and the time required to use a packet parsing, reacquisition time record from the local register information corresponding to the packet time.

步骤307:进一步判断所述IEEE1588报文是否为Follow Up报文,如果是, 则执行步骤308;否则,执行步骤309。 Step 307: further determining whether the packet of the IEEE1588 Follow Up message, if yes, execute step 308; otherwise, step 309 is executed.

步骤308:通过解析报文得到主设备发送Sync报文的时间,Tm(n)。 Step 308: parsing packets obtained by the master device sending Sync packets, Tm (n).

步骤309:判断所述IEEE 1588报文是否为Response报文,如果是,则执行步骤310;否则,将该报文丢弃结束本次时间戳报文接收过程。 Step 309: determining whether or not the IEEE 1588 packet is a Response message, if yes, execute step 310; otherwise, the packet is discarded end of this time stamp packet receiving process.

步骤310:通过解析报文,得到主设备接收到Delay Request报文的时间, 记为Tm(n+1)。 Step 310: parsing by packets received by the master device to give Delay Request packets, referred to as Tm (n + 1).

以上为IEEE1588报文从主设备发送至从设备的基本过程,所述正EE1588 报文中可以填入不同的标识信息,以区别IEEE 1588的才艮文类别,例如,填入Sync4艮文、FollowUp才艮文、Delay Request !艮文或Delay Response 4艮文。 The above is the packet transmitted from the IEEE1588 device to the master device from the basic process, the positive EE1588 packet can fill in a different identification information to distinguish it Gen IEEE 1588 packet category, for example, fill packets Sync4 Burgundy, Followup Gen text only, Delay Request! Burgundy Burgundy Delay Response 4 text or text. 下面以IEEE1588报文交互完成一次同步时间校正的过程为例进行分别描述: IEEE1588 below to complete a packet exchange time synchronization correcting process are described with an example:

1 、主设备向从设备发送Sync报文及Follow Up报文的过程: 1, the master sends the Sync message packets and Follow Up slave process:

主设备的时间戳报文生成子模块103产生携带有Sync报文的IEEE1588报文,通过时间戳报文收发子模块101向Switch模块11转发,所述Switch模块11将Sync报文通过交换作用转发给PHY模块13 ,由所述PHY模块13向从设备发送含有Sync报文的正EE1588报文;同时,所述正EE1588报文通过PHY 模块13时需要向所述主设备的本地时间记录寄存器104发送时间戳报文发送指示信号,由所述主设备的本地时间记录寄存器104记录Sync报文的发送时间Tm2,时间戳报文生成子模块103读取所述本地时间记录寄存器104和RTC校正/时间读写子模块105的时间信息,并在时间戳报文生成子模块103中在IEEE1588报文中加入Follow Up报文类别,通过时间戳4良文收发子模块101 、 Switch模块11及通过PHY才莫块13向从设备发送。 Stamp message generation sub-module 103 generates the master device Sync packets carrying IEEE1588 packet forwarding module to Switch 11 via the transceiver stamp message sub-module 101, the Sync Switch module 11 forwards the packet through the switching action to the PHY module 13, the PHY module 13 from the positive to the slave device transmits packets containing EE1588 Sync message; recording at the same time, the positive EE1588 packets through the PHY module 13 needs the local time of the master device registers 104 transmitting the time stamp message transmission instruction signal, the recording time of the master device by a local register 104 records the transmission time of the Sync message Tm2, ​​stamp message generation sub-module 103 reads the local time capture register 104 and RTC calibration / time to read and write the time information of the sub-module 105, and time stamp message generation sub-module 103 is added Follow Up message category IEEE1588 packets by timestamps 4 Yoshibumi transceiver submodule 101, Switch module 11 and through the PHY before Mo from block 13 is transmitted to the device.

然后,由所述,人设备接收该Sync l艮文并记录4妻收时间为Ts2、接收该FollowUp报文并记录主设备发送Sync报文时间为Tm2,所述从设备通过PHY Then, receiving the message by the Sync L Gen, 4 wife who received the device and the recording time Ts2 is, the received message and recording FollowUp master sends Sync message time Tm2, ​​from the PHY device through

15模块13接收到带有Sync报文或FollowUp报文的报文后,所述PHY模块13 向自身的本地时间记录寄存器104发送时间戳报文接收指示信号,由所述本地时间记录寄存器104记录该报文的到达时间;并将所述Sync报文或FollowUp 报文通过Switch模块11转发给时间戳处理模块10,通过时间戳报文收发子模块101接收后转发给时间戳报文解析子模块102判断出报文类别进行记录。 15 after the module 13 receives the packet with the Sync message packets or FollowUp, the PHY module 13 to the own local time capture register 104 receives the transmission time stamp message indication signal, the register 104 is recorded by recording the local time packet arrival time; Sync message and the packet is forwarded to or FollowUp stamp processing module 11. Switch module 10, the receiver 101 is forwarded to the time stamp message transceiver module sub-stamp message parsing submodule 102 determines that the message categories recorded. 2、从设备向主设备发送Delay Request报文的过程: 2, the transmission process Delay Request packet to the master device from the device:

从设备向主设备发送携带有Delay Request报文的IEEE 1588报文时,本地的时间记录寄存器104记下所述Delay Request l艮文的发送时间Ts3 ,并通过时间戳报文收发子模块101发送给Switch模块11,经过交换处理后发送给从设备的PHY模块13将所述Delay Request报文向主设备发送。 Transmitting from the device carrying the Delay Request packet IEEE 1588 packet to the master device, the local time of the register 104 records the transmission time of a note Delay Request l Gen text Ts3, and time stamp message transmitted by the transceiver 101 submodule Switch to the module 11, 13 transmits to the Delay Request packet sent from the exchange processing after module PHY device to the host device.

3 、主设备向从设备回复Delay Response报文的过程: 3, the master device to respond to Delay Response message from process equipment:

主设备的PHY模块13接收到从设备的Delay R叫uest报文后,通过PHY 模块13向本地时间记录寄存器104发送时间戳l艮文指示信号,由所述本地时间记录寄存器104记录Delay R叫uest报文的到达时间Tm3 ,并指示时间戳报文生成子模块IO3在IEEEl588报文中加入Delay Response报文,再通过时间戳报文收发子模块101、 Switch模块11以及PHY模块13向从设备发送。 After the master device PHY module 13 receives packets from the called uest Delay R device, the recording module 13 through the PHY to the local time stamp register 104 l Gen transmitted signal indicated above, the time recorded by the local register 104 records called Delay R uest of Tm3 packet arrival time, and a time stamp indicating message generation sub-module IO3 added in IEEEl588 Delay Response message packet, and then by time stamp packet reception and transmission sub-module 101, Switch module 11 and PHY module 13 to the slave device send.

4、从设备接收主设备返回的Delay Response报文的过程: 4, the receiving apparatus returns from the master device Delay Response message procedure:

从设备接收到主设备返回的Delay Response报文后,依据公式: Delay=( ( Ts2-Tm2 ) + ( Ts3-Tm3 ) )/2 ( 1 ) After receiving from the device to the Delay Response message returned by the master device, according to the formula: Delay = ((Ts2-Tm2) + (Ts3-Tm3)) / 2 (1)

计算出主设备、从设备之间的线路时延,并将该时延值存储在从设备的时间戳报文解析子模块102中。 The master device is calculated, from the line delay between the devices and the delay value from the time stamp message is stored in the parsing submodule 102 device.

5 、从设备根据与主设备的时间偏移量调整本地时间的过程: 5, the amount of adjustment of the device from the procedure according to the local time offset from the time master device:

此时,从设备继续接收由主设备的时间戳报文生成子模块103发送来的Sync报文和Follow Up报文,通过从设备的时间戳报文解析子模块102的解析, 记录Sync净艮文到达的时间为Ts4、并记录主i殳备发送Sync净艮文的时间Tm4; 从设备的时间戳报文解析子模块102根据公式: In this case, the device continues to receive packets transmitted by the time stamp generation sub-module 103 to the host device and Follow Up Sync message packets, by analyzing the time stamp message parsing submodule device 102, the recording Sync net Gen time packet reaches to Ts4, and recording the master device sends Sync net i Shu Gen packets Tm4 of time; the time stamp message parsing submodule apparatus 102 according to the formula:

Offset=Ts4-Tm4-Delay ( 2 )主钟的时间偏移量,即时间差,所述从设备此时即可利用该时间差来校正本地时间,即所述从设备读取时间戳报文解析 Offset = offset time Ts4-Tm4-Delay (2) of the master clock, i.e. the time difference, the device is now corrected to the local time by using the time difference from that of the read time stamp from the message parsing apparatus

子模块102中的时间偏移量Offset,通过RTC冲交正/时间读写子模块105调整PLL模块,将本地RTC的时间调整为与主设备时间同步网络一致,从而得到与主设备的实时时钟保持一致的高精度同步时间。 Offset time offset sub-module 102, through the red cross RTC n / write time of adjusting the PLL module 105 sub-module, the local network RTC time synchronization adjustment is consistent with the master time to obtain real-time clock with the master device retention time consistent precision synchronization.

在从设备校正完本地时间后,还需要一个确认时间同步的过程,即: 从设备继续接收来自主设备的到时间戳报文生成子模块103发送来的Sync 报文和Follow Up报文,通过从设备的时间戳报文解析子模块102的解析,记录Sync 4艮文到达的时间为Ts5,并记录主设备发送Sync报文的时间Tm5;验证Offset^Ts5-Tm5-Delay的值是否为零,如果Offset=0,则主设备、从设备的时间同步得到4全证;如果经验证Offset* 0,则此次时间同步校正过程失败,需要重新执行本方法的时间同步校正过程。 After completion of correction of the local time from the device, but also the process requires a time synchronization acknowledgment, namely: from the device continues to receive from the master device to generate a time stamp message sent by the sub-module and Follow Up Sync message packets 103, by from the parsed time stamp packet parsing submodule device 102, the recording time. 4 Gen Sync message arrives for Ts5, and recording the master sends Sync packets Tm5; Ts5-Tm5-Delay Offset ^ verification value is zero If Offset = 0, then the master device 4 to obtain full synchronization time card from the device; if validated Offset * 0, then the time synchronization correction process fails, the process time required to re-execute the synchronization correction process.

以上所述,仅为本发明的较佳实施例而已,并非用于限定本发明的保护范围。 The above are only preferred embodiments of the present invention but are not intended to limit the scope of the present invention.

17 17

Claims (11)

  1. 1、一种IEEE1588时间同步系统,包括交换机(Switch)模块、物理芯片(PHY)模块、CPU管理模块以及实时时钟(RTC)模块;其特征在于,该系统还包括时间戳处理模块;其中:Switch模块,用于将来自多个PHY模块端口的IEEE1588时间戳报文过滤后,送到时间戳处理模块;PHY模块,用于识别所述IEEE1588报文,并向向所述时间戳处理模块提供时间戳报文接收指示信号及时间戳报文发送指示信号;CPU管理模块,用于管理所述时间同步系统;RTC模块,用于提供本地时钟,根据接收到同步时钟来动态校准RTC;以及时间戳处理模块,用于实现对IEEE1588时间戳报文的解析,获得同步时间,以校正RTC本地实时时钟;还用于产生IEEE1588报文、并向其他设备发送。 An IEEE1588 time synchronization system, comprising a switch (Switch) module, a physical chip (PHY) module, CPU module management and real-time clock (RTC) module; characterized in that the system further comprises a stamp processing module; wherein: Switch IEEE1588 module, a PHY module from the plurality of ports after the time stamp packet filtering, to stamp processing module; PHY module, for identifying the IEEE1588 packet, and providing to the time stamp processing module receiving a signal indicative of the message timestamp and the timestamp of the message transmission instruction signal; the CPU management module for managing the time synchronization system; RTC module, for providing a local clock, RTC dynamically calibrate the received synchronization clock; and a timestamp a processing module for implementing the IEEE1588 timestamps parse packets, time synchronization is obtained, to correct the local real time clock RTC; IEEE1588 also used to generate packets transmitted to other devices.
  2. 2、 根据权利要求1所述的时间同步系统,其特征在于,所述Switch模块具有多个端口,每个端口对应一个所述PHY才莫块。 2, according to the time synchronization system according to claim 1, wherein the Switch module having a plurality of ports, each port corresponding to a block of the PHY before mo.
  3. 3、 根据权利要求1所述的时间同步系统,其特征在于,所述时间戳处理模块中进一步包括时间戳报文收发子模块、时间戳报文解析子模块、时间戳报文生成子模块、本地时间记录寄存器以及RTC校正/时间读写模块;其中:时间戳报文收发子模块,用于接收或发送时间戳报文,并记录时间戳报文接收或发送的准确时间;时间戳报文解析子模块,用于根据时间戳报文内容及本地时间记录寄存器的记录判断时间戳类型;时间戳报文生成子模块,用于生成时间戳报文,并在所述时间戳报文中填入Sync、 FllowUp、 Delay Request或Delay Response报文类另'J标识;本地时间记录寄存器,用于记录发送/接收时间f^艮文的时间;还用于同时接收并处理多对时间戳报文接收指示信号和时间戳报文发送指示信号,并在RTC校正/时间读写子^t块所提供的正确时间的作用下,向时间戳报文 3, according to the time synchronization system according to claim 1, wherein said time stamp processing module further includes a time stamp packet reception and transmission sub-module, parsing submodule stamp message, the time stamp message generation sub-module, RTC register and the local time correction of the recording / time reader module; wherein: the time stamp packet reception and transmission sub-module, for receiving or sending time stamp message, and records the time stamp message is received or sent exact time; stamp message parsing submodule, for determining a time stamp recording the time stamp according to the type of the register and the local time the packet contents; stamp message generation sub-module, for generating a time stamp message, and to fill in the time stamp packet the Sync, FllowUp, Delay Request Delay Response message, or another type 'J identifier; local time recording register for recording transmission / reception time f ^ Gen time packets; further for receiving and processing multiple packets at the same time time stamp receiving an indication signal and the time stamp message transmission instruction signal and the read sub RTC calibration / ^ at time t of the block action of the correct time provided by the time stamp packet 生成子模块和时间戳报文解析子模块提供所需的时间信息;RTC校正/时间读写模块,用于校准本地RTC或读取、修改本地时间。 Generating a time stamp message sub-module and sub-module provides time information parsing required; RTC correction / time read-write module for calibrating the local RTC or read, modify local time.
  4. 4、 根据权利要求1或3所述的时间同步系统,其特征在于,所述时间戳处理模块中进一步包括CPU接口子模块,用于通过CPU管理模块对所述时间戳处理模块进行读写操作。 4. The time synchronization system according to claim 13, wherein said time stamp processing module further comprises a sub-CPU interface module for read and write operations of the time stamp processing module management module CPU .
  5. 5、 一种采用权利要求1所述IEEE1588时间同步系统实现时间同步的方法, 将该时间同步系统分别设置在主设备和从设备中,其特征在于,该方法包括:A、 主设备通过自身内置的时间戳处理模块顺次向从设备发送Sync报文和FollowUp报文,所述从设备接收该Sync报文并记录接收时间为Ts2、接收该FollowUp才艮文并记录主i殳备发送Sync净艮文时间Tm2;B、 所述从设备向所述主设备发送DelayRequest报文,记录发送时间为Ts3; 所述主设备接收并解析该DelayRequest报文,并向所述从设备回复DelayResponse才艮文,所述从设备记录主设备接收DelayR叫uest报文时间为Tm3;然后依据相应公式计算出线路时延值Delay;C、 所述从设备继续接收所述主设备顺次发来的Sync报文和FollowUp报文,所述从设备接收该Sync报文并记录接收时间为Ts4、接收该FollowUp报文并记录主设备发送Sync报文时间为Tm4;利用时延 5. A time synchronization using the system of claim 1 IEEE1588 method of claim achieve time synchronization, the time synchronization system are provided in the master and slave devices, wherein the method comprises: A, the master device through its own built- the stamp processing module sequentially transmitted to the slave device and FollowUp Sync message packets, the packet received from the Sync device receives and records the time Ts2 is, the received message and recording FollowUp only Gen Shu master device sends Sync net i Gen packet time Tm2; B, from the device to the host device sends DelayRequest packet transmission time is recorded Ts3; the master device receives and parses the DelayRequest packet, and the slave device was described Gen reply DelayResponse the call from the master device receives the packets uest DelayR recording apparatus of Tm3 time; then calculates the delay value delay line basis corresponding formula; C, the device continues to receive the master device sequentially from the packets sent by the Sync and FollowUp packet, the packet received from the Sync device receives and records the time Ts4, receives the packets and recording FollowUp master sends Sync message Tm4 of time; using delay 值Delay并按照预设的时间偏移量计算公式算出从设备与主设备之间的时间偏移量Offset,然后利用所述Offset值对从设备的本地时间进行校正。 And calculates the value of the Offset Delay from the time between the master device and the time offset according to a preset calculation formula, using the value of Offset is then corrects the local time from the device.
  6. 6、 才艮据权利要求5所述的实现时间同步的方法,其特征在于,所述步骤C 之后进一步包括:D、 所述从设备继续接收所述主设备顺次发来的Sync报文和FollowUp报文,所述从设备接收该Sync报文并记录接收时间为Ts5、接收该FollowUp报文并记录主设备发送Sync报文时间为Tm5,然后利用7>式:Offset=Ts5-Tm5- Delay;验证该Offset的值是否为零,若Offset=0,则结束主设备、从设备的时间同步校正过程;否则,返回执行步骤A。 6, implemented according to the time before Gen 5 of the synchronizing method as claimed in claim, wherein after said step C further comprising: D, the master device sequentially sent to the Sync message and continues to receive from the device FollowUp packet, from said receiving apparatus which receives the Sync message and the recording time Ts5, and receives the packet FollowUp recording master sends Sync message Tm5 time, and then using 7> formula: Offset = Ts5-Tm5- Delay ; verifying the Offset value is zero, if Offset = 0, then the end of the main apparatus, the time from the synchronization correction process of the device; otherwise, return to step A.
  7. 7、 根据权利要求5所述的实现时间同步的方法,其特征在于,步骤A所述主设备的时间戳处理模块顺次向从设备发送Sync报文和FollowUp报文的过程为:所述主设备的时间戳报文生成子模块产生携带有Sync报文的IEEE1588报文,通过时间戳报文收发子模块向Switch模块转发,所述Switch模块将Sync 报文通过交换作用转发给PHY模块,并由所述PHY模块向从设备发送所述含有Sync报文的IEEE1588报文;同时,所述IEEE1588报文通过PHY模块时向所述主设备的本地时间记录寄存器发送时间戳净艮文发送指示信号,由所述主设备的本地时间记录寄存器记录Sync报文的发送时间,所述时间戳报文生成子模块读取所述本地时间记录寄存器和RTC校正/时间读写子模块的时间信息,并在时间戳报文生成子模块中生成FollowUp报文,把Sync发送时间放到FollowUp中,通过时间戳报文收发子模块、Switch模块 7. The method of claim 5 times to achieve synchronization claim, wherein the step of stamp processing module A to the master device sequentially transmits a Sync message and process packets from FollowUp equipment: the main stamp message generation sub-module carrying device generates IEEE1588 packets Sync packet forwarding module through the Switch sub stamp message transceiver module, the Sync Switch module forwards the packets to the PHY module via the exchange interaction, and the PHY module from a transmitting apparatus to a Sync packet contains the IEEE1588 packets; Meanwhile, the IEEE1588 packet sending time stamp capture register net Gen instruction signal sending to the local time of the master device through the PHY module , by the local time of the master device registers the recording time of the recording Sync packet transmission, the packet time stamp generating submodule to read the local time and recording time information register RTC calibration / write time submodule, and FollowUp packets generated time stamp message generation sub-module, the transmission time of the Sync into FollowUp by the time stamp packet reception and transmission sub-module, Switch module PHY模块向从设备发送,并记下发送Follow Up报文的时间。 Follow Up PHY module sends packets to the transmitting device, and note.
  8. 8、 根据权利要求5所述的实现时间同步的方法,其特征在于,步骤A所所述从设备通过PHY模块接收到带有Sync报文或FollowUp报文类别的IEEE1588报文后,所述PHY模块向自身的本地时间记录寄存器发送时间戳报文接收指示信号,由所述本地时间记录寄存器记录相应报文的到达时间;并将所述Sync报文或FollowUp才艮文通过Switch模块转发给时间戳处理模块,通过时间戳报文收发子模块接收后转发给时间戳报文解析子模块判断出报文类别进行记录。 8. The method of claim 5 times to achieve synchronization claim, wherein, after the step A of the received packet with IEEE1588 or FollowUp Sync message packets through the PHY device from the category module, the PHY the module's own local time capture register transmitting instruction signal received time stamp message, the local time recorded by the recording register the arrival time of the respective packet; and the Sync message before or FollowUp Gen forwards the message to time by Switch module stamp processing module forwards the packets to the time stamp parsing submodule determines that the message categories recorded by time stamp message transceiver after receiving the sub-module.
  9. 9、 根据权利要求5所述的实现时间同步的方法,其特征在于,步骤B所述计算线路时延值Delay的公式为:<formula>formula see original document page 4</formula>其中,Ts3为所述从i殳备向主设备发送DelayRequest报文的发送时间;Tm3为所述主设备接收到DelayResponse报文的时间。 9. The method of claim 5 times to achieve synchronization claim, wherein the step of calculating the line B delay value Delay of formula: <formula> formula see original document page 4 </ formula> where, Ts3 is Preparation of the transmission time of the transmission from the i Shu DelayRequest packets to the host device; DelayResponse of Tm3 received packets to the master device.
  10. 10、根据权利要求5所述的实现时间同步的方法,其特征在于,步骤C所述预设的时间偏移量Offset的计算公式为: Offset=Ts4-Tm4- Delay; 其中,Ts4为从设备接收主设备随后发来Sync报文的接收时间; Tm4为主"i殳备发送Sync报文的本地时间; Delay为主设备、从设备之间的线路时延值。 10, realized according to the time synchronization method of claim 5 claim, wherein the step C of the predetermined time is calculated as the Offset: Offset = Ts4-Tm4- Delay; wherein, a slave device Ts4 then the master device receiving the reception time sent by the Sync packets; Tm4 of the main "i Shu device sends the local time of the Sync message; delay-based equipment, the time delay value from the line between devices.
  11. 11、根据权利要求5所述的实现时间同步的方法,其特征在于,步骤C 所述利用所述Offset值对从设备的本地时间进行校正的过程为:所述从设备读取时间戳报文解析子模块中的时间偏移量Offset,通过RTC 校正/时间读写子模块调整PLL模块,将本地RTC的时间调整为与主设备时间同步网络一致。 11, realized according to the time synchronization method of claim 5 claim, wherein the step of using the Offset value C of the process of correcting the local time from the device to: read the timestamp from packet device time-resolved sub-module offset offset, the correction by the RTC / PLL module adjusts the time to read and write the sub-module, the local time of RTC adjusted to match the network time synchronization master.
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