CN112235067B - Centralized 1588 time synchronization method and time synchronization system - Google Patents
Centralized 1588 time synchronization method and time synchronization system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
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- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
Abstract
The invention discloses a centralized 1588 time synchronization method and a time synchronization system, wherein the time synchronization method comprises the following steps: the first circuit board and the second circuit board respectively stamp a time stamp t1 and a time stamp t2 for the synchronous message; the first master control disk conducts timestamp recombination based on the local synchronization time and the timestamp T1 to obtain a timestamp T1; the second master control disk conducts timestamp recombination based on the local synchronization time and the timestamp T2 to obtain a timestamp T2; the second line disk and the first line disk respectively stamp a time stamp t3 and a time stamp t4 for the delay request message; the second master control disk conducts timestamp recombination based on the local synchronization time and the timestamp T3 to obtain a timestamp T3; the first master control disk conducts timestamp recombination based on the local synchronization time and the timestamp T4 to obtain a timestamp T4; the second master is time biased according to timestamp T1, timestamp T2, timestamp T3, and timestamp T4. According to the invention, the stamping times are reduced, and the synchronization precision is improved.
Description
Technical Field
The invention belongs to the field of time synchronization, and particularly relates to a centralized 1588 time synchronization method and a time synchronization system.
Background
Commercial deployment of the 5G network is being promoted in order, the 5G is in the key period of industrial cultivation and application, and the 5G ultra-high precision synchronous network is taken as an indispensable basic support network, so that the development of the technology and the industry needs to be promoted as soon as possible. Compared with a 4G system, the 5G system has higher synchronization requirement precision (the precision required by a single station in 4G is +/-30 ns, and the precision required by a single station in 5G is +/-5 ns), and in order to meet the synchronization requirement of the 5G system, an ultra-high precision 1588 time synchronization technology is in the forefront.
Currently, the mainstream method of 1588 time synchronization devices is realized in a centralized manner. Referring to IEEE1588-2008 standard, 1588 time synchronization technology obtains 4 timestamps t1, t2, t3 and t4, a synchronization message correction domain CF1 and a delay request message correction domain CF2 by exchanging synchronization messages, delay request messages and delay response messages between a master device and a slave device, and then according to a formula:
time offset ((t2-t1-CF1) - (t4-t3-CF2))/2
And obtaining a time deviation value, and adjusting to realize time synchronization among the devices.
(1) As shown in fig. 1, a conventional centralized implementation apparatus generally includes a main control panel and a line panel, and a time synchronization module is disposed in both of the main control panel and the line panel.
And the master control disk time synchronization module finishes the sending and receiving work of the 1588 message, calculates deviation according to the collected data and finishes the time synchronization adjustment of the device.
And the circuit board time synchronization module completes normal forwarding and timestamp stamping of the 1588 message and corrects the forwarding delay of the message in the device.
The time synchronization module of the master control panel and the time synchronization module of the line panel must ensure time synchronization, and only when the time reference of 2 modules is consistent, the internal forwarding time delay of the message corrected by the line panel is accurate. It is common practice for the master to send a 1PPS + TOD (Time of Day, abbreviated TOD) signal to the line board, which synchronizes the Time of 1 slave master every 1 second.
(2) As shown in fig. 2, a schematic diagram of obtaining the t1 and t2 timestamps and the sync message correction field CF1 is shown.
The device 1 uses the time synchronization module of the master control disk as a master clock, sends a synchronization message and stamps a timestamp t1, the timestamp is carried in the synchronization message and sent, and at this time, the value of the correction field CF1 field of the synchronization message is 0.
The circuit board time synchronization module of the device 1 receives the synchronization message, stamps a timestamp t1', and updates the correction field CF1 of the message to t1' -t1 (the difference is just the forwarding delay of the synchronization message in the device 1), so that the synchronization message is forwarded out of the device 1.
The device 2 circuit board time synchronization module receives the synchronization message, and stamps a timestamp t2', and the timestamp is carried in the synchronization message and is forwarded to the device 2 master control board.
The device 2 master control disk time synchronization module is used as a slave clock, receives the synchronization message and stamps a timestamp t2, and the correction domain CF1 of the update message takes the value of t1'-t1+ t2-t2' (the difference is exactly the total forwarding delay of the message in the devices 1 and 2).
(3) As shown in fig. 3, a schematic diagram of the correction domain CF2 for obtaining the t3 and t4 timestamps and the delay request message is shown.
The device 2 uses the master control disk time synchronization module as a slave clock, sends a delay request message and stamps a timestamp t3, the timestamp is stored locally and is sent out in the delay request message, and the value of the CF2 field of the message is 0 at this time.
The time synchronization module of the circuit board of the device 2 receives the delay request message, stamps a timestamp t3', updates the correction domain CF2 of the delay request message to take the value of t3' -t3 (the difference is exactly the forwarding delay of the delay request message in the device 2), and forwards the delay request message out of the device 2.
The time synchronization module of the circuit board of the device 1 receives the time delay request message and stamps a time stamp t4', and the time stamp is carried in the time delay request message and is forwarded to the master control board of the device 1.
The device 1 uses the time synchronization module of the master control disk as a master clock, receives the delay request message and stamps a timestamp t4, and the correction domain CF2 of the update message takes the value of t3'-t3+ t4-t4' (the difference is exactly the total forwarding delay of the message in the devices 1 and 2).
The device 1 main control panel time synchronization module replies a delay response message, a delay request message carries t4 and CF2, the delay request message is transmitted to the device 2 main control panel time synchronization module all the time, and intermediate links are not processed.
Through the above (2) and (3), the slave clock device time synchronization module has acquired all the data required for adjusting the deviation, and can normally complete the time synchronization with the master clock device time synchronization module. Careful analysis has revealed that this implementation presents a potential problem.
As shown in fig. 4, assuming that the initial time of the master clock device master time synchronization module and the initial time of the line disk time synchronization module are both 0, and the time of the slave clock device master time synchronization module and the time of the line disk time synchronization module are both 5, then the time deviation of the master clock device and the slave clock device is 5, and the time delay of the forwarding path between the message modules is not fixed to 1, then the deviation needs to be calculated and adjusted through message interaction.
The initial time of the time synchronization module of the master control disk of the device 1 is 0, at this time, a synchronization message is sent out, a timestamp t1 is printed as 0, and at this time, the value of the CF1 field of the message is 0.
The device 1 disk time synchronization module receives the synchronization message, and at this time, the module time is 1, so that the timestamp t1 'is 1, and the value of the correction field CF1 of the update message is t1' -t1 is 1-0.
The device 2 disk time synchronization module receives the synchronization message, and the module time is 7, so the timestamp t2' is 7.
The device 2 master control disk time synchronization module receives the synchronization message, and at this time, the module time is 8, so that the timestamp t2 is 8, and the value of the correction field CF1 of the update message is t1'-t1+ t2-t2', 1-0+8-7 is 2.
The device 2 sends a delay request message by a master control disk time synchronization module, and if the delay request message is sent immediately while the synchronization message is received, the module time is still 8 at this time, so that the timestamp t3 is 8, and the value of the correction field CF2 field of the message is 0 at this time.
The device 2 disk time synchronization module receives the delay request message, and at this time, the module time is 9, so that the timestamp t3 'is 9, and the value of the correction field CF2 of the update message is t3' -t 3-9-8-1.
The device 1 receives the delay request message from the line disk time synchronization module, and at this time, the module time is 5, so that the timestamp t4' is 5.
The device 1 master control disk time synchronization module receives the delay request message, and at this time, the module time is 6, so that the timestamp t4 is 6, and the value of the correction field CF2 of the update message is t3'-t3+ t4-t4', 9-8+6-5 is 2.
After the messages are exchanged, the slave clock device calculates the deviation ((t2-t1-CF1) - (t4-t3-CF2))/2 ((8-0-2) - (6-8-2))/2 is 5, which means that the slave clock device is 5 times faster than the master clock device, at this time, the time of the slave clock device is 11, so the adjustment time is 11-5-6, and the time of the master clock device is exactly 6, so the two devices are time-synchronized.
However, only the slave clock master time synchronization module and the slave clock line board time synchronization module need to be adjusted at this time, which is still 11, according to the above (1), the slave clock master time synchronization module realizes synchronization between the two modules by outputting a 1PPS + TOD signal to the slave clock line board time synchronization module, however, the signal is sent out 1 time per second, and then if:
firstly, before the slave clock finishes the next message interaction, the slave clock line panel time synchronization module synchronizes the slave clock master control panel time synchronization module in time, so that the time deviation of the master clock device and the slave clock device is always fixed to be 0 and synchronous convergence is found no matter how many times of message interaction calculation deviation adjustment is repeated in the following process.
Secondly, before the slave clock finishes the next message interaction, the slave clock circuit board time synchronization module cannot timely synchronize the slave clock master control board time synchronization module, and if the message interaction is finished for 4 times in 1 second and the deviation calculation before the message interaction is repeated for multiple times, the time deviation of the master clock device and the slave clock device is found to be as shown in fig. 5, the time deviation cannot be stably converged to 0, and the requirement of time synchronization cannot be met.
In summary, the aforementioned time synchronization method has the following drawbacks:
(1) for the traditional centralized implementation device, the message interaction speed must be required to be not more than 1 time per second, otherwise, the synchronization cannot be converged. According to the requirement of 1588 standard, the message interaction is generally completed 16 times per second, which is far more than 1 time, and the synchronous system can not be converged under the condition of high-rate message interaction.
(2) The Sync message transmitted from device 1 to device 2 needs to be stamped with 4 timestamps t1, t1', t2 and t2' in one direction. The current stamping precision (generally only 4ns) is easy to meet the index of single station +/-30 ns in 4G era, but for the index of ultrahigh precision single station +/-5 ns in 5G era, 4 timestamps are stamped in a single direction, so that the index requirement is difficult to meet.
The current mainstream centralized scheme has a plurality of stamping points, and is very difficult to meet the index of +/-5 ns, and under the condition of high-rate message interaction, a synchronization system cannot be converged, so that a more reasonable system must be designed to realize ultrahigh-precision time synchronization so as to meet 5G application.
Disclosure of Invention
Aiming at the defects or improvement requirements of the prior art, the invention provides a centralized 1588 time synchronization method and a time synchronization system, and aims to reduce the stamping times and improve the time synchronization precision by only stamping two necessary timestamps for unidirectional message transmission, thereby solving the technical problems that the existing 1588 time synchronization scheme has more stamping points and cannot meet the index of 5G times ultrahigh-precision single station +/-5 ns.
To achieve the above object, according to one aspect of the present invention, there is provided a centralized 1588 time synchronization method applied to a time synchronization system, the time synchronization system including a master clock device and a slave clock device, the master clock device including a first master and a first line driver, the slave clock device including a second master and a second line driver, the time synchronization method including:
in the process that the master clock device sends the synchronous message to the slave clock device, the first circuit board and the second circuit board respectively stamp a time stamp t1 and a time stamp t2 on the synchronous message;
the first master control disk conducts timestamp recombination based on local synchronization time and the timestamp T1 to obtain a timestamp T1, and the timestamp T1 is sent to the second master control disk;
the second master control disk conducts time stamp recombination on the basis of local synchronization time and the time stamp T2 to obtain a time stamp T2;
in the process that the slave clock device sends the delay request message to the master clock device, the second circuit board and the first circuit board respectively stamp a time stamp t3 and a time stamp t4 on the delay request message;
the second master control disk conducts time stamp recombination on the basis of local synchronization time and the time stamp T3 to obtain a time stamp T3;
the first master control disk conducts timestamp recombination based on local synchronization time and the timestamp T4 to obtain a timestamp T4, and the timestamp T4 is sent to the second master control disk;
the second master control disk obtains a time offset according to the time stamp T1, the time stamp T2, the time stamp T3 and the time stamp T4 so as to complete time synchronization adjustment according to the time offset.
Preferably, the time synchronization method further includes:
and the first master control panel sends a time synchronization signal to the first circuit panel, and the second master control panel sends a time synchronization signal to the second circuit panel so as to ensure time synchronization between the master control panel and the circuit panels.
Preferably, the time synchronization signal is a 4Khz + TOD signal.
Preferably, the time synchronization method further includes:
acquiring a correction domain CF1 of the synchronous message and a correction domain CF2 of the delay request message;
the second master control disk obtaining a time offset according to the time stamp T1, the time stamp T2, the time stamp T3 and the time stamp T4, so that the completing the time synchronization adjustment according to the time offset comprises:
the second main control panel obtains time deviation according to a formula I so as to complete time synchronization adjustment according to the time deviation;
wherein, the first formula is: the time offset is ((T2-T1-CF1) - (T4-T3-CF 2))/2.
Preferably, the time stamp reorganizing by the first master control disk based on the local synchronization time and the time stamp T1 to obtain a time stamp T1, and sending the time stamp T1 to the second master control disk includes:
the first master control disk acquires a timestamp t1 returned by the first circuit board, wherein the timestamp t1 is a nanosecond value of 32 bits;
the first master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t1 is greater than a nanosecond value Tns;
if the timestamp T1 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T1 and the subtracted second value Ts to form a timestamp T1;
if the timestamp T1 is smaller than the nanosecond value Tns, directly forming a timestamp T1 by using the timestamp T1 and the second value Ts;
and the first master control disk transmits the following message carrying the timestamp T1 to the second master control disk.
Preferably, the timestamp T2 is a nanosecond value of 32bits, and the obtaining of the timestamp T2 by the second master control performing timestamp reassembly based on the local synchronization time and the timestamp T2 includes:
the second master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t2 is greater than a nanosecond value Tns;
if the timestamp T2 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T2 and the subtracted second value Ts to form a timestamp T2;
and if the timestamp T2 is less than the nanosecond value Tns, directly forming a timestamp T2 by using the timestamp T2 and the second value Ts, and storing the timestamp T2 locally.
Preferably, the time stamp reorganizing by the second master control disk based on the local synchronization time and the time stamp T3, and obtaining the time stamp T3 includes:
the second master control disk acquires a timestamp t3 returned by the second line disk, wherein the timestamp t3 is a nanosecond value of 32 bits;
the second master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t3 is greater than a nanosecond value Tns;
if the timestamp T3 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T3 and the subtracted second value Ts to form a timestamp T3;
if the timestamp T3 is smaller than the nanosecond value Tns, directly forming a timestamp T3 by using the timestamp T3 and the second value Ts;
the second master control disk stores the timestamp T3 locally.
Preferably, the time stamp reorganizing by the first master control disk based on the local synchronization time and the time stamp T4 to obtain a time stamp T4, and sending the time stamp T4 to the second master control disk includes:
the first circuit board sends a delay request message carrying a timestamp t4 to the first master control board, wherein the timestamp t4 is a nanosecond value of 32 bits;
the first master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t4 is greater than a nanosecond value Tns;
if the timestamp T4 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T4 and the subtracted second value Ts to form a timestamp T4;
if the timestamp T4 is smaller than the nanosecond value Tns, directly forming a timestamp T4 by using the timestamp T4 and the second value Ts;
and the first master control disk transmits the delay response message carrying the timestamp T4 to the second master control disk.
According to another aspect of the present invention, there is provided a centralized 1588 time synchronization system, which includes a master clock device and a slave clock device, where the master clock device includes a first master and a first line board, the slave clock device includes a second master and a second line board, and the first line board and the second line board are respectively used to timestamp a message according to the time synchronization method of the present invention;
the first master control disk and the second master control disk are respectively used for recombining the time stamps printed on the line disks according to the time synchronization method;
the second master control disk is used for calculating the time deviation according to the time synchronization method of the invention so as to complete time synchronization adjustment according to the time deviation.
Preferably, the first master control panel, the first circuit panel, the second master control panel and the second circuit panel each include a time synchronization module, the time synchronization module of the first master control panel is configured to output a 4Khz + TOD signal to perform time synchronization on the time synchronization module of the first circuit panel, and the time synchronization module of the second master control panel is configured to output a 4Khz + TOD signal to perform time synchronization on the time synchronization module of the second circuit panel.
Generally, compared with the prior art, the technical scheme of the invention has the following beneficial effects: the invention provides a centralized 1588 time synchronization method and a time synchronization system, wherein the time synchronization method is applied to the time synchronization system, the time synchronization system comprises a master clock device and a slave clock device, the master clock device comprises a first master control panel and a first circuit panel, the slave clock device comprises a second master control panel and a second circuit panel, and the time synchronization method comprises the following steps: in the process that the master clock device sends the synchronous message to the slave clock device, the first circuit board and the second circuit board respectively stamp a time stamp t1 and a time stamp t2 for the synchronous message; the first master control disk conducts timestamp recombination based on local synchronization time and a timestamp T1 to obtain a timestamp T1, and the timestamp T1 is sent to the second master control disk; the second master control disk conducts timestamp recombination based on the local synchronization time and the timestamp T2 to obtain a timestamp T2; in the process that the slave clock device sends the delay request message to the master clock device, the second circuit board and the first circuit board respectively stamp a time stamp t3 and a time stamp t4 on the delay request message; the second master control disk conducts timestamp recombination based on the local synchronization time and the timestamp T3 to obtain a timestamp T3; the first master control disk conducts timestamp recombination based on local synchronization time and a timestamp T4 to obtain a timestamp T4, and the timestamp T4 is sent to the second master control disk; the second master obtains a time offset according to the time stamp T1, the time stamp T2, the time stamp T3 and the time stamp T4, so as to complete time synchronization adjustment according to the time offset.
The one-way message transmission only needs to print two necessary time stamps, only 4 time stamps are printed in the whole synchronous interaction process, compared with the current mainstream method, 8 time stamps are printed, half of stamping points are reduced, the stamping times are reduced, the time synchronization precision is improved, after the stamping precision reaches the limit, the improvement can greatly improve the synchronization effect, and the index of 5G times ultrahigh precision single station +/-5 ns can be met.
Drawings
Fig. 1 is a schematic diagram of a conventional centralized implementation apparatus according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a conventional centralized implementation apparatus interacting a synchronization message according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an interaction delay request packet of a conventional centralized implementation apparatus according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an exemplary embodiment of a conventional centralized implementation apparatus according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of high rate deviation divergence in accordance with an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a centralized 1588 time synchronization system according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a centralized 1588 time synchronization method according to an embodiment of the present invention;
fig. 8 is a schematic diagram of interaction of a sync message according to an embodiment of the present invention;
fig. 9 is a schematic diagram of interaction of a delay request packet according to an embodiment of the present invention;
fig. 10 is a schematic diagram of timestamp reorganization according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1:
in order to solve the foregoing problems, this embodiment provides a centralized 1588 time synchronization system, where the time synchronization system includes a master clock device and a slave clock device, each device includes a master control panel and a line panel, and each of the master control panel and the line panel includes a time synchronization module. And the master control disk time synchronization module finishes the sending and receiving work of the 1588 message, and calculates the deviation according to the collected timestamp data to finish the time synchronization adjustment of the device. The master control disk time synchronization module outputs a 4Khz + TOD signal to the line disk time synchronization module for synchronization. And the circuit board time synchronization module completes normal forwarding and timestamp stamping of the 1588 message and returns the timestamp to the master control board for full timestamp reassembly.
Specifically, as shown in fig. 6, the time synchronization system includes a master clock device and a slave clock device, the master clock device includes a first master and a first line board, the slave clock device includes a second master and a second line board, the first master, the first line board, the second master and the second line board each include a time synchronization module, the time synchronization module of the first master is used to output a 4Khz + TOD signal to the time synchronization module of the first line board for time synchronization, the time synchronization module of the second master is used to output a 4Khz + TOD signal to the time synchronization module of the second line board for time synchronization, since the 4Khz + TOD signal can transmit 4000 times of time signals per second, that is, the line board can synchronize the master 4000 times per second, which is much higher than the synchronization and adjustment of the master in the prior art every 256 times per second, and the time of the master control panel and the time of the line panel can be ensured to be synchronous in real time at any message rate.
The first line board and the second line board are respectively used for stamping timestamps for messages, and the specific implementation process is described in embodiment 2 below.
The first master control panel and the second master control panel are respectively used for recombining the timestamps printed on the line panels, the detailed implementation process is described in the following embodiment 2, the second master control panel is used for calculating the time deviation so as to complete the time synchronization adjustment according to the time deviation, and the detailed implementation process is described in the following embodiment 2.
Example 2:
based on the time synchronization system in embodiment 1, this embodiment mainly explains a specific implementation process of the centralized 1588 time synchronization method, and as shown in fig. 7, this embodiment provides a centralized 1588 time synchronization method, where the time synchronization method includes the following steps:
step 101: in the process that the master clock device sends the synchronous message to the slave clock device, the first circuit board and the second circuit board respectively stamp a time stamp t1 and a time stamp t2 on the synchronous message.
In this embodiment, referring to fig. 6, in order to ensure that the time between the master and the line panel can be synchronized, the first master sends a time synchronization signal to the first line panel, and the second master sends a time synchronization signal to the second line panel, so as to ensure the time synchronization between the master and the line panel. Wherein, the time synchronization signal is a 4Khz + TOD signal. The circuit board and the master control board are synchronous through 4Khz + TOD, and the real-time of the master control board is sent to the circuit board through a 4k clock, so that the adjustment of the circuit board can always follow the rhythm of the master control board, and the problem of incapability of convergence is avoided.
The 1588 message includes a synchronization message (sync message), a follow-up message (follow _ up message), a delay request message (delay _ req message), and a delay response message (delay _ resp message).
Referring to fig. 8, the time synchronization module of the first master sends a synchronization message, and the time synchronization module of the first circuit board forwards the synchronization message out of the master clock device, and stamps t1 on the synchronization message, and transmits the timestamp t1 back to the first master through a return message.
Step 102: and the first master control disk conducts time stamp recombination on the basis of local synchronization time and the time stamp T1 to obtain a time stamp T1, and the time stamp T1 is sent to the second master control disk.
Specifically, the first master control disk obtains a timestamp t1 returned by the first line disk, where the timestamp t1 is a nanosecond value of 32 bits; the first master control disk acquires local synchronization time, wherein the local synchronization time consists of a second value of 48bits and a nanosecond value of 32bits, and the local synchronization time is converted into a full nanosecond form T (Ts) multiplied by 1000000000+ Tns before recombination, so that the second value Ts of 48bits and the nanosecond value Tns of 32bits are obtained. It should be noted that the local synchronization time is composed of a 48-bit second value and a 32-bit nanosecond value, the nanosecond value is 1000000000-1 ═ 9999999ns at most, the timestamp in the form of all nanoseconds is different by 32bits, which can mean that 0 xfffffffffff-1 ═ 4294967294ns, so that the two 32bits are different, and the timestamp printed by the line board is a 32-bit timestamp, which can reach 4294967294ns, so that it is necessary to convert to a full timestamp nanosecond and compare with the low 32 bits.
The reconstruction needs to replace the lower 32bits (Tns) of the full nanosecond timestamp by the returned 32bits timestamp t1, and since the 32bits are overturned due to overflow, namely the lower 32bits (Tns) of the full nanosecond timestamp is reset to 0 again when the 32bits are out of limit, the lower 32bits (Tns) of the full nanosecond timestamp is intercepted before the reconstruction and compared with the returned 32bits timestamp t1(32bits), and the replacement is carried out strategically according to the comparison result, and the specific implementation process is as follows:
judging whether the timestamp T1 is greater than a nanosecond value Tns or not, if the timestamp T1 is greater than the nanosecond value Tns, namely the nanosecond value Tns is less than T1 and 32bits are low, subtracting 1 from a second value Ts (48bits high of the all-nanosecond timestamp) of local synchronization time, and forming a timestamp T1 (80-bit full timestamp) by the timestamp T1 and the subtracted second value Ts;
and if the timestamp T1 is smaller than the nanosecond value Tns, namely, Tns is larger than T1, and 32bits are not turned over, directly forming a timestamp T1(80bits full timestamp) by using the timestamp T1 and the second value Ts.
And the first master control disk transmits the following message carrying the timestamp T1 to the second master control disk. Because the timestamp is transmitted in the form of 48bits seconds value +32bits nanoseconds value in the IEEE 1588V2 protocol, the recombined T1 needs to be converted into the form of 48bits seconds value +32bits nanoseconds value again. Specifically, the first master control panel converts the recombined T1(80bits full timestamp) into a form of 48bits seconds +32bits nanoseconds, and sends the following message to a line panel of the same device (i.e., the first line panel), and the first line panel forwards the following message carrying a timestamp T1 out of the master clock device, so as to send the timestamp T1 to the second master control panel. And the time synchronization module of the second master control disk receives the following message and extracts T1 (in the form of 48bits second value +32bits nanosecond value) in the following message, so that the timestamp T1 is acquired.
To facilitate understanding of the foregoing, reference is made to FIG. 10 for illustration:
because the master control disk and the line disk are synchronized, assuming that the full nanosecond timestamp T of the local synchronization time of the master control disk at the time of stamping the line disk is 0x 00000000000100000002, the full nanosecond timestamp T of the 32bits stamped by the line disk is 0x 00000001, assuming that 9ns is required for transmitting the timestamp back to the master control disk through a message, when T1(32bits) is transmitted back to the master control disk to be recombined, the local synchronization time T of the master control disk is 0x 00000000000010002 +9 is 0x 0000000000010000000B, at this time, the low 32bits Tns of the full nanosecond timestamp T of the local synchronization time of the master control disk is 0x 0000B, no inversion occurs, but the master control disk time synchronization module can only judge by comparing the sizes of the 32bits timestamps T and transmitted back, that the time Tns is greater than T1(32bits), and the time of the full nanosecond timestamp T32 (32bits) is directly replaced by the time T2(32bits) of the returned timestamp T0000ns, namely, the full nanosecond (32) consisting of the low time T32 (32bits) of the full 0000000000000, namely, the full nanosecond (32) timestamp T38764), this time is the full nanosecond time at the moment when the line disk generates the 32bits T1 timestamp, i.e. T1(80bits full timestamp) ═ 0x 00000000000100000001, which is passed to the slave clock device for time synchronization.
Because the master control disk and the line disk are synchronized, assuming that the local synchronization time full nanosecond timestamp T of the master control disk at the time of stamping the line disk is 0x 000000000001 FFFE, assuming that the time stamp needs to be 9ns by a message to be transmitted back to the master control disk, when T1(32bits) is transmitted back to the master control disk to be recombined, the local synchronization time T1(32bits) of the master control disk is 0xfffff FFFD, assuming that the time stamp needs to be 9ns, when T1(32bits) is transmitted back to the master control disk to be recombined, the local synchronization time T of the master control disk is 0x 00000001 FFFE +9 is 0x 0000000000020000000200000007, at this time, the low 32bits Tns of the local synchronization time full nanosecond timestamp of the master control disk is 0x 00000007, the master control disk time synchronization module can only judge by comparing the sizes of the returned 32bits timestamps of the master control disk, that is Tns < T1(32bits), when the local synchronization time of the master control disk is recombined, the high synchronization time full nanosecond time ts of the master control disk needs to be reduced by 0x 00003, that is 0x 0000000048, that is a high time full nanosecond, that is a part of the local synchronization time stamp, that is reduced by 0x 00000 x 00003, that is reduced by (T00003) and a part, that is reduced by a part of the full nanosecond) (i., namely, the low 32bits of 0x 000000000000000100000007 is replaced by t1(32bits) to obtain 0x 000000000001 FFFF FFFD, which is the full nanosecond time at the moment when the line disk generates the 32bits t1 timestamp, i.e. t1(80bits full timestamp) is 0x 000000000001 FFFD, and the time needs to be transmitted to the slave clock device for time synchronization operation.
Step 103: and the second master control disk conducts time stamp reorganization on the basis of the local synchronization time and the time stamp T2 to obtain a time stamp T2.
The timestamp T2 is a nanosecond value of 32bits, the second master control board acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32bits, specifically, the local synchronization time is composed of the second value of 48bits and the nanosecond value of 32bits, before recombination, the local synchronization time needs to be converted into the full nanosecond form T (Ts) 1000000000+ Tns, a higher 48bit is taken as the second value Ts, a lower 32bit is taken as the nanosecond value, and thus the second value Ts of 48bits and the nanosecond value Tns of 32bits are obtained.
The reconstruction needs to replace the lower 32bits (Tns) of the full nanosecond timestamp by the returned 32bits timestamp T2, and since the 32bits are overturned due to overflow, namely the lower 32bits (Tns) of the full nanosecond timestamp is reset to 0 again when the 32bits are out of limit, the lower 32bits (Tns) of the full nanosecond timestamp is intercepted before the reconstruction and compared with the returned 32bits timestamp T2(32bits), and the replacement is carried out strategically according to the comparison result, and the specific implementation process is as follows:
judging whether the timestamp T2 is greater than a nanosecond value Tns or not, if the timestamp T2 is greater than the nanosecond value Tns, namely the nanosecond value Tns is less than T2 and 32bits are low, subtracting 1 from a second value Ts (48bits high of the all-nanosecond timestamp) of local synchronization time, and forming a timestamp T2 (80-bit full timestamp) by the timestamp T2 and the subtracted second value Ts;
if the timestamp T2 is smaller than the nanosecond value Tns, namely, Tns is greater than T2, and 32bits are not turned over, the timestamp T2 and the second value Ts are directly used to form a timestamp T2(80bits full timestamp), and the timestamp T2 is stored locally.
In the one-way message transmission process, only the first circuit board and the second circuit board stamp the synchronous message twice, namely, the single device only stamps the time stamp once at the outlet of the circuit board, and the time stamping times are reduced and the time synchronization precision is improved through the time stamp returning and time stamp recombining technology.
Step 104: in the process that the slave clock device sends the delay request message to the master clock device, the second circuit board and the first circuit board respectively stamp the delay request message with a timestamp t3 and a timestamp t 4.
As shown in fig. 8, Delay _ req packets (Delay request packets) and Delay _ resp packets (Delay response packets) complete forwarding and time stamping between the master clock device and the slave clock device, and the specific implementation process is as follows:
and the time synchronization module of the second master control panel sends a Delay request message, the time synchronization module of the second circuit panel receives the Delay _ req message, stamps t3(32bits) on the message, forwards the message out of the slave clock device, and simultaneously transmits the t3(32bits) timestamp back to the second master control panel through a return message.
Step 105: and the second master control disk conducts time stamp reorganization on the basis of the local synchronization time and the time stamp T3 to obtain a time stamp T3.
Specifically, the second master controller obtains a timestamp t3 returned by the second line driver, where the timestamp t3 is a nanosecond value of 32 bits; the second master control disk obtains local synchronization time, converts the local synchronization time into a full nanosecond form, and obtains a second value Ts of 48bits and a nanosecond value Tns of 32bits, specifically, the local synchronization time is composed of the second value of 48bits and the nanosecond value of 32bits, before recombination, the local synchronization time needs to be converted into the full nanosecond form T which is Ts × 1000000000+ Tns, a high 48bit is taken as the second value Ts, a low 32bit is taken as the nanosecond value, and therefore the second value Ts of 48bits and the nanosecond value Tns of 32bits are obtained.
The reconstruction needs to replace the lower 32bits (Tns) of the full nanosecond timestamp by the returned 32bits timestamp t3, and since the 32bits are overturned due to overflow, namely the lower 32bits (Tns) of the full nanosecond timestamp is reset to 0 again when the 32bits are out of limit, the lower 32bits (Tns) of the full nanosecond timestamp is intercepted before the reconstruction and compared with the returned 32bits timestamp t3(32bits), and the replacement is carried out strategically according to the comparison result, and the specific implementation process is as follows:
judging whether the timestamp T3 is greater than a nanosecond value Tns or not, if the timestamp T3 is greater than the nanosecond value Tns, namely the nanosecond value Tns is less than T3 and 32bits are low, subtracting 1 from a second value Ts (48bits high of the all-nanosecond timestamp) of local synchronization time, and forming a timestamp T3 (80-bit full timestamp) by the timestamp T3 and the subtracted second value Ts; if the timestamp T3 is smaller than the nanosecond value Tns, namely, Tns is larger than T3, and 32bits are not turned over, the timestamp T3 and the second value Ts are directly used to form a timestamp T3(80bits full timestamp); the second master control disk stores the timestamp T3 locally.
Step 106: and the first master control disk conducts time stamp recombination on the basis of local synchronization time and the time stamp T4 to obtain a time stamp T4, and the time stamp T4 is sent to the second master control disk.
And the first circuit board sends a delay request message carrying a timestamp t4 to the first master control board, wherein the timestamp t4 is a nanosecond value of 32 bits. The time synchronization module of the first master control disk receives the delay request message, extracts a T4(32bits) timestamp and recombines with local synchronization time, the local synchronization time is composed of a 48bits second value and a 32bits nanosecond value, the time synchronization module needs to be converted into a full nanosecond form T (Ts) 1000000000+ Tns before recombination, a high 48bits is taken as a second value Ts, a low 32bits is taken as a nanosecond value, and therefore the second value Ts of the 48bits and the nanosecond value Tns of the 32bits are obtained. The recombination needs to replace the low 32bits (Tns) of the full nanosecond timestamp with the 32bits timestamp t4(32bits) in the delay request message, and because the low 32bits can be inverted due to overflow, namely the low 32bits can be reset to 0 from the new state when the 32bits are out of limit, the low 32bits (Tns) of the full nanosecond timestamp is intercepted before the recombination and compared with the 32bits timestamp t4(32bits) in the delay request message, the specific process is as follows:
judging whether the timestamp t4 is greater than a nanosecond value Tns; if the timestamp T4 is greater than the nanosecond value Tns, which indicates that the 32-bit low event upset occurs, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T4 and the subtracted second value Ts to form a timestamp T4; and if the timestamp T4 is smaller than the nanosecond value Tns, which indicates that the 32bits are not flipped, the timestamp T4 and the second value Ts are directly used to form a timestamp T4.
And the first master control disk transmits the delay response message carrying the timestamp T4 to the second master control disk. Because the timestamp is transmitted in the form of 48bits seconds value +32bits nanoseconds value in the IEEE 1588V2 protocol, the recombined T4 needs to be converted into the form of 48bits seconds value +32bits nanoseconds value again. Specifically, the time synchronization module of the first master control panel converts the recombined T4(80bits full timestamp) into a form of 48bits second value +32bits nanosecond value again and stores the converted value into the delay response message, and sends the delay response message to the slave clock device, and the delay response message is transmitted to the master control panel time synchronization module of the slave clock device, and the intermediate link is not processed.
Step 107: the second master control disk obtains a time offset according to the time stamp T1, the time stamp T2, the time stamp T3 and the time stamp T4 so as to complete time synchronization adjustment according to the time offset.
In this embodiment, since the single message is only time stamped once, the correction field CF1 of the synchronous message is equal to 0, and the correction field CF2 of the delay request message is equal to 0, then the second master control disk is configured by the following formula: the time offset is calculated as ((T2-T1) - (T4-T3))/2, and time synchronization is performed.
In the embodiment, only two necessary timestamps are needed to be stamped in one-way message transmission, only 4 timestamps are stamped in the whole synchronous interaction process, compared with the current mainstream method, the number of stamping points required to be stamped is reduced by half by 8 timestamps, and after the stamping precision reaches the limit, the improvement can greatly improve the synchronization effect; meanwhile, the time synchronization between the circuit board and the master control board is ensured by 4Khz + TOD, the real-time synchronization between the circuit board and the master control board of the same device is also a necessary condition for reducing the stamping points, and the two technical points jointly realize the centralized 1588 ultrahigh-precision time synchronization.
Example 3:
in an actual application scenario, a case that CF1 and CF2 are not 0 is not excluded, and in order to improve the applicability of the foregoing time synchronization method, in this embodiment, unlike the foregoing embodiment 2, the time synchronization method further includes:
the second master control disk obtains a correction field CF1 in the correlation field of the header of the synchronization packet, and obtains a correction field CF2 in the correlation field of the header of the delay response packet.
In this embodiment, the second master controller obtains a time offset according to the timestamp T1, the timestamp T2, the timestamp T3, the timestamp T4, the correction domain CF1, and the correction domain CF2, so as to complete time synchronization adjustment according to the time offset. Specifically, the second master control panel obtains a time deviation according to a formula I, so as to complete time synchronization adjustment according to the time deviation; wherein, the first formula is: the time offset is ((T2-T1-CF1) - (T4-T3-CF 2))/2.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A centralized 1588 time synchronization method, which is applied to a time synchronization system, wherein the time synchronization system comprises a master clock device and a slave clock device, the master clock device comprises a first master control panel and a first line panel, the slave clock device comprises a second master control panel and a second line panel, and the time synchronization method comprises:
in the process that the master clock device sends the synchronous message to the slave clock device, the first circuit board and the second circuit board respectively stamp a time stamp t1 and a time stamp t2 on the synchronous message;
the first master control disk conducts timestamp recombination based on local synchronization time and the timestamp T1 to obtain a timestamp T1, and the timestamp T1 is sent to the second master control disk;
the second master control disk conducts time stamp recombination on the basis of local synchronization time and the time stamp T2 to obtain a time stamp T2;
in the process that the slave clock device sends the delay request message to the master clock device, the second circuit board and the first circuit board respectively stamp a time stamp t3 and a time stamp t4 on the delay request message;
the second master control disk conducts time stamp recombination on the basis of local synchronization time and the time stamp T3 to obtain a time stamp T3;
the first master control disk conducts timestamp recombination based on local synchronization time and the timestamp T4 to obtain a timestamp T4, and the timestamp T4 is sent to the second master control disk;
the second master control disk obtains a time offset according to the time stamp T1, the time stamp T2, the time stamp T3 and the time stamp T4 so as to complete time synchronization adjustment according to the time offset.
2. The time synchronization method of claim 1, further comprising:
and the first master control panel sends a time synchronization signal to the first circuit panel, and the second master control panel sends a time synchronization signal to the second circuit panel so as to ensure time synchronization between the master control panel and the circuit panels.
3. The method according to claim 2, wherein the time synchronization signal is a 4Khz + TOD signal.
4. The time synchronization method of claim 1, further comprising:
acquiring a correction domain CF1 of the synchronous message and a correction domain CF2 of the delay request message;
the second master control disk obtaining a time offset according to the time stamp T1, the time stamp T2, the time stamp T3 and the time stamp T4, so that the completing the time synchronization adjustment according to the time offset comprises:
the second main control panel obtains time deviation according to a formula I so as to complete time synchronization adjustment according to the time deviation;
wherein, the first formula is: the time offset is ((T2-T1-CF1) - (T4-T3-CF 2))/2.
5. The time synchronization method of claim 1, wherein the first master control disk performs time stamp reorganization based on the local synchronization time and the time stamp T1 to obtain a time stamp T1, and the sending the time stamp T1 to the second master control disk comprises:
the first master control disk acquires a timestamp t1 returned by the first circuit board, wherein the timestamp t1 is a nanosecond value of 32 bits;
the first master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t1 is greater than a nanosecond value Tns;
if the timestamp T1 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T1 and the subtracted second value Ts to form a timestamp T1;
if the timestamp T1 is smaller than the nanosecond value Tns, directly forming a timestamp T1 by using the timestamp T1 and the second value Ts;
and the first master control disk transmits the following message carrying the timestamp T1 to the second master control disk.
6. The time synchronization method of claim 1, wherein the time stamp T2 is a nanosecond value of 32bits, and the time stamp reorganizing by the second master control disk based on the local synchronization time and the time stamp T2 to obtain the time stamp T2 comprises:
the second master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t2 is greater than a nanosecond value Tns;
if the timestamp T2 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T2 and the subtracted second value Ts to form a timestamp T2;
and if the timestamp T2 is less than the nanosecond value Tns, directly forming a timestamp T2 by using the timestamp T2 and the second value Ts, and storing the timestamp T2 locally.
7. The time synchronization method of claim 1, wherein the second master control disk performs time stamp reorganization based on the local synchronization time and the time stamp T3, and obtaining the time stamp T3 comprises:
the second master control disk acquires a timestamp t3 returned by the second line disk, wherein the timestamp t3 is a nanosecond value of 32 bits;
the second master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t3 is greater than a nanosecond value Tns;
if the timestamp T3 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T3 and the subtracted second value Ts to form a timestamp T3;
if the timestamp T3 is smaller than the nanosecond value Tns, directly forming a timestamp T3 by using the timestamp T3 and the second value Ts;
the second master control disk stores the timestamp T3 locally.
8. The time synchronization method of claim 1, wherein the first master control disk performs time stamp reorganization based on the local synchronization time and the time stamp T4 to obtain a time stamp T4, and the sending the time stamp T4 to the second master control disk comprises:
the first circuit board sends a delay request message carrying a timestamp t4 to the first master control board, wherein the timestamp t4 is a nanosecond value of 32 bits;
the first master control disk acquires local synchronization time, and converts the local synchronization time into a full nanosecond form to obtain a second value Ts of 48bits and a nanosecond value Tns of 32 bits;
judging whether the timestamp t4 is greater than a nanosecond value Tns;
if the timestamp T4 is greater than the nanosecond value Tns, subtracting 1 from the second value Ts of the local synchronization time, and combining the timestamp T4 and the subtracted second value Ts to form a timestamp T4;
if the timestamp T4 is smaller than the nanosecond value Tns, directly forming a timestamp T4 by using the timestamp T4 and the second value Ts;
and the first master control disk transmits the delay response message carrying the timestamp T4 to the second master control disk.
9. A centralized 1588 time synchronization system, comprising a master clock device and a slave clock device, wherein the master clock device comprises a first master control panel and a first line panel, and the slave clock device comprises a second master control panel and a second line panel, wherein the first line panel and the second line panel are respectively used for time stamping messages according to the time synchronization method of any one of claims 1 to 8;
the first master control disk and the second master control disk are respectively used for recombining the time stamps printed on the line disks according to the time synchronization method of any one of claims 1 to 8;
the second master control disk is used for calculating the time deviation according to the time synchronization method of any one of claims 1 to 8, so as to complete time synchronization adjustment according to the time deviation.
10. The time synchronization system of claim 9, wherein the first master, the first line board, the second master and the second line board each comprise a time synchronization module, the time synchronization module of the first master is configured to output a 4Khz + TOD signal to the time synchronization module of the first line board for time synchronization, and the time synchronization module of the second master is configured to output a 4Khz + TOD signal to the time synchronization module of the second line board for time synchronization.
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