CN107294634A - The centralized approach of 1588 time synchronizeds is realized in a kind of distributed system - Google Patents
The centralized approach of 1588 time synchronizeds is realized in a kind of distributed system Download PDFInfo
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- CN107294634A CN107294634A CN201710442697.1A CN201710442697A CN107294634A CN 107294634 A CN107294634 A CN 107294634A CN 201710442697 A CN201710442697 A CN 201710442697A CN 107294634 A CN107294634 A CN 107294634A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0647—Synchronisation among TDM nodes
- H04J3/065—Synchronisation among TDM nodes using timestamps
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Abstract
The centralized approach of 1588 time synchronizeds is realized in a kind of distributed system, is related to 1588 time synchronized fields, including：Master clock node sends sync message, carries t1 and t1'-t1, t1' at the time of sending sync message with node line card, to be received from clock node, stamps t2' and t2, calculates sync message correction time delay value；From clock node transmission delay request message, carry t3 and t3'-t3, t3' is at the time of sending time delay request message with node line card, master clock node is received, and stamps t4' and t4, calculation delay request message correction time delay value, DELAY RESPONSE message is inserted into t4, issue from clock node, all timestamps and two correction time delay values are obtained from clock node, synchronized algorithm deadline passage time is synchronous.The present invention can reduce exploitation and debugging work load, simplify backboard wiring, and reduction synchronizing signal interference is externally embodied with overall time source information.
Description
Technical field
The present invention relates to 1588 time synchronized fields, realize that 1588 times are same in particular to a kind of distributed system
The centralized approach of step.
Background technology
1588 Time synchronization techniques are a kind of precise synchronization technology based on IEEE 1588V2 agreements, the agreement
The time synchronized of submicrosecond level can be realized, in mobile bearer network, except TDM (Time Division
Multiplexing, time division multiplexing) demand of business in itself, in addition it is also necessary to ensure the precise synchronization between base station.
At present, operator is mainly partial to realize for 1588 times by BC (Boundary Clock, boundary clock) pattern
It is synchronous.For the centralized mini-plant of single board, realize that BC model comparisions are simple, it is only necessary to which board possesses support
The hardware condition of 1588 functions, runs 1588 agreements on board.
But, it is necessary to support the port distribution of 1588 functions in each line card for distributed big-and-middle-sized equipment
On, because the hardware configuration of different line cards is different, all boards are required for running a set of BMC (Best Master
Clockalgorithm, best master clock) algorithm and 1588 agreements, it is not only excessive to take resource, exploitation and debugging work load
It is very big.Also, it is required for being mutually in step between each board, backboard wiring is complicated；When association between each line card in reversed process
Not at that time, synchronizing signal is easily disturbed tune；Equipment temporal information is divided into some pieces, and node was externally difficult to the overall time
Source information embodies.
The content of the invention
For defect present in prior art, it is an object of the invention to provide realize 1588 in a kind of distributed system
The centralized approach of time synchronized, reduction exploitation and debugging work load, simplify backboard wiring, reduction synchronizing signal interference, with whole
The time source information of body externally embodies.
To achieve the above objectives, the present invention takes the centralization side that 1588 time synchronizeds are realized in a kind of distributed system
Method, including step：
S1. by configuring interface, operation PTP protocol and BMC algorithms on the main control unit of 1588 functional nodes of all supports,
Calculate 1588 working conditions of each line card port, the line cards of 1588 messages of transmission in need complete related channel program configuration and synchronous
Processing configuration；
S2. master clock node sends sync message, carries master clock node main control unit and sends timestamp t1 and correction field
Value t1'-t1, wherein t1' for send sync message with node line card at the time of；
S3. the sync message is received from clock node, stamps from clock node line card and receive timestamp t2' and from clock
Node main control unit receives timestamp t2, and calculates correction time delay value (t2-t2')+(t1'- of the whole transmission path of sync message
t1)；
S4. from clock node transmission delay request message, carry from clock node main control unit and send timestamp t3 and correction
The value t3'-t3 of field, wherein t3' is at the time of sending time delay request message with node line card；
S5. master clock node receives the time delay request message, stamps the clamping of master clock nodal line and receives timestamp t4' and master
Clock node main control unit receives timestamp t4, and the correction time delay value (t4-t4') of the whole transmission path of calculation delay request message+
(t3'-t3)；
S6. t4 and (t4-t4')+(t3'-t3) are inserted into DELAY RESPONSE message by the main control unit of master clock node, are issued
From clock node；Received from the main control unit of clock node after DELAY RESPONSE message, find corresponding time delay request message, obtain institute
There are timestamp and two correction time delay values；It is synchronous with the node main control unit passage time synchronized algorithm deadline.
On the basis of above-mentioned technical proposal, in the S2, the main control unit of master clock node is toward containing in same node
The line card of master status ports sends sync message；Correspondence line card, which is received, extracts t1 after sync message, sent in sync message
At the time of t1', calculate t1'-t1 values, and be filled up in the correction field of sync message.
On the basis of above-mentioned technical proposal, the main control unit issues the sync message of same node line card, wherein, message goes out
The value of port timestamp field is t1, and the value for now correcting field is 0.
On the basis of above-mentioned technical proposal, in the S3, the line card containing slave status ports is received from clock node
To sync message, the t2' for propagation delay time amendment is stamped, same node main control unit is sent to, synchronization is received with node main control unit
After message, t2 is stamped, and t1, t2' and t1'-t1 are obtained from sync message, (t2-t2')+(t1'-t1) is calculated.
On the basis of above-mentioned technical proposal, sent out from clock node line card by stipulated form between disk to same node main control unit
Sync message is sent, the value of its message exit port timestamp field is t1, and correction field value is t1'-t1, and t2' is inserted into synchronous report
The position arranged in text.
On the basis of above-mentioned technical proposal, in the S4, from the main control unit of clock node toward containing slave in same node
The line card transmission delay request message of status port；Correspondence line card extracts t3 after receiving time delay request message, in time delay request
T3' at the time of message is sent, calculates t3'-t3 value, and is filled up in the correction field of time delay request message.
On the basis of above-mentioned technical proposal, in the S5, the line card containing master status ports in master clock node
Receive time delay request message, stamp t4' and issue same node main control unit, t4 is stamped in same node main control unit, and extract t3'-t3 and
T4', calculates (t4-t4')+(t3'-t3).
On the basis of above-mentioned technical proposal, in the S6, formula is passed through from the main control unit of clock node
Calculate and master clock node time source time synchronized deviation offset, wherein CFsync=(t2-t2')+
(t1'-t1), it is the correction time delay value of the whole transmission path of sync message；CFdelayresp=(t4-t4')+(t3'-t3), be
The correction time delay value of the whole transmission path of time delay request message.
On the basis of above-mentioned technical proposal, main timing node and from timing node include main control unit and multiple line cards,
With between the main control unit and line card of node, stipulated form bag between 1588 protocol massages, disk is transmitted according to stipulated form between disk disk
Include packet sending and receiving rule and message format definition.
On the basis of above-mentioned technical proposal, each timestamp is same fiducial time.
The beneficial effects of the present invention are：
1st, the present invention supports 1588 agreements, and BMC algorithms and Time synchronization algorithm run on main control unit, the transmission of message and
Termination is also in main control unit, for overall equipment, and 1588 messages send and receive interface on line card；Except main control unit
Hardware needs the 1588BC patterns for supporting to complete, and each line card hardware requirement only needs to support 1588TC (Transparent
Clock, transparent clock) pattern, reduction exploitation and the workload debugged.
2nd, the centralized solution that the present invention is used, by using BC+TC patterns inside device systems, solves message and exists
The message transmissions delay variation problem that main control unit is beaten between timestamp position and line card panel terminal port, it is ensured that 1588 time synchronizeds
The validity that protocol algorithm is run on main control unit.
3rd, line card carries out special measurement processing to the delay between main control unit, is accumulated in the absence of the synchronization accuracy between board,
Greatly improve synchronization accuracy.
4th, only in main control unit processing in reversed process, in the absence of the coordination between board, it is small to switch risk, reduces synchronizing signal
Interference；And all line card one directions are synchronized to main control unit, and backboard wiring is simple.
5th, time source information exists only in main control unit, and time source information externally embodies unique.
Brief description of the drawings
Fig. 1 is the centralized approach flow chart that 1588 time synchronizeds are realized in distributed system of the embodiment of the present invention；
Fig. 2 is the embodiment of the present invention with main control unit in node and the schematic diagram of line card；
Fig. 3 is the processing schematic diagram of the centralized timestamp of the embodiment of the present invention.
It is explained as follows in order to make it easy to understand, letter of the present invention represents implication：
t1：Master clock node main control unit sends timestamp；
t1'：At the time of master clock node line card sends sync message；
t2：Timestamp is received from clock node main control unit；
t2'：Timestamp is received from clock node line card；
t3：Timestamp is sent from clock node main control unit；
t3'：At the time of time delay request message being sent from clock node line card；
t4：Master clock node main control unit receives timestamp；
t4'：Timestamp is received in the clamping of master clock nodal line；
CFsync：The correction time delay value of the whole transmission path of sync message；
CFdelayresp：The correction time delay value of the whole transmission path of time delay request message.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
The centralized approach of 1588 time synchronizeds is realized in distributed system of the present invention, it is adaptable to include main control unit and line card
The big-and-middle-sized equipment constituted Deng polylith board, or line card integrate the mini-plant of one, each equipment with main control unit function
A node of whole network is can be seen as, as shown in Fig. 2 each node includes main control unit and multiple line cards, main control unit
Need to support PTP protocol and BMC algorithms, each line card needs to support the timestamp processing mode of TC patterns, line card one direction all the time
It is synchronized with main control unit.1588 protocol massages are transmitted according to stipulated form between disk between main control unit and line card, such as are drawn by VLAN
Grade, stipulated form includes packet sending and receiving rule and message format definition between disk, for ensureing that message can accurately be toward predetermined end
Mouth is sent, while also can correctly be recognized to message sink mouthful.
As shown in figure 1, the present invention specifically includes following steps：
S1. by the configuration interface of distributed system, PTP is run on the main control unit of the node of 1588 functions of all supports
Agreement and BMC algorithms, 1588 working conditions (Master states, the Slave shapes of each line card port can be calculated in whole network
State, Passive states or Disabled states).The line cards of 1588 messages of transmission in need complete related channel program configuration and same
Step processing configuration, configuration includes playing the processing of timestamp, the calculating and more of correction field (i.e. correctionField fields) value
Newly, message format conversion etc..
S2. as shown in figure 3, master clock node sends sync message (i.e. sync messages), master clock node main control unit is carried
Timestamp t1 (hereinafter referred to as t1) and correction field, the value CF=t1'-t1 of the correction field of carrying are sent, wherein t1' is
At the time of sync message being sent with node line card.
Specifically, the main control unit of master clock node sends synchronous report toward the line card containing master status ports in same node
Text, beats t1 on main control unit, with the message format of agreement, is sent to correspondence line card in same node.Wherein, One-step patterns
When, t1 is inserted into sync message, the value T1 of message exit port timestamp (originTimestamp) field of sync message
=t1, the value for now correcting field is 0.
Correspondence line card is received after the sync message of this node main control unit, extracts t1；T1' at the time of sync message is sent,
Calculate t1'-t1 values, be filled up in the correction field of sync message, i.e., now CF=t1'-t1.
S3. the sync message is received from clock node, stamps from clock node line card and receive timestamp t2' and from clock
Node main control unit receives timestamp t2, and calculates the correction time delay value CF of the whole transmission path of sync messagesync。
Specifically, the line card containing slave status ports from clock node receives sync message, t2' is stamped, t2' is used
In sync message path transmission time delay amendment.Send same to same node main control unit from clock node line card by stipulated form between disk
Walk message, T1=t1, the CF=t1'-t1 of sync message, while t2' to be inserted into the position arranged in sync message.With section
The main control unit of point is received after sync message, stamps t2, and acquisition t1, t2' and t1'-t1 from sync message, and then calculate same
Walk the correction time delay value CF of the whole path transmission of messagesync, CFsync=(t2-t2')+(t1'-t1).
S4. from clock node transmission delay request message (i.e. delay_req messages), carry from clock node main control unit hair
The value t3'-t3 of timestamp t3 and correction field is sent, wherein t3' is at the time of sending time delay request message with node line card.
Specifically, please toward the line card transmission delay containing slave status ports in same node from the main control unit of clock node
Message is sought, t3 is stamped in main control unit.Time delay request message is received with correspondence line card on node and extracts t3, in time delay request message
T3' at the time of sending, calculates t3'-t3 value, is added in the correction field of time delay request message, and time delay is asked into report
Text is sent by the port of agreement.
S5. master clock node receives the time delay request message, stamps the clamping of master clock nodal line and receives timestamp t4' and master
Clock node main control unit receives timestamp t4, the correction time delay value CF of the whole transmission path of calculation delay request messagedelayresp。
Specifically, the line card containing master status ports in master clock node receives time delay request message, t4' hairs are stamped
To same node main control unit, t4 is stamped with node main control unit, t3'-t3 and t4' is obtained from time delay request message, calculation delay please
Seek the correction time delay value CF of the whole path transmission of messagedelayresp, CFdelayresp=(t4-t4')+(t3'-t3).
S6. t4 and (t4-t4')+(t3'-t3) are inserted into DELAY RESPONSE message (i.e. by the main control unit of master clock node
Delay_resp messages) in, issue from clock node；Receive after DELAY RESPONSE message, find pair from the main control unit of clock node
The time delay request message answered, obtains all timestamps and two correction time delay values, specially t1, t2, t3, t4, (t2-t2')+
(t1'-t1) and (t4-t4')+(t3'-t3), formula is passed through from clock node main control unit
Calculate and master clock node time source time synchronized deviation offset, complete from clock node relative to it is main when
The time synchronized adjustment of clock node.
In above-mentioned steps, in order to keep the validity of propagation delay time, therefore each timestamp to ensure to come from it is same
Fiducial time, that is, need to ensure the time synchronized of line card and main control unit.
The present invention is not limited to the above-described embodiments, for those skilled in the art, is not departing from
On the premise of the principle of the invention, some improvements and modifications can also be made, these improvements and modifications are also considered as the protection of the present invention
Within the scope of.The content not being described in detail in this specification belongs to prior art known to professional and technical personnel in the field.
Claims (10)
1. the centralized approach of 1588 time synchronizeds is realized in a kind of distributed system, it is characterised in that including step：
S1. by configuring interface, operation PTP protocol and BMC algorithms on the main control unit of 1588 functional nodes of all supports are calculated
1588 working conditions of each line card port, it is in need transmission 1588 messages line card complete related channel program configuration and synchronization process
Configuration；
S2. master clock node sends sync message, carries the value that master clock node main control unit sends timestamp t1 and correction field
T1'-t1, wherein t1' is at the time of sending sync message with node line card；
S3. the sync message is received from clock node, stamps from clock node line card and receive timestamp t2' and from clock node
Main control unit receives timestamp t2, and calculates correction time delay value (t2-t2')+(t1'-t1) of the whole transmission path of sync message；
S4. from clock node transmission delay request message, carry from clock node main control unit and send timestamp t3 and correction field
Value t3'-t3, wherein t3' for send time delay request message with node line card at the time of；
S5. master clock node receives the time delay request message, stamps the clamping of master clock nodal line and receives timestamp t4' and master clock
Node main control unit receives timestamp t4, and the correction time delay value (t4-t4') of the whole transmission path of calculation delay request message+
(t3'-t3)；
S6. t4 and (t4-t4')+(t3'-t3) are inserted into DELAY RESPONSE message by the main control unit of master clock node, issue from when
Clock node；Received from the main control unit of clock node after DELAY RESPONSE message, find corresponding time delay request message, obtain institute sometimes
Between stamp and two correction time delay values；It is synchronous with the node main control unit passage time synchronized algorithm deadline.
2. the centralized approach of 1588 time synchronizeds is realized in distributed system as claimed in claim 1, it is characterised in that：Institute
State in S2, the main control unit of master clock node sends sync message toward the line card containing master status ports in same node；Correspondence
Line card, which is received, extracts t1 after sync message, t1' at the time of sync message is sent calculates t1'-t1 values, and be filled up to synchronization
In the correction field of message.
3. the centralized approach of 1588 time synchronizeds is realized in distributed system as claimed in claim 2, it is characterised in that：Institute
The sync message that main control unit issues same node line card is stated, wherein, the value of message exit port timestamp field is t1, now corrects word
The value of section is 0.
4. the centralized approach of 1588 time synchronizeds is realized in distributed system as claimed in claim 1, it is characterised in that：Institute
State in S3, the line card containing slave status ports from clock node receives sync message, stamps for propagation delay time amendment
T2', is sent to same node main control unit, is received with node main control unit after sync message, stamps t2, and obtained from sync message
T1, t2' and t1'-t1, calculate (t2-t2')+(t1'-t1).
5. the centralized approach of 1588 time synchronizeds is realized in distributed system as claimed in claim 4, it is characterised in that：From
Clock node line card sends sync message, its message exit port timestamp field by stipulated form between disk to same node main control unit
Value be t1, correction field value is t1'-t1, and t2' is inserted into the position arranged in sync message.
6. the centralized approach of 1588 time synchronizeds is realized in distributed system as claimed in claim 1, it is characterised in that：Institute
State in S4, from the main control unit of clock node toward the line card transmission delay request message containing slave status ports in same node；It is right
Line card is answered to extract t3 after receiving time delay request message, t3' at the time of time delay request message is sent calculates t3'-t3's
Value, and be filled up in the correction field of time delay request message.
7. the centralized approach of 1588 time synchronizeds is realized in distributed system as claimed in claim 1, it is characterised in that：Institute
State in S5, the line card containing master status ports in master clock node receives time delay request message, stamp t4' and issue same node
Main control unit, t4 is stamped in same node main control unit, and extracts t3'-t3 and t4', calculates (t4-t4')+(t3'-t3).
8. the centralized approach of 1588 time synchronizeds is realized in distributed system as claimed in claim 1, it is characterised in that：Institute
State in S6, formula is passed through from the main control unit of clock node
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Calculate and master clock node time source time synchronized deviation offset, wherein CFsync=(t2-t2')+(t1'-
T1), it is the correction time delay value of the whole transmission path of sync message；CFdelayresp=(t4-t4')+(t3'-t3), is employed when being
Seek the correction time delay value of the whole transmission path of message.
9. the centralized approach of 1588 time synchronizeds, its feature are realized in the distributed system as described in claim 1-8 is any
It is：Main timing node and from timing node include main control unit and multiple line cards, between the main control unit and line card of node, press
Stipulated form between 1588 protocol massages, disk is transmitted according to stipulated form between disk disk including packet sending and receiving rule and message format to determine
Justice.
10. the centralized approach of 1588 time synchronizeds, its feature are realized in the distributed system as described in claim 1-8 is any
It is：Each timestamp is same fiducial time.
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