CN114745774A - Centralized time synchronization method, device, equipment and readable storage medium - Google Patents
Centralized time synchronization method, device, equipment and readable storage medium Download PDFInfo
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Abstract
The application relates to a centralized time synchronization method, a device, equipment and a readable storage medium, which relate to the technical field of time synchronization, wherein a master clock equipment line card and a slave clock equipment line card are used for stamping a synchronous message and a time delay request message, the residence time in the equipment is calculated according to the time stamp stamped by the line card, a correction domain is calculated based on the time stamp stamped by the line card and the residence time in the equipment, and time synchronization adjustment can be carried out according to the time stamp stamped by the correction domain and the line card; the residence time in the line card refers to the residence time in the line card, namely, the residence time can be calculated on one line card, and clocks used in the same line card can be strictly synchronized easily, so that the difficulty of time synchronization is reduced, and the precision of time synchronization is improved; and the calculated residence time on the same board card is shorter than the paths passed by the residence times on different board cards, and the calculated residence time is less interfered and uncertain, so that the time synchronization performance is favorably improved.
Description
Technical Field
The present application relates to the field of time synchronization technologies, and in particular, to a centralized time synchronization method, apparatus, device, and readable storage medium.
Background
The time synchronization technology is mainly used for time synchronization among communication devices, wherein the high-precision centralized time synchronization technology based on the 1588V2 protocol can meet the requirement of the traditional 4G device (the single station of the device only needs +/-30 ns in precision) on time synchronization; however, for the SPN (Slicing Packet Network) device applied to 5G, since the Packet transmission Network needs all nodes to support PTP (Precision Time Protocol), and the networking is complex, and congestion, delay, jitter, and Packet loss of the Network all affect the clock accuracy, it needs to support ultra-high Precision Time synchronization, that is, its Time synchronization dedicated interface needs to meet the index of single station Precision ± 5ns, such as GE (Gigabit Ethernet, Gigabit Ethernet interface) interface and Flexe interface; therefore, the SPN device for 5G applications puts higher requirements on the accuracy of time synchronization, and the conventional 1588V2 time synchronization technology cannot meet the time synchronization requirements of 5G applications, so that further optimization of the current centralized time synchronization scheme is required.
In the related art, the time deviation between a master clock and a slave clock is calculated based on the residence time in equipment, and the time synchronization is realized according to the time deviation adjustment; however, in the conventional scheme, the residence time in the device refers to the residence time between the main control card and the line card (i.e., the residence time between different board cards), and it needs to stamp a timestamp on the main control card (when sending the synchronization packet) and the line card (when receiving the synchronization packet), and then calculates the difference between the two timestamps, and updates the difference as the residence time in the device into the correction domain CF; however, since there is a time delay between the main control card and the line card, if it is desired to obtain an accurate residence time, it is necessary to equalize the time delays of the uplink and downlink, that is, it is necessary to strictly synchronize the real-time on the main control card and the real-time on the line card to ensure a high accuracy, otherwise, it is necessary to perform manual calibration, and this implementation process is very complicated and difficult, so that the accuracy of time synchronization is low.
Disclosure of Invention
The application provides a centralized time synchronization method, a centralized time synchronization device, a centralized time synchronization equipment and a readable storage medium, so as to solve the problems of large difficulty and low precision of time synchronization caused by applying the traditional 1588V2 time synchronization technology to 5G equipment in the related art.
In a first aspect, a centralized time synchronization method is provided, which includes the following steps:
a PTP message processing unit of a line card of a main clock device stamps t1 on a synchronous message when receiving the synchronous message, and a service processing unit of the line card of the main clock device stamps t 1' on the synchronous message when receiving the synchronous message;
when receiving a synchronous message, a service processing unit of a slave clock equipment line card stamps t2 ' for the synchronous message, when receiving the synchronous message, a PTP message processing unit of the slave clock equipment line card stamps t2 for the synchronous message, calculates a current correction domain CF1 based on the time stamps t1, t1 ', t2 ' and t2, updates the correction domain CF1 into the synchronous message, and sends the synchronous message to the PTP message processing unit of a slave clock equipment main control card;
when receiving a delay request message, a PTP message processing unit of a slave clock equipment line card stamps t3 on the delay request message, and when receiving the delay request message, a service processing unit of the slave clock equipment line card stamps t 3' on the delay request message;
the method comprises the steps that when a service processing unit of a main clock equipment line card receives a delay request message, a timestamp t4 ' is marked on the delay request message, when a PTP message processing unit of the main clock equipment line card receives the delay request message, a timestamp t4 is marked on the delay request message, a current correction domain CF2 is obtained through calculation based on the timestamp t3, the timestamp t3 ', the timestamp t4 ' and the timestamp t4, the timestamp t4 and the correction domain CF2 are sent to the PTP message processing unit of a main clock equipment main control card, the PTP message processing unit of the main clock equipment main control card inserts the timestamp t4 and the correction domain CF2 into a delay response message, and the delay response message is sent to the PTP message processing unit of a slave clock equipment main control card;
and after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock equipment main control card, performing time synchronization adjustment based on the time stamp t1, the time stamp t2, the time stamp t3, the time stamp t4, the correction domain CF1 and the correction domain CF 2.
In some embodiments, before the step of receiving the synchronization message, the PTP message processing unit of the line card of the master clock device further includes:
a real-time processing unit of a master control card of the master clock equipment sends reference real-time to a real-time processing unit of a line card of the master clock equipment;
a real-time processing unit of the line card of the master clock equipment carries out synchronous calibration of real-time based on the reference real-time to obtain first real-time;
and the real-time processing unit of the line card of the master clock equipment respectively sends the first real-time to the PTP message processing unit of the line card of the master clock equipment and the service processing unit of the line card of the master clock equipment.
In some embodiments, when receiving the synchronization packet, the PTP packet processing unit of the line card of the master clock device stamps t1 on the synchronization packet, and when receiving the synchronization packet, the service processing unit of the line card of the master clock device stamps t 1' on the synchronization packet, including:
when a PTP message processing unit of a line card of a master clock device receives a synchronous message, a timestamp t1 is marked for the synchronous message based on the first real-time;
when a service processing unit of a line card of main clock equipment receives a synchronous message, a timestamp t 1' is marked for the synchronous message based on the first real-time.
In some embodiments, when receiving the delay request message, the service processing unit of the line card of the master clock device stamps a timestamp t 4' on the delay request message, and when receiving the delay request message, the PTP message processing unit of the line card of the master clock device stamps a timestamp t4 on the delay request message, including:
when a service processing unit of a line card of main clock equipment receives a time delay request message, a timestamp t 4' is marked for the time delay request message based on the first real-time;
when receiving a delay request message, a PTP message processing unit of a line card of a master clock device stamps t4 on the delay request message based on the first real-time.
In some embodiments, after receiving the synchronization packet and the delay response packet, the PTP packet processing unit of the slave clock device master card performs time synchronization adjustment based on the timestamp t1, the timestamp t2, the timestamp t3, the timestamp t4, the correction domain CF1, and the correction domain CF2, including:
after receiving the synchronization message and the delay response message, the PTP message processing unit of the slave clock device main control card finds a delay request message corresponding to the delay response message, and obtains a timestamp t1, a timestamp t2, a timestamp t3, a timestamp t4, a correction domain CF1, and a correction domain CF 2;
the PTP message processing unit of the master control card of the slave clock equipment calculates the synchronous time offset between the slave clock equipment and the master clock equipment according to the following formula:
in a second aspect, a centralized time synchronization apparatus is provided, including: the master clock equipment line card, the slave clock equipment master control card and the slave clock equipment line card all comprise PTP message processing units, and the master clock equipment line card and the slave clock equipment line card all comprise service processing units;
the PTP message processing unit of the line card of the main clock equipment stamps t1 on the synchronous message when receiving the synchronous message, and the service processing unit of the line card of the main clock equipment stamps t 1' on the synchronous message when receiving the synchronous message;
when receiving a synchronous message, a service processing unit of a slave clock equipment line card stamps t2 ' for the synchronous message, when receiving the synchronous message, a PTP message processing unit of the slave clock equipment line card stamps t2 for the synchronous message, calculates a current correction domain CF1 based on the time stamps t1, t1 ', t2 ' and t2, updates the correction domain CF1 into the synchronous message, and sends the synchronous message to the PTP message processing unit of a slave clock equipment main control card;
the method comprises the steps that when a PTP message processing unit of a slave clock equipment line card receives a time delay request message, a time stamp t3 is marked on the time delay request message, and when a service processing unit of the slave clock equipment line card receives the time delay request message, a time stamp t 3' is marked on the time delay request message;
when receiving a delay request message, a service processing unit of a line card of a master clock device stamps a time stamp t4 ' for the delay request message, when receiving the delay request message, a PTP message processing unit of the line card of the master clock device stamps a time stamp t4 for the delay request message, and calculates a current correction domain CF2(CF2 ═ t3 ' -t3+ t4-t4 ') based on the time stamp t3, the time stamp t3 ', the time stamp t4 ' and the time stamp t4, and sends the time stamp t4 and the correction domain CF2 to a PTP message processing unit of a master control card of the master clock device, and the PTP message processing unit of the master control card of the master clock device inserts the time stamp t4 and the correction domain CF2 into a delay response message and sends the delay response message to a PTP message processing unit of a master control card of a slave clock device;
and after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock equipment main control card, performing time synchronization adjustment based on the time stamp t1, the time stamp t2, the time stamp t3, the time stamp t4, the correction domain CF1 and the correction domain CF 2.
In some embodiments, the master clock device master card and the master clock device line card each further include a real-time processing unit, where:
a real-time processing unit of a master control card of the master clock equipment sends reference real-time to a real-time processing unit of a line card of the master clock equipment;
a real-time processing unit of the line card of the master clock equipment carries out synchronous calibration of real-time based on the reference real-time to obtain first real-time;
and the real-time processing unit of the line card of the master clock equipment respectively sends the first real-time to the PTP message processing unit of the line card of the master clock equipment and the service processing unit of the line card of the master clock equipment.
In some embodiments, the PTP message processing unit of the slave clock device master control card is specifically configured to:
after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock device master control card, finding a delay request message corresponding to the delay response message, and obtaining a timestamp t1, a timestamp t2, a timestamp t3, a timestamp t4, a correction domain CF1, and a correction domain CF 2;
the PTP message processing unit of the master control card of the slave clock equipment calculates the synchronous time offset between the slave clock equipment and the master clock equipment according to the following formula:
in a third aspect, a centralized time synchronization apparatus is provided, including: the device comprises a memory and a processor, wherein at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processor to realize the centralized time synchronization method.
In a fourth aspect, a computer-readable storage medium is provided, which stores computer instructions that, when executed by a computer, cause the computer to perform the aforementioned centralized time synchronization method.
The technical scheme who provides this application brings beneficial effect includes: the difficulty of time synchronization can be effectively reduced and the precision of time synchronization is improved.
The application provides a centralized time synchronization method, a device, equipment and a readable storage medium, wherein a master clock equipment line card and a slave clock equipment line card are used for stamping a synchronization message and a time delay request message, the time stamp of the line card is used for calculating the residence time in the equipment, a correction domain is calculated based on the time stamp of the line card and the residence time in the equipment, and finally, the time synchronization adjustment can be carried out according to the time stamp of the correction domain and the line card; because the residence time in the line card refers to the residence time in the line card, the residence time can be calculated only by stamping the message by the PTP message processing unit and the service processing unit in the line card, namely, the residence time can be calculated on one board card without stamping the message by the main control card, and the clocks used in the same board card can be strictly synchronized easily, thereby reducing the difficulty of time synchronization and improving the precision of time synchronization; meanwhile, the calculated residence time on the same board card is shorter than the paths passed by the residence times on different board cards, and the interference and uncertainty are less, so that the time synchronization performance is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a centralized time synchronization method according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating transmission and timestamp processing of a synchronization packet according to an embodiment of the present application;
fig. 3 is a schematic diagram illustrating transmission and timestamp processing of a delay request packet and a delay response packet according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a centralized time synchronization device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a centralized time synchronization method, a centralized time synchronization device, a centralized time synchronization equipment and a readable storage medium, which can solve the problems of large difficulty and low precision of time synchronization caused by applying the traditional 1588V2 time synchronization technology to 5G equipment in the related technology.
Referring to fig. 1, an embodiment of the present application provides a centralized time synchronization method, which specifically includes the following steps
Step S10: when receiving the synchronization message, the PTP message processing unit of the main clock equipment line card stamps t1 on the synchronization message, and when receiving the synchronization message, the service processing unit of the main clock equipment line card stamps t 1' on the synchronization message;
exemplarily, in this embodiment, referring to fig. 2, a PTP message processing unit of a master card of a master clock device sends a synchronization message (a self-defined frame header is added to the synchronization message) to a PTP message processing unit of a line card of the master clock device, at this time, since the PTP message processing unit of the master card of the master clock device is not required to stamp the synchronization message, a timestamp field of t1 may be filled with 0, and a CF field may be configured by software to fill a real-time offset compensation value, which is temporarily filled with 0 at this stage;
when a PTP message processing unit of a line card of a master clock device receives a synchronous message, format adaptation processing is carried out on the synchronous message according to software configuration, a timestamp t1 is sent, the timestamp t1 is updated to a t1 timestamp field of the synchronous message, and then the synchronous message is sent to a service processing unit (namely a Framer) of the line card of the master clock device; when receiving the synchronization message, the service processing unit of the line card of the master clock device stamps t1 'on the synchronization message, calculates the residence time as (t 1' -t1), and adds the residence time to the CF domain field, such as: assuming that a CF domain of a synchronization message on a transmission path is CF1, and CF1 of a PTP message processing unit from a master control card of a master clock device is 0, when the synchronization message goes out of a line card of the master clock device, a correction domain CF1 is t 1' -t 1; and then the synchronous message is transmitted to a service processing unit of a slave clock equipment line card through a PTP port in a standard packaging format.
Step S20: when receiving a synchronous message, a service processing unit of a slave clock equipment line card stamps t2 ' for the synchronous message, when receiving the synchronous message, a PTP message processing unit of the slave clock equipment line card stamps t2 for the synchronous message, calculates a current correction domain CF1 based on the time stamps t1, t1 ', t2 ' and t2, updates the correction domain CF1 into the synchronous message, and sends the synchronous message to the PTP message processing unit of a slave clock equipment main control card;
exemplarily, in this embodiment, referring to fig. 2, after receiving a synchronization message and marking a receiving timestamp t 2' for the synchronization message, a service processing unit (i.e., Framer) of a slave clock line card transmits the synchronization message to a PTP message processing unit of the slave clock line card; when receiving the synchronous message, a PTP message processing unit of the slave clock equipment line card stamps t2 for the synchronous message, calculates the residence time to be (t2-t2 '), adds the residence time to a CF domain field, calculates a current correction domain CF1 to be t 1' -t1+ t2-t2 'based on a correction domain CF1 to be t 1' -t1 extracted from the synchronous message, and sends the synchronous message to a PTP message processing unit of the slave clock equipment master control card; and extracting the time stamp t1, the time stamp t2 and the current correction domain CF1 from a PTP message processing unit of the clock equipment master control card for adjusting time synchronization.
Step S30: the method comprises the steps that when a PTP message processing unit of a slave clock equipment line card receives a time delay request message, a time stamp t3 is marked on the time delay request message, and when a service processing unit of the slave clock equipment line card receives the time delay request message, a time stamp t 3' is marked on the time delay request message;
exemplarily, in this embodiment, referring to fig. 3, a PTP message processing unit of a master card of a slave clock device sends a delay request message (a self-defined frame header is added to the delay request message) to a PTP message processing unit of a line card of the slave clock device, at this time, since the PTP message processing unit of the master card of the slave clock device does not need to stamp the delay request message, a timestamp field of t3 may be filled with 0, a CF field may be filled with a real-time offset compensation value through software configuration, and is temporarily filled with 0 at this stage;
when receiving a delay request message, a PTP message processing unit of a slave clock device line card performs format adaptation processing on the delay request message according to software configuration, and sends a timestamp t3, updates the timestamp t3 to a timestamp t3 field of the delay request message, and then sends the delay request message to a service processing unit (i.e., Framer) of the slave clock device line card, it should be noted that the delay request message with the timestamp t3 may also be directly transmitted back to a PTP processing unit of a slave clock device master control card, so that the PTP message processing unit of the slave clock device master control card directly obtains a timestamp t3, that is, it supports returning a timestamp t3 based on a PTP message transmission mechanism in the same device, therefore, whether the timestamp t3 is updated to the timestamp t3 timestamp field of the delay request message is optional, and can be determined according to actual needs;
when receiving the delay request message, the service processing unit of the slave clock device line card stamps a timestamp t3 ' for the delay request message, calculates the residence time to be (t3 ' -t3), and adds the residence time to a CF domain field, for example, the CF domain of the delay request message on the transmission path is CF2, and CF2 from the PTP message processing unit of the slave clock device master control card is 0, when the delay request message comes out of the slave clock device line card, the correction domain CF2 is t3 ' -t 3; and then transmitting the time delay request message to a service processing unit of a line card of the master clock equipment through a PTP port in a standard packaging format.
Step S40: when receiving a delay request message, a service processing unit of a line card of a master clock device stamps t4 ' on the delay request message, when receiving the delay request message, a PTP message processing unit of the line card of the master clock device stamps t4 on the delay request message, calculates a current correction domain CF2 based on the timestamp t3, the timestamp t3 ', the timestamp t4 ' and the timestamp t4, and sends the timestamp t4 and the correction domain CF2 to a PTP message processing unit of a master control card of the master clock device, wherein the PTP message processing unit of the master control card of the master clock device inserts the timestamp t4 and the correction domain CF2 into a delay response message and sends the delay response message to a PTP message processing unit of a master control card of a slave clock device;
exemplarily, in this embodiment, referring to fig. 4, after receiving a delay request message and stamping a receiving timestamp t 4' for the delay request message, a service processing unit (i.e., Framer) of a line card of a master clock device transmits the delay request message to a PTP message processing unit of the line card of the master clock device; when receiving the delay request message, the PTP message processing unit of the master clock device line card timestamps t4 for the delay request message, calculates the residence time to be (t4-t4 '), adds the residence time to the CF domain field, calculates the current correction domain CF2 (t 3' -t3+ t4-t4 ') based on the CF2 (t 3' -t3) extracted from the delay request message, and sends the delay request message to the PTP message processing unit of the master clock device master card;
after receiving the delay request message, the PTP message processing unit of the master control card of the master clock device generates a delay response message, and correspondingly fills a timestamp t4 and a correction domain CF2 in a t4 timestamp field and a CF domain field of the delay response message respectively; after format adaptation is carried out on the delay response message by a PTP message processing unit of the line card of the main clock equipment, the delay response message is sequentially sent to the PTP message processing unit and a service processing unit of the line card of the main clock equipment, and then sent to a PTP port by the service processing unit of the line card of the main clock equipment; the service processing unit of the slave clock equipment line card receives and transmits the delay response message to the PTP message processing unit of the slave clock equipment line card based on the PTP port; after the PTP message processing unit of the slave clock equipment line card performs format adaptation on the delay response message, the delay response message is transmitted to the PTP message processing unit of the slave clock equipment main control card.
The service processing unit needs to be time-stamped by t1 ', t 2', t3 'and t 4' in a TC mode, calculates the residence time in the equipment in the sending direction (sent to a circuit PTP interface) and updates a CF domain field; however, in the BC mode, the service processing unit only needs to directly time stamp t1, time stamp t2, time stamp t3, and time stamp t 4. Therefore, the method and the device support TC mode and BC mode processing in the equipment, and for the business processing chip supporting ultra-high precision, BC mode processing can be directly adopted, namely the chip is used for stamping, so that errors caused by residence time in the computing equipment are avoided, and the precision of time synchronization is improved.
Step S50: and after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock equipment main control card, performing time synchronization adjustment based on the time stamp t1, the time stamp t2, the time stamp t3, the time stamp t4, the correction domain CF1 and the correction domain CF 2.
Exemplarily, in this embodiment, after receiving the delay response message from the PTP message processing unit of the clock device main control card, the delay request message and the delay response message are matched according to the serial number, and if the serial numbers are consistent, the timestamp t3, the timestamp t4, and the correction domain CF2 are extracted; the PTP message processing unit of the master control card of the slave clock equipment calculates the synchronous time offset between the slave clock equipment and the master clock equipment according to the following formula:
and performs time synchronization adjustment according to the synchronization time offset.
Therefore, according to the method, a master clock equipment line card and a slave clock equipment line card are used for stamping the synchronous message and the delay request message, the time stamp of the line card is used for calculating the residence time in the equipment, a correction domain is calculated based on the time stamp of the line card and the residence time in the equipment, and finally the time synchronization adjustment can be carried out according to the time stamp of the correction domain and the line card, wherein the generation and the recovery of the time stamp are only processed on the line card supporting PTP interfaces (including various traditional Ethernet interfaces such as GE optical interface, 10GE, 40GE, 50GE and 100 GE); because the residence time in the line card refers to the residence time in the line card, the residence time can be calculated only by stamping the message by the PTP message processing unit and the service processing unit in the line card, namely, the residence time can be calculated on one board card without stamping the message by the main control card, and the clocks used in the same board card can be strictly synchronized easily, thereby reducing the difficulty of time synchronization and improving the precision of time synchronization; meanwhile, the calculated residence time on the same board card is shorter than the paths passed by the residence times on different board cards, and the interference and uncertainty are less, so that the time synchronization performance is improved.
Further, in this embodiment of the present application, before the step of receiving the synchronization packet, the PTP packet processing unit of the line card of the master clock device further includes the following steps: a real-time processing unit of a master control card of the master clock equipment sends reference real-time to a real-time processing unit of a line card of the master clock equipment; a real-time processing unit of the line card of the master clock equipment carries out synchronous calibration of real-time based on the reference real-time to obtain first real-time; and the real-time processing unit of the line card of the master clock equipment respectively sends the first real-time to the PTP message processing unit of the line card of the master clock equipment and the service processing unit of the line card of the master clock equipment.
Exemplarily, in this embodiment, when receiving a synchronization packet, a PTP packet processing unit of a line card of a master clock device stamps a timestamp t1 on the synchronization packet based on the first real-time; when a service processing unit of a line card of main clock equipment receives a synchronous message, a timestamp t 1' is marked for the synchronous message based on the first real-time; when a service processing unit of a line card of main clock equipment receives a time delay request message, a timestamp t 4' is marked on the time delay request message based on the first real-time; and when receiving the delay request message, the PTP message processing unit of the line card of the master clock device stamps a timestamp t4 on the delay request message based on the first real-time. When the PTP message processing unit and the service processing unit of the line card of the main clock equipment perform stamping actions, stamping is completed through real-time obtained by calibrating the real-time based on the reference real-time generated by the real-time processing unit of the main clock equipment main control card by the real-time processing unit in the line card of the main clock equipment, and real-time obtained by calibrating the reference real-time generated by the real-time processing unit of the main clock equipment main control card is effectively ensured, so that the stamping time accuracy of the PTP message processing unit and the service processing unit of the line card of the main clock equipment is effectively ensured. It should be noted that the time synchronization principle of the slave clock device line card is similar to that of the master clock device line card, and is not described herein again.
The embodiment of the present application further provides a centralized time synchronization apparatus, including: the main clock equipment line card, the slave clock equipment main control card and the slave clock equipment line card respectively comprise PTP message processing units, and the main clock equipment line card and the slave clock equipment line card respectively comprise service processing units;
the PTP message processing unit of the line card of the main clock equipment stamps t1 on the synchronous message when receiving the synchronous message, and the service processing unit of the line card of the main clock equipment stamps t 1' on the synchronous message when receiving the synchronous message;
when receiving a synchronous message, a service processing unit of a slave clock equipment line card stamps t2 ' for the synchronous message, when receiving the synchronous message, a PTP message processing unit of the slave clock equipment line card stamps t2 for the synchronous message, calculates a current correction domain CF1 based on the time stamps t1, t1 ', t2 ' and t2, updates the correction domain CF1 into the synchronous message, and sends the synchronous message to the PTP message processing unit of a slave clock equipment main control card;
when receiving a delay request message, a PTP message processing unit of a slave clock equipment line card stamps t3 on the delay request message, and when receiving the delay request message, a service processing unit of the slave clock equipment line card stamps t 3' on the delay request message;
when receiving a delay request message, a service processing unit of a line card of a master clock device stamps t4 ' on the delay request message, when receiving the delay request message, a PTP message processing unit of the line card of the master clock device stamps t4 on the delay request message, calculates a current correction domain CF2 based on the timestamp t3, the timestamp t3 ', the timestamp t4 ' and the timestamp t4, and sends the timestamp t4 and the correction domain CF2 to a PTP message processing unit of a master control card of the master clock device, wherein the PTP message processing unit of the master control card of the master clock device inserts the timestamp t4 and the correction domain CF2 into a delay response message and sends the delay response message to a PTP message processing unit of a master control card of a slave clock device;
and after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock equipment main control card, performing time synchronization adjustment based on the time stamp t1, the time stamp t2, the time stamp t3, the time stamp t4, the correction domain CF1 and the correction domain CF 2.
Furthermore, in this embodiment, each of the master control card of the master clock device and the line card of the master clock device further includes a real-time processing unit, where:
a real-time processing unit of a master control card of the master clock equipment sends reference real-time to a real-time processing unit of a line card of the master clock equipment;
a real-time processing unit of the line card of the master clock equipment carries out synchronous calibration of real-time based on the reference real-time to obtain first real-time;
and the real-time processing unit of the line card of the master clock equipment respectively sends the first real-time to the PTP message processing unit of the line card of the master clock equipment and the service processing unit of the line card of the master clock equipment.
Furthermore, in this embodiment of the present application, when receiving a synchronization packet, a PTP packet processing unit of a line card of a master clock device stamps t1 on the synchronization packet based on the first real-time; when a service processing unit of a line card of main clock equipment receives a synchronous message, a timestamp t 1' is marked for the synchronous message based on the first real-time.
Furthermore, in this embodiment of the present application, when receiving a delay request packet, a service processing unit of a line card of a master clock device stamps t 4' on the delay request packet based on the first real-time; when receiving a delay request message, a PTP message processing unit of a line card of a master clock device stamps t4 on the delay request message based on the first real-time.
Further, in this embodiment of the present application, the PTP message processing unit of the slave clock device master control card is specifically configured to:
after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock device master control card, finding a delay request message corresponding to the delay response message, and obtaining a timestamp t1, a timestamp t2, a timestamp t3, a timestamp t4, a correction field CF1, and a correction field CF 2;
the PTP message processing unit of the master control card of the slave clock equipment calculates the synchronous time offset between the slave clock equipment and the master clock equipment according to the following formula:
it should be noted that, as is clear to those skilled in the art, for convenience and brevity of description, the specific working processes of the apparatus and the units described above may refer to the corresponding processes in the foregoing embodiment of the centralized time synchronization method, and are not described herein again.
The apparatus provided by the above embodiments can be implemented in the form of a computer program, which can run on a centralized time synchronization device as shown in fig. 4.
An embodiment of the present application further provides a centralized time synchronization device, including: the system comprises a memory, a processor and a network interface which are connected through a system bus, wherein at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processor so as to realize all or part of the steps of the centralized time synchronization method.
The network interface is used for performing network communication, such as sending distributed tasks. Those skilled in the art will appreciate that the architecture shown in fig. 4 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
The Processor may be a CPU, other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable Gate Array (FPGA) or other programmable logic device, discrete Gate or transistor logic device, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the computer device and the various interfaces and lines connecting the various parts of the overall computer device.
The memory may be used to store computer programs and/or modules, and the processor may implement various functions of the computer device by executing or executing the computer programs and/or modules stored in the memory, as well as by invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a video playing function, an image playing function, etc.), and the like; the storage data area may store data (such as video data, image data, etc.) created according to the use of the cellular phone, etc. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
Embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements all or part of the steps of the foregoing centralized time synchronization method.
The embodiments of the present application may implement all or part of the foregoing processes, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of the foregoing methods. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer memory, Read-Only memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunication signals, software distribution medium, etc., capable of carrying computer program code. It should be noted that the computer-readable medium may contain suitable additions or subtractions depending on the requirements of legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer-readable media may not include electrical carrier signals or telecommunication signals in accordance with legislation and patent practice.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, server, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A centralized time synchronization method, comprising the steps of:
a PTP message processing unit of a line card of a main clock device stamps t1 on a synchronous message when receiving the synchronous message, and a service processing unit of the line card of the main clock device stamps t 1' on the synchronous message when receiving the synchronous message;
when receiving a synchronous message, a service processing unit of a slave clock equipment line card stamps t2 ' for the synchronous message, when receiving the synchronous message, a PTP message processing unit of the slave clock equipment line card stamps t2 for the synchronous message, calculates a current correction domain CF1 based on the time stamps t1, t1 ', t2 ' and t2, updates the correction domain CF1 into the synchronous message, and sends the synchronous message to the PTP message processing unit of a slave clock equipment main control card;
the method comprises the steps that when a PTP message processing unit of a slave clock equipment line card receives a time delay request message, a time stamp t3 is marked on the time delay request message, and when a service processing unit of the slave clock equipment line card receives the time delay request message, a time stamp t 3' is marked on the time delay request message;
when receiving a delay request message, a service processing unit of a line card of a master clock device stamps t4 ' on the delay request message, when receiving the delay request message, a PTP message processing unit of the line card of the master clock device stamps t4 on the delay request message, calculates a current correction domain CF2 based on the timestamp t3, the timestamp t3 ', the timestamp t4 ' and the timestamp t4, and sends the timestamp t4 and the correction domain CF2 to a PTP message processing unit of a master control card of the master clock device, wherein the PTP message processing unit of the master control card of the master clock device inserts the timestamp t4 and the correction domain CF2 into a delay response message and sends the delay response message to a PTP message processing unit of a master control card of a slave clock device;
and after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock equipment main control card, performing time synchronization adjustment based on the time stamp t1, the time stamp t2, the time stamp t3, the time stamp t4, the correction domain CF1 and the correction domain CF 2.
2. The centralized time synchronization method according to claim 1, wherein before the step of receiving the synchronization message, the PTP message processing unit of the line card of the master clock device further comprises:
a real-time processing unit of a master control card of the master clock equipment sends reference real-time to a real-time processing unit of a line card of the master clock equipment;
a real-time processing unit of the line card of the master clock equipment carries out synchronous calibration of real-time based on the reference real-time to obtain first real-time;
and the real-time processing unit of the line card of the master clock equipment respectively sends the first real-time to the PTP message processing unit of the line card of the master clock equipment and the service processing unit of the line card of the master clock equipment.
3. The centralized time synchronization method according to claim 2, wherein the PTP message processing unit of the line card of the master clock device stamps t1 on the synchronization message when receiving the synchronization message, and the service processing unit of the line card of the master clock device stamps t 1' on the synchronization message when receiving the synchronization message, including:
when a PTP message processing unit of a line card of a master clock device receives a synchronous message, a timestamp t1 is marked for the synchronous message based on the first real-time;
when a service processing unit of a line card of main clock equipment receives a synchronous message, a timestamp t 1' is marked for the synchronous message based on the first real-time.
4. The centralized time synchronization method according to claim 2, wherein the service processing unit of the line card of the master clock device stamps a timestamp t 4' for the delay request message when receiving the delay request message, and the PTP message processing unit of the line card of the master clock device stamps a timestamp t4 for the delay request message when receiving the delay request message, comprising:
when a service processing unit of a line card of main clock equipment receives a time delay request message, a timestamp t 4' is marked for the time delay request message based on the first real-time;
when receiving a delay request message, a PTP message processing unit of a line card of a master clock device stamps t4 on the delay request message based on the first real-time.
5. The centralized time synchronization method according to claim 1, wherein after receiving the synchronization packet and the delay response packet, the PTP packet processing unit of the slave clock device master card performs time synchronization adjustment based on the timestamp t1, the timestamp t2, the timestamp t3, the timestamp t4, the modified domain CF1, and the modified domain CF2, and includes:
after receiving the synchronization message and the delay response message, the PTP message processing unit of the slave clock device main control card finds a delay request message corresponding to the delay response message, and obtains a timestamp t1, a timestamp t2, a timestamp t3, a timestamp t4, a correction domain CF1, and a correction domain CF 2;
the PTP message processing unit of the master control card of the slave clock equipment calculates the synchronous time offset between the slave clock equipment and the master clock equipment according to the following formula:
6. a centralized time synchronization apparatus, comprising: the main clock equipment line card, the slave clock equipment main control card and the slave clock equipment line card respectively comprise PTP message processing units, and the main clock equipment line card and the slave clock equipment line card respectively comprise service processing units;
the PTP message processing unit of the main clock equipment line card stamps t1 on the synchronous message when receiving the synchronous message, and the service processing unit of the main clock equipment line card stamps t 1' on the synchronous message when receiving the synchronous message;
when receiving a synchronous message, a service processing unit of a slave clock equipment line card stamps t2 ' for the synchronous message, when receiving the synchronous message, a PTP message processing unit of the slave clock equipment line card stamps t2 for the synchronous message, calculates a current correction domain CF1 based on the time stamps t1, t1 ', t2 ' and t2, updates the correction domain CF1 into the synchronous message, and sends the synchronous message to the PTP message processing unit of a slave clock equipment main control card;
the method comprises the steps that when a PTP message processing unit of a slave clock equipment line card receives a time delay request message, a time stamp t3 is marked on the time delay request message, and when a service processing unit of the slave clock equipment line card receives the time delay request message, a time stamp t 3' is marked on the time delay request message;
when receiving a delay request message, a service processing unit of a line card of a master clock device stamps a time stamp t4 ' for the delay request message, when receiving the delay request message, a PTP message processing unit of the line card of the master clock device stamps a time stamp t4 for the delay request message, and calculates a current correction domain CF2(CF2 ═ t3 ' -t3+ t4-t4 ') based on the time stamp t3, the time stamp t3 ', the time stamp t4 ' and the time stamp t4, and sends the time stamp t4 and the correction domain CF2 to a PTP message processing unit of a master control card of the master clock device, and the PTP message processing unit of the master control card of the master clock device inserts the time stamp t4 and the correction domain CF2 into a delay response message and sends the delay response message to a PTP message processing unit of a master control card of a slave clock device;
and after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock equipment main control card, performing time synchronization adjustment based on the time stamp t1, the time stamp t2, the time stamp t3, the time stamp t4, the correction domain CF1 and the correction domain CF 2.
7. The centralized time synchronization apparatus of claim 6, wherein the master clock device master card and the master clock device line card each further comprise a real-time processing unit, wherein:
a real-time processing unit of a master control card of the master clock equipment sends reference real-time to a real-time processing unit of a line card of the master clock equipment;
a real-time processing unit of the line card of the master clock equipment carries out synchronous calibration of real-time based on the reference real-time to obtain first real-time;
and the real-time processing unit of the line card of the master clock equipment respectively sends the first real-time to the PTP message processing unit of the line card of the master clock equipment and the service processing unit of the line card of the master clock equipment.
8. The centralized time synchronizing device according to claim 6, wherein the PTP message processing unit of the slave clock device master control card is specifically configured to:
after receiving the synchronization message and the delay response message from the PTP message processing unit of the clock device master control card, finding a delay request message corresponding to the delay response message, and obtaining a timestamp t1, a timestamp t2, a timestamp t3, a timestamp t4, a correction domain CF1, and a correction domain CF 2;
the PTP message processing unit of the master control card of the slave clock equipment calculates the synchronous time offset between the slave clock equipment and the master clock equipment according to the following formula:
9. a centralized time synchronization device, comprising: a memory and a processor, the memory having stored therein at least one instruction that is loaded and executed by the processor to implement the centralized time synchronization method of any of claims 1-5.
10. A computer-readable storage medium characterized by: the computer storage medium stores computer instructions that, when executed by a computer, cause the computer to perform the centralized time synchronization method of any of claims 1-5.
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