CN102891747A - Clock synchronization method and device in communication network - Google Patents
Clock synchronization method and device in communication network Download PDFInfo
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- CN102891747A CN102891747A CN2011102024346A CN201110202434A CN102891747A CN 102891747 A CN102891747 A CN 102891747A CN 2011102024346 A CN2011102024346 A CN 2011102024346A CN 201110202434 A CN201110202434 A CN 201110202434A CN 102891747 A CN102891747 A CN 102891747A
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Abstract
The invention provides a clock synchronization method and a clock synchronization device for the clock synchronization method between a master station and a slave station in a communication network. The master station is used for testing link asymmetry between the stations; according to the test, a link asymmetry parameter is determined and is notified to the slave station; the slave station is used for carrying out corresponding time deviation correction according to the link asymmetry parameter; the master station can be used for carrying out an asymmetry test by establishing an auxiliary reference station; and the auxiliary station and the master station as well as the slave station and the master station have the same link characteristic. According to the scheme of the invention, the master station can use a high-precision main clock to measure a link asymmetry error in advance, the time deviation brought by the link asymmetry can be further compensated by the slave station, the compensation effect is good, and extra expenditure is small.
Description
Technical field
The present invention relates to communication technical field, relate in particular to clock synchronizing method in the communication system and device thereof, system.
Background technology
Ethernet is after becoming the IEEE802.3 standard in 1985, industry is also in the problem of the Timing Synchronization scarce capacity of being devoted to solve Ethernet, develop a kind of NTP (Network Time Protocol) (NTP) of software mode, improve the Timing Synchronization ability between each network equipment.The synchronous accuracy of NTP version in 1992 can reach 200 μ s, but still can not satisfy the required accuracy of measuring instrument and Industry Control.
In order to solve the needs of measuring and controlling the distributed network Timing Synchronization of using, released again " the precision interval clock synchronous protocol standard of network measure and control system ", be IEEE1588, it is the standard of general lifting network system Timing Synchronization ability, basic conception is by hardware and software the internal clock of the network equipment and the master clock of main control computer to be realized synchronously, the utilization of synchronous settling time less than 10 μ s is provided, compare time of delay with the Ethernet of not carrying out the IEEE1588 agreement, the Timing Synchronization index of whole network is significantly improved.
IEEE 1588 is the clock synchronous that are designed for Industrial Ethernet, and Industrial Ethernet is to be approximately symmetrical network.But this hypothesis can not be set up in telecommunications network fully. for example, little base station in the premises, built-in from clock. this base station communicates by the DSLAM (digital subscriber line access multiplex) of ADSL (ADSL (Asymmetric Digital Subscriber Line)) circuit and local side, the built-in master clock of DSLAM, ITU-T Q9922 stipulates that its downstream rate is 1.5Mbps, upstream rate is 512Kbps, is typical asymmetric link.
In fact, a lot of links in the communication network all are asymmetrical. for example, the technology such as ADSL access in radio, WiMAX wireless access, because physical layer up-downgoing processing mode asymmetry (such as, communication modulation system asymmetric, cause the unequal of up-downgoing propagation delay time), the physical link asymmetry of up-downgoing is (such as in the application of looped network, the existence of many transmission paths is arranged) etc., if also can cause the unequal of up-downgoing propagation delay time. still adopt original 1588 mechanism to carry out the synchronous of upper and lower side, will introduce error.
Summary of the invention
The present invention aims to provide a kind of technical scheme of eliminating the clock synchronous error that causes owing to link asymmetry.
According to an aspect of the present invention, provide the clock synchronizing method between master and slave station in a kind of communications network system here, wherein: the link asymmetry between main Station To Station is tested; Main website determines the link asymmetry parameter and notifies slave station according to described test; Slave station carries out corresponding time deviation according to described link asymmetry parameter and proofreaies and correct.
According to another aspect of the present invention, provide here to be used for the method that auxiliary slave station carries out clock synchronous in a kind of communication network device, wherein: the link asymmetry property testing between execution and slave station; Determine the link asymmetry parameter according to described test again; Afterwards, with described link asymmetry parameter notice slave station.
According to another aspect of the present invention, provide a kind of communication network device that carries out clock synchronous for auxiliary slave station here, comprising: synchronizer is used for the link asymmetry property testing between execution and slave station; CPU: determine the link asymmetry parameter according to described test; Transmitting element: with described link asymmetry parameter notice slave station.
According to another aspect of the present invention, provide the method for carrying out clock synchronous in a kind of communication network device with main website here, wherein: communication network device receives the link asymmetry parameter from main website; By with carry out the clock synchronous message switching with main website, calculate the time deviation with respect to the main website clock; Further time deviation is proofreaied and correct according to described link asymmetry parameter.
According to another aspect of the present invention, provide here a kind of for synchronous main website clock communication network device, comprising: deriving means is used for obtaining the link asymmetry parameter of itself and main website; Synchronizer is used for carrying out the clock synchronous message switching with main website; Processing unit according to the sync message exchange of described synchronizer, calculates the time deviation with respect to the main website clock, and further according to described link asymmetry parameter time deviation is proofreaied and correct.
By technology embodiment scheme provided by the present invention, communication network device as main website can come in advance measure link non-symmetric error by high-precision master clock, again by compensating the time deviation that these link asymmetry are brought at each slave station place, with respect to existing scheme, its certainty of measurement is high, compensation effect is good, and extra expense is very little.
Description of drawings
By the detailed description with the accompanying drawing that proposes below, it is more obvious that feature of the present invention, character and advantage will become, and identical element has identical sign in the accompanying drawing, wherein:
Fig. 1 is the clock synchronous schematic flow sheet example of link asymmetry provided by the present invention;
Fig. 2 is clock system structure legend provided by the present invention;
Fig. 3 is link asymmetry on-line testing flow chart illustration provided by the present invention;
Fig. 4 is clock synchronous flow chart illustration provided by the present invention;
Embodiment
Below in conjunction with accompanying drawing, preferred implementation of the present invention is described in detail.
Fig. 1 is the clock synchronous schematic flow sheet example of communication system link asymmetry provided by the present invention, and this communication system comprises a main website and the slave station that is connected thereof, and it comprises the steps:
Step S10, main website carries out the link asymmetry property testing.
Usually, cause the link asymmetry sexual factor between main website and the slave station a lot, for example: physical layer up-downgoing processing mode is different, the material difference of the difference in length of up-downgoing physical link or up-downgoing physical link etc.We can decide according to the link property between main website and the slave station to carry out which kind of link asymmetry property testing, and take which kind of test mode.
Step S11, main website determines that by test link asymmetry parameter and notice are to slave station.For some link asymmetry parameter, it is applicable to all slave stations under the system, and main website can be by mass-sending in the correction territory that it is stored in IEEE 1588 synchronization message Sync to slave stations all under the system; For example: the asymmetry parameter that the physical layer up-downgoing is processed.And only limiting to asymmetry parameter applicable between main website and certain the specific slave station for some, main website can configure by certain mode (such as the software of slave station configures) to corresponding slave station, for example: the asymmetry parameter of physical link between the master-salve station.
Step S12, the clock synchronous flow process is carried out at master and slave station, be main website issue PTP time synchronization protocol and time information, slave station receives the timestamp information that main website sends, system calculates accordingly master and slave circuit up-downgoing and postpones and principal and subordinate's time difference average time, and utilizes this time difference to adjust the local zone time deviation.
Step S13, the link asymmetry parameter that slave station obtains according to step S11 is further carried out the time deviation correction, thereby can eliminate the impact that link asymmetry is brought.
What deserves to be explained is, after communication system started, step S10 and step S11 must finish before step S12, to obtain in advance asymmetry parameter; Before the step S12 of circular flow, can consider also that again operating procedure S10 and step S11 are with the link asymmetry parameter that upgrades in time afterwards;
Below, in conjunction with the clock system structure legend that provides among Fig. 2 the link asymmetry property testing being carried out example explanation, this system comprises a main website 20 with high accuracy real-time clock, extension station 25 and slave station 27, wherein:
Main website 20, it is comprising outside clock unit 411, synchronizer 414, CPU (CPU) 412, MAC layer unit 413, the physical layer element 415, further comprise: a plurality of Mux (selector unit) 403,404,405,406,407,408, these selector unit are subjected to the control of CPU 412, and its control signal 421 is controlled aforementioned selector with different position states and selected different signal paths with the uplink and downlink link of 20 pairs of slave stations 27 of multiple test link and main website of formation native system use.Synchronizer 414 produces synchronism detection message, respectively by receiving the timestamp information of synchronizer 414 record sending and receivings behind the aforementioned test link again; CPU (CPU) 412 determines the link asymmetry parameter according to these timestamp informations, notifies to slave station 27 by relevant mode again.
Slave station 27, be connected with main website 20 by up-downgoing physical link 425,426, it by and main website between the clock synchronous message in the timestamp that carries, calculate up-downgoing path average delay (Delay) and master-salve station time deviation (Offset), thereby obtain proofreading and correct with synchronously, in the present embodiment, it further receives and proofreaies and correct to eliminate the impact that link asymmetry is brought from the link asymmetry parameter of main website and on time deviation.
Extension station 25, be mainly used in auxiliary main website 20 and carry out multiple link asymmetry property testing, it can simulate the link property between aforementioned main website 20 and the slave station 27, particularly, it comprises a complete physical layer 416, its reception (Rx), transmission (Tx) mode of operation are equal to the physical layer design of slave station 27, and physical layer 416 is connected with main website 20 by physical link 422,423.Correspondingly, up-downgoing physical link 422,423 link property also are equal to the up-downgoing physical link 425,426 between main website 20 and the slave station 27; The autonomous station clock 411 of extension station 25 signal source of clock.
As previously mentioned, can test effectively various link asymmetry characteristics are calculated by making up the different links line correlation of going forward side by side between main website 20 and the extension station 25, below the present embodiment the relevant link of link asymmetry formation impact is defined:
In order to test and to estimate the time deviation impact that asymmetry that the physical layer up-downgoing at master and slave station is processed is brought, introduce up test link, descending test link 1, in the legend:
Descending test link 1=physical layer 415Tx+ physical link 409+ physical link 423+ physical layer 416Rx;
Up test link=physical layer 416Tx+ physical link 422+ physical link 424+ physical layer 415Rx;
What deserves to be explained is, physical link length is consistent in descending test link 1, the up test link, that is: physical link 409+ physical link 423=physical link 424+ physical link 422.
Descending test physical link 2 is introduced in the time deviation impact that brings in order further to test and estimate descending physical link length asymmetry, wherein:
Descending test link 2=physical layer 415Tx+ physical link 410+ physical link 423+ physical layer 416Rx.
What deserves to be explained is, above-mentioned descending test link 2 is that with the difference of descending test physical link 1 physical link 410 is different from physical link 409 in length.
Those skilled in the art are to be understood that, in order to test and to estimate that the time deviation that other asymmetric properties bring in the link affects, can further make up other corresponding test links and carry out dependence test, here be not repeated, the concrete test case that the present embodiment provides only is to set forth mentality of designing of the present invention.
According to a kind of embodiment provided by the present invention, when the control signal 421 that CPU 412 produces in the main website 20 is 3 ' b001, performed test is the test of descending test link 1 between main website 20 and the extension station 25, and the path that the synchronism detection message Sync1 that synchronizer 414 produces is passed through is followed successively by: synchronizer 414-〉selector 403-〉physical layer 415Tx-〉selector 405-〉link 409-〉selector 407-〉link 423-〉physical layer 416Rx-〉selector 404-〉synchronizer 414.
According to a kind of embodiment provided by the present invention, when the control signal 421 that CPU 412 produces in the main website 20 is 3 ' b010, performed test is the test of up test link between main website 20 and the extension station 25, and the path that the synchronism detection message Sync2 that synchronizer 414 produces is passed through is followed successively by: synchronizer 414-〉selector 403-〉physical layer 416Tx-〉link 422-〉selector 408-〉link 424-〉selector 406-〉physical layer 415Rx-〉selector 404-〉synchronizer 414.
According to a kind of embodiment provided by the present invention, when the control signal 421 that CPU 412 produces in the main website 20 is 3 ' b100, performed test is the test of descending test link 2 between main website 20 and the extension station 25, and the path that the synchronism detection message Sync3 that synchronizer 414 produces is passed through is followed successively by: synchronizer 414-〉selector 403-〉physical layer 415Tx-〉selector 405-〉link 410-〉selector 407-〉link 423-〉physical layer 416Rx-〉selector 404-〉synchronizer 414.
According to a kind of embodiment provided by the present invention, when the control signal 421 that CPU 412 produces in the main website 20 is 3 ' b000, the uplink and downlink link of 20 pairs of slave stations 27 of main website is chosen simultaneously: wherein a paths is down link, i.e. synchronizer 414-〉selector 403-〉physical layer 415Tx-〉selector 405-〉link 409-〉selector 407-〉link 426-〉slave station 27; An other paths is up link, i.e. slave station 27-〉link 425-〉selector 408-〉link 424-〉selector 406-〉physical layer 415Rx-〉selector 404-〉IEEE 1588 clock synchronous message between synchronizer 414. main websites 20 and the slave station 27 can be undertaken by above-mentioned two paths alternately.
The below describes further combined with the link asymmetry property testing flow process that Fig. 3 provides:
Step S101, S102, the test of descending test link 1 between main website 20 execution and the extension station 25, the synchronism detection signal Sync1 that main website 20 sends returns main website 20 through behind the link, time stamp T 1 and the T2 of synchronism detection signal Sync1 sending and receiving are recorded by main website 20, thus, can obtain following test result:
Major-minor time difference 1,=T2 one T1
Step S103, S104, carry out the test of up link between main website 20 execution and the extension station 25, the synchronism detection signal Sync2 that main website 20 sends returns main website 20 through behind the link, time stamp T 3 and the T4 of synchronism detection signal Sync2 sending and receiving are recorded by main website 20, thus, can obtain following test result:
Auxiliary main time difference=T4 one T3
Step S105, S106, the test of descending test link 2 between main website 20 execution and the extension station 25, the synchronism detection signal Sync3 that main website 20 sends returns main website 20 through behind the link, synchronism detection signal Sync3 sending and receiving time stamp T 5 and T6 are recorded by main website 20, thus, can obtain following test result:
Major-minor time difference 2,=T6 one T5;
Main website 20 is according to the test result in the abovementioned steps, can determine the link asymmetry parameter between it and the slave station 27:
A kind of mode, test by aforementioned major-minor time difference 1, auxiliary main time difference, because adopting same clock to cause the time deviation amount between the major-minor station is 0, physical link length is consistent in descending test link 1, the up test link. and can obtain thus the departure Offset_p that asymmetry that master and slave station physical layer up-downgoing processes is brought, its computing formula is as follows:
Offset_p=(auxiliary main time difference of major-minor time difference 1-)
＝((T2-T1)-(T4-T3))
A kind of mode, the difference between the descending test link 1,2 only is the difference of link 409, link 410, so, if the length of link 410 is compared long L rice with 409 length, can calculate downlink physical liaison unit length lag characteristic:
Descending physical link unit length lag characteristic=(major-minor time difference 1 of major-minor time difference 2-)/L
＝((T6-T5)-(T2-T1))/L；
Fig. 4 is the clock synchronous flow chart illustration between the master and slave station provided by the present invention:
In the synchronizing process of system, main website 20 periodically issues PTP time synchronization protocol and time information, slave station 27 receives the timestamp information that main website 20 sends, system calculates master and slave circuit up-downgoing average retardation and principal and subordinate's time difference accordingly, and utilize this time difference to adjust local zone time, make from equipment time maintenance frequency and the phase place consistent with main station time.
Step S121, main website 20 mass-sendings synchronously (Sync) message are recorded this message t2 time of advent to slave station 27 after slave station 27 receives; As previously mentioned, main website can further carry the asymmetry parameter that the physical layer up-downgoing is processed in this synchronization message;
Step S122, main website 20 initiates the Follow_Up message, t1 when it comprises previous Sync message and leaves main website 20 accurate, slave station 27 is write down t1 after receiving Follow_Up message;
Step S123, the PTP protocol application layer of slave station 27 send out and postpone request (Delay_Req) message to main website 20, the departure time t3 of slave station 27 record Delay_Req, 20 record its time of advent of the t4 of main website;
Step S124, main website 20 issues slave station 27 to t4 by delayed response (Delay_Resp) message.This moment slave station 27 know Delay_Req message delivery time t3 and the time of reception t4, and send and receive time t1, the t2 of Sync message.
Through after the above-mentioned time-stamping messages answering, can obtain following computing formula:
Principal and subordinate time difference=A=Offset+MS_Delay=t2 one t1
From main time difference=B=SM_Delay-Offset=t4 one t3
Two formula by top can obtain:
Offset＝(A-B)/2-(MS_Delay-SM_Delay)/2
Under the regular situation, related protocol hypothesis downlink delay MS_Delay equals up link time delay SM_Delay, then can draw the time deviation Offset_est of an estimation at slave station:
Offset_est＝(A-B)/2
27 of main website 20 and slave stations constantly send the PTP agreement, and slave station 27 is revised local time deviation according to aforementioned Offset_est, synchronizes them 20 times of main website.
Step S13, slave station 27 is further revised local time deviation according to the link asymmetry parameter that obtains, namely on aforementioned Offset_est basis, further consider the deviation that master and slave station physical layer up-downgoing processing mode asymmetry is brought, then new deviation is:
Offset_1＝Offset_est-0.5*Offset_p
＝Offset_est-0.5*((T2-T1)-(T4-T3))；
Wherein, Offset_p is the departure that asymmetry that master and slave station physical layer up-downgoing that aforementioned test obtains is processed is brought.
If further contemplated the deviation that physical link length asymmetry is brought between the master and slave station, then new deviation is:
Offset_2=Offset_1-0.5* descending physical link unit length lag characteristic * l
＝Offset_1-0.5*((((T6-T5)-(T2-T1))/L)*l)；
What deserves to be explained is, suppose that here main website 20 is identical with upper and lower property link transmission characteristic between the slave station 27, only length distance is different, and l is the difference in length between link 425 and 426, parameter l difference for each slave station.
Come therefrom, slave station 27 is proofreaied and correct local zone time according to aforementioned time deviation Offset_1 or Offset_2, has eliminated the impact that link asymmetry is brought time deviation, makes it approach as far as possible the time of master clock.
Those skilled in the art can further understand, and can be used as electronic hardware, computer software or the combination of the two in conjunction with the described various illustrative logical blocks of embodiment disclosed herein, module and algorithm steps and realizes.In order to clearly demonstrate the interchangeability between the hardware and software, as various illustrative assemblies, block diagram, module, circuit and the step 1 according to its functional elaboration.These are functional realizes specific application program and the design of depending on that whole system adopts as hardware or software actually.The technical staff can recognize the interactivity of hardware and software in these situations, and the described function that how to realize best each application-specific.The technical staff may be realizing described function for the different mode of each application-specific, but this realization determines should not be interpreted as causing to deviate from scope of the present invention.
The realization of various illustrative logical block, module and the algorithm steps of describing in conjunction with embodiment as described herein or carry out and to use: general processor, digital signal processor (DSP), application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or the combination in any that designs for carrying out function described here.General processor may be microprocessor, yet or, processor can be processor, controller, microcontroller or the state machine of any routine.Processor also may realize with the combination of computing equipment, such as the combination of DSP and microprocessor, multi-microprocessor, in conjunction with one or more microprocessors of DSP kernel or arbitrarily other this configuration.
May directly be included in the hardware in conjunction with the method for disclosed embodiment description here or the step of algorithm, by in the software module of processor execution or in the middle of both.Software module may reside in the storage media of RAM memory, flash memory, ROM memory, eprom memory, eeprom memory, register, hard disk, removable dish, CD-ROM or any other form as known in the art.The coupling of exemplary storage medium and processor so that processor can be from the storage media reading information, or writes storage media to information.Perhaps, storage media can be integrated with processor.Processor and storage media may reside among the ASIC.
Although above-mentioned being illustrated as the invention provides some embodiment; be not to limit protection scope of the present invention; the professional of the art can carry out various modifications to embodiment under the prerequisite that does not depart from the scope of the present invention with spirit, this modification all is within the scope of the present invention.
Claims (14)
1. the clock synchronizing method between master and slave station in the communications network system comprises the steps:
Steps A 1, the link asymmetry between main Station To Station is tested;
Step B1, main website determines the link asymmetry parameter and notifies slave station according to described test;
Step C1, slave station carry out corresponding time deviation according to described link asymmetry parameter and proofread and correct.
2. the method for claim 1 is characterized in that in the described steps A 1, and main website carries out described link asymmetry property testing by setting up an extension station, between extension station and the main website, have identical link property between slave station and the main website.
3. the method for claim 1 is characterized in that described link asymmetry property testing comprises the test of physical layer up-downgoing processing mode asymmetry.
4. method as claimed in claim 3 is characterized in that described link asymmetry property testing further comprises the test of physical link length asymmetry.
5. be used for the method that auxiliary slave station carries out clock synchronous in a communication network device, comprise the steps:
Steps A 2, the link asymmetry property testing between execution and slave station;
Step B2 determines the link asymmetry parameter according to described test;
Step C2 is with described link asymmetry parameter notice slave station.
6. method as claimed in claim 5, it is characterized in that in the described steps A 2, communication network device carries out described link asymmetry property testing by setting up an extension station, between extension station and the communication network device, have identical link property between slave station and the communication network device.
7. method as claimed in claim 6 is characterized in that among the described step B2, and described link asymmetry parameter comprises that physical layer up-downgoing processing asymmetry postpones.
8. method as claimed in claim 6 is characterized in that among the described step B2, and described link asymmetry parameter comprises that physical link length asymmetry postpones.
9. method as claimed in claim 5 is characterized in that among the described step C2, and described link asymmetry parameter sends to slave station by IEEE 1588 synchronization messages.
10. one kind is used for the communication network device that auxiliary slave station carries out clock synchronous, it is characterized in that comprising:
Synchronizer is used for the link asymmetry property testing between execution and slave station;
CPU: determine the link asymmetry parameter according to described test;
Transmitting element: with described link asymmetry parameter notice slave station.
11. carry out the method for clock synchronous in the communication network device with main website, comprise the steps:
Steps A 3 receives the link asymmetry parameter from main website;
Step B3 carries out the clock synchronous message switching with main website, calculates the time deviation with respect to the main website clock;
Step C3 further proofreaies and correct time deviation according to described link asymmetry parameter.
12. method as claimed in claim 11 is characterized in that among the described step C3, communication network device is proofreaied and correct the time deviation that physical layer up-downgoing processing asymmetry causes according to the link asymmetry parameter.
13. method as claimed in claim 11 is characterized in that among the described step C3 that communication network device is proofreaied and correct the time deviation that physical link length asymmetry causes according to the link asymmetry parameter.
14. one kind be used for synchronous main website clock communication network device, it is characterized in that comprising:
Deriving means: the link asymmetry parameter that is used for obtaining itself and main website;
Synchronizer: be used for carrying out the clock synchronous message switching with main website;
Processing unit: according to the sync message exchange of described synchronizer, calculate the time deviation with respect to the main website clock, and further according to described link asymmetry parameter time deviation is proofreaied and correct.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103546268A (en) * | 2013-10-15 | 2014-01-29 | 瑞斯康达科技发展股份有限公司 | Method and device for compensating system time |
| CN103825695B (en) * | 2014-03-11 | 2017-02-08 | 武汉迈信电气技术有限公司 | Compensation method for synchronous time delay of network based on POWERLINK |
| CN109005557A (en) * | 2018-09-26 | 2018-12-14 | 南京中兴新软件有限责任公司 | A kind of time delay symmetry measurement method, device and system |
| CN109787704A (en) * | 2019-03-01 | 2019-05-21 | 燕山大学 | A kind of time deviation compensation method based on asymmetric link |
| WO2019128869A1 (en) * | 2017-12-29 | 2019-07-04 | 华为技术有限公司 | Flexible ethernet delay measurement method and related device |
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| CN101854240A (en) * | 2010-05-11 | 2010-10-06 | 上海奇微通讯技术有限公司 | Method for improving wireless time service precision |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101854240A (en) * | 2010-05-11 | 2010-10-06 | 上海奇微通讯技术有限公司 | Method for improving wireless time service precision |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103546268A (en) * | 2013-10-15 | 2014-01-29 | 瑞斯康达科技发展股份有限公司 | Method and device for compensating system time |
| CN103546268B (en) * | 2013-10-15 | 2016-08-10 | 瑞斯康达科技发展股份有限公司 | The compensation method of a kind of system time and equipment |
| CN103825695B (en) * | 2014-03-11 | 2017-02-08 | 武汉迈信电气技术有限公司 | Compensation method for synchronous time delay of network based on POWERLINK |
| WO2019128869A1 (en) * | 2017-12-29 | 2019-07-04 | 华为技术有限公司 | Flexible ethernet delay measurement method and related device |
| US11411848B2 (en) | 2017-12-29 | 2022-08-09 | Huawei Technologies Co., Ltd. | Flexible ethernet latency measurement method and related device |
| CN109005557A (en) * | 2018-09-26 | 2018-12-14 | 南京中兴新软件有限责任公司 | A kind of time delay symmetry measurement method, device and system |
| CN109787704A (en) * | 2019-03-01 | 2019-05-21 | 燕山大学 | A kind of time deviation compensation method based on asymmetric link |
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