CN102006157A - Time synchronization method and system - Google Patents

Time synchronization method and system Download PDF

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CN102006157A
CN102006157A CN2010105610706A CN201010561070A CN102006157A CN 102006157 A CN102006157 A CN 102006157A CN 2010105610706 A CN2010105610706 A CN 2010105610706A CN 201010561070 A CN201010561070 A CN 201010561070A CN 102006157 A CN102006157 A CN 102006157A
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network interface
physics network
slave unit
main equipment
expression
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CN102006157B (en
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罗丽
彭勇
傅小明
唐雄
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ZTE Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays

Abstract

The invention discloses a time synchronization method and a time synchronization system. The method comprises the following steps that: main equipment informs slave equipment of physical network port rate of the main equipment in an information form; and after acquiring the physical network port rate of the main equipment, the slave equipment judges whether the acquired physical network port rate of the main equipment is the same as the physical network port rate of the slave equipment or not, if so, the slave equipment does not compensate calculated average line transmission delay, and otherwise, the slave equipment compensates the calculated average line transmission delay. By using the technical scheme, the problem of phase asynchronization due to delay asymmetry caused by inconsistent main and slave physical network port rates can be solved in a delay request response mechanism.

Description

A kind of method and system of time synchronized
Technical field
The present invention relates to the clock synchronization field, relate in particular to a kind of method and system of time synchronized.
Background technology
In communication system, along with the continuous development of data service and multimedia service, IP-based packet network transmits the main flow that data have been development.At this moment, new on the one hand business and new application propose higher requirement to the net synchronization capability of network, on the other hand to the professional compatibility of traditional TDM (Time Division Multiplexing, time division multiplexing) etc. all need packet network provide high-quality synchronously with performance regularly.
IEEE1588 PTP (Precision Time Synchronization Protocol, the precision interval clock synchronous protocol) be for overcome the Ethernet real-time not enough stipulate a kind of to the time mechanism, its appearance has brought hope to us, its cardinal principle be to all nodes in the network carry out to the time synchronous, periodically the clock of all nodes in the network is proofreaied and correct synchronously by a precise time source.
IEEE 1588 PTP are a kind of ethernet clock synchronous protocols, realize that by sync message the principal and subordinate is synchronous.The PTP standard agreement can be carried on Ethernet 802.3, UDP/IPv4 and UDP/IPv6, and the form of 802.3 frame structures is as shown in table 1.
Table 1
IEEE 1588v2 system is as a kind of principal and subordinate's synchro system, in the synchronizing process of system, master clock sends the PTP temporal information at interval according to preset time, receive the timestamp information that the master clock port is sent from clock port, system calculates principal and subordinate's circuit time delay and principal and subordinate's time difference in view of the above, and utilize this time difference to adjust local zone time, make the slave unit time keep frequency and the phase place consistent with the main equipment time.Concrete scheme as shown in Figure 1.Main equipment (Master) sends Sync (synchronously) message, and writing time t1.Slave unit (Slave) writes down t2 when receiving the Sync message.Slave unit is known t1 according to Follow_up (tracking) message that main equipment sends.Slave unit is initiated Delay_Req (postpone request) message accordingly, simultaneously writing time t3, after main equipment was received the Delay_Req message, writing time, t4 and inserted Delay_Resp (time-delay response) message.Slave unit is known t4 according to Delay_Resp (delayed response) message that main equipment sends.
T1 and t2 are respectively the transmission of Sync message and time of reception stabs among Fig. 1, and promptly t1 is the time of Sync message when going out main equipment, and t2 is the time during to slave unit for the Sync message.T3 and t4 are respectively the transmission of Delay_Req message and time of reception stabs, i.e. t3 time of going out slave unit for the Delay_Req message, t4 is the time of Delay_Req message to main equipment.
Average line transmission delay mean_path_delay=[(t2-t1)+(t4-t3)]/2=[(t2-t3)+(t4-t1)]/2 (formula 1)
The difference of the time of slave unit and the time of main equipment is offset=[(t1-t2)+(t4-t3)]/2 (formulas 2)
By top two formulas, can be the time synchronized of slave unit in main equipment.
Synchronizer manufacturers are attempting to replace GPS (Global Positioning System, global positioning system) clock source with the IEEE1588 network clocking at present, but also there are some problems in the IEEE1588-2008 of issue when realizing.
Summary of the invention
Existing IEEE1588-2008 standard clearly describe main with from physical connection network interface rate-matched whether, if principal and subordinate's physical connection network interface speed is inconsistent, can cause main to from time of delay with from different to the time of delay of leading, thereby the generation time synchronous error causes phase place asymmetry problem when synchronous.
The technical problem to be solved in the present invention proposes a kind of method and system of time synchronized, because timestamp interface physical rate is inconsistent, causes asynchronism(-nization) step problem between the principal and subordinate between the solution principal and subordinate.
In order to address the above problem, the invention provides a kind of method of time synchronized, comprising:
Main equipment is informed slave unit with the physics network interface rate information of self;
After slave unit is known the physics network interface speed of main equipment, compare,, then the average line transmission delay that calculates is compensated if inequality with self physics network interface speed, otherwise, do not compensate.
Preferably, said method has following characteristics:
Described main equipment informs that with the physics network interface speed of self step of slave unit comprises:
Main equipment sends the notice message to slave unit, carries the physics network interface rate information of self in the described notice message.
Preferably, said method has following characteristics:
Described main equipment is before slave unit sends the notice message, and described main equipment writes self physics network interface rate information in the territory number and the reserve bytes between the identification field of described notice message.
Preferably, said method has following characteristics:
In the described physics network interface rate information, adopt physics network interface speed, 0010 expression 100M physics network interface speed, 0100 expression 1000M physics network interface speed, the 1000 expression 10000M physics network interface speed of 0001 expression 10M.
Preferably, said method has following characteristics:
Described slave unit deducts delay time error by the average line transmission delay that will calculate, described clock jitter compensated, wherein,
Described delay time error is:
L 1Expression is whole frame length except that frame preamble and check digit, L 2Expression check bit length, L 3Expression frame preamble length, Sm represents that the physics network interface of main equipment transmits the time of every Bit data, Ss represents that the physics network interface of slave unit transmits the time of every Bit data.
In order to address the above problem, the invention provides a kind of system of time synchronized, comprise main equipment and one or more slave unit,
Main equipment is used for the physics network interface rate information of self is informed slave unit;
After slave unit is used to know the physics network interface speed of main equipment, compare,, then the average line transmission delay that calculates is compensated if inequality with self physics network interface speed, otherwise, do not compensate.
Preferably, said system has following characteristics:
Main equipment is further used for carrying the physics network interface rate information of self in the described notice message by send the notice message to slave unit, and the physics network interface rate information of self is informed slave unit.
Preferably, said system has following characteristics:
Described main equipment was further used for before slave unit sends the notice message, self physics network interface rate information was write in the territory number and the reserve bytes between the identification field of described notice message.
Preferably, said system has following characteristics:
In the described physics network interface rate information, adopt physics network interface speed, 0010 expression 100M physics network interface speed, 0100 expression 1000M physics network interface speed, the 1000 expression 10000M physics network interface speed of 0001 expression 10M.
Preferably, said system has following characteristics:
Described slave unit is further used for deducting delay time error by the average line transmission delay that will calculate, described clock jitter compensated, wherein,
Described delay time error is:
Figure BDA0000034422720000041
L 1Expression is whole frame length except that frame preamble and check digit, L 2Expression check bit length, L 3Expression frame preamble length, Sm represents that the physics network interface of main equipment transmits the time of every Bit data, Ss represents that the physics network interface of slave unit transmits the time of every Bit data.
Adopt technical scheme of the present invention, in time-delay request response mechanism, can solve, cause the asynchronous problem of phase place because the inconsistent delay that causes of principal and subordinate's physics network interface speed is asymmetric.
Description of drawings
Fig. 1 is a time-delay request response mechanism schematic diagram;
Fig. 2 is the networking schematic diagram;
Fig. 3 is the flow chart that the present invention uses example.
Embodiment
At first, the problem that prior art is occurred is analyzed:
In the networking mode as shown in Figure 2, under the unmatched situation of physical interface speed, can bring asymmetric latency issue between main equipment and the slave unit.For Fig. 2, we analyze under the following conditions:
1, the circuit transmission delay of both direction equates;
2, middle unknown network (cloud network) time-delay is identical;
3, between frame preamble (preamble) and purpose MAC, beat timestamp;
For problem analysis needs, do following hypothesis simultaneously:
(1) adopts the UDP/IPv4/Ethernet header, comprise check digit, whole Bao Changwei 86 bits;
(2) message frame begins to transmit after reading in buffer memory fully by switch again;
(3) frame preamble is 8 bits;
(4) check digit is 4 bits;
(5) the physics network interface speed of main equipment is gigabit Ethernet;
(6) the physics network interface speed of slave unit is 100 m ethernet;
On the direction of slave unit, the time-delay of event message is at main equipment:
T2-t1=(L 1+ L 2) Bytes* 8 Bits/byte* GE Ns/bit+ D PSN+ (L 3) Bytes* 8 Bits/byte* FE Ns/bit(formula 3)
Wherein, L 1Expression whole frame length except that frame preamble (pre-amble) and check digit (FCS);
L 2Expression check bit (FCS) length;
L 3Expression frame preamble (pre-amble) length;
GE Ns/bitThe time that expression 1000M physics network interface is transmitted every bit data;
FE Ns/bitThe time that expression 100M physics network interface is transmitted every bit data;
D PSNThe expression packet is through the time of delay of unknown network;
On the direction of main equipment, the time-delay of event message is at slave unit:
T4-t3=(L 1+ L 2) Bytes* 8 Bits/byte* FE Ns/bit+ D PSN+ (L 3) Bytes* 8 Bits/byte* GE Ns/bit(formula 4)
L wherein 1, L 2, L 3, GE Ns/bit, FE Ns/bit, D PSNIdentical with formula 3 expressions.
The average line transmission delay as shown in the formula:
N meanPathDelay = [ ( t 2 - t 1 ) + ( t 4 - t 3 ) ] 2 (formula 5)
With formula (3) and formula (4) substitution formula (5) be:
N meanPathDealy = ( L 1 + L 2 + L 3 ) × 8 × ( GE + FE ) ns 2 + D PSN (formula 6)
Top result of calculation is to think just to think on the symmetrical basis in the delay of principal and subordinate's both direction
(t2-t1)=(t4-t3) (formula 7)
And in fact these two is unequal.
Formula 3 subtracts formula 6 calculating Master:
N meanPathDelayAssymmetry = ( L 1 + L 2 ) × 8 × GE - FE 2 + L 3 × 8 × FE - GE 2 (formula 8)
Formula 6 subtracts formula 4 calculating Master:
N meanPathDelayAssymmetry = ( L 1 + L 2 ) × 8 × GE - FE 2 + L 3 × 8 × FE - GE 2 (formula 9)
For 1000M physics network interface, passing one digit number is 1ns according to the needed time, and for 100M physics network interface, passing one digit number is 10ns according to the needed time.Substitution formula 8 or formula 9 can obtain,
N meanPathDelayAssymmetry = ( 86 + 4 ) × 8 × 1 - 10 2 + 8 × 8 × 10 - 1 2 = - 2952 ns (formula 10)
Derive theoretically, between the principal and subordinate, owing under 1000M physics network interface and the unmatched situation of 100M physics network interface speed, cause-error of 2.952us, it is because the deviation between the principal and subordinate causes that this error will be mistaken as, and will cause the different problem of phase place between the principal and subordinate after the adjustment.
For the correctness that proves that this is theoretical, done following experiment, main equipment is a 1000M physics network interface speed, slave unit is a 100M physics network interface speed, respectively through one-level exchange and nine grades of exchanges.Experimental result is as shown in the table.As seen from Table 2, the increase of exchange progression, to not influence of asymmetry, this asymmetry is not matched by principal and subordinate's physics network interface speed to cause.
Table 2
Figure BDA0000034422720000071
Illustrate: the phase place of "-" expression Slave is ahead of the phase place of Master
No matter the PTP message is carried on the Ethernet 802.3, still is carried on all to have same problem on UDP/IPv4 and the UDP/IPv6.As long as physics network interface speed is inconsistent between the principal and subordinate, then can cause main to from time-delay between with from different time of delay to primary message, thereby the asynchronous problem of phase place between the principal and subordinate after causing synchronously.
The present invention proposes to solve between the principal and subordinate that physics network interface speed is inconsistent to cause postponing the asymmetry problem.Method is as follows: main equipment is informed slave unit with the physics network interface rate information of self; After slave unit is known the physics network interface speed of main equipment, compare,, then the average line transmission delay that calculates is compensated if inequality with self physics network interface speed, otherwise, do not compensate.
Particularly, main equipment can carry the physics network interface rate information of self by sending Announce (notice) message to slave unit in the described notice message.
This physics network interface rate information can be arranged in reserved (reservation) byte between domainNumber (territory number) and the flagField (identification field), also promptly: described main equipment is before slave unit sends the notice message, and described main equipment can write the physics network interface rate information of self in the domainNumber of described notice message and the reserved byte between the flagField.
In the described physics network interface rate information, can adopt physics network interface speed, 0010 expression 100M physics network interface speed, 0100 expression 1000M physics network interface speed, the 1000 expression 10000M physics network interface speed of 0001 expression 10M.
Described slave unit deducts delay time error by the average line transmission delay that will calculate, described clock jitter compensated, wherein,
Described delay time error is:
Figure BDA0000034422720000072
(formula 11)
L 1Expression is whole frame length except that frame preamble and check digit, L 2Expression check bit length, L 3Expression frame preamble length, Sm represents that the physics network interface of main equipment transmits the time of every Bit data, Ss represents that the physics network interface of slave unit transmits the time of every Bit data.
Correspondingly, the system of the time synchronized of the embodiment of the invention comprises main equipment and one or more slave unit, wherein,
Main equipment is informed slave unit with the physics network interface rate information of self when implementing its master device functionality;
Slave unit when implementing its master device functionality, know the physics network interface speed of main equipment by the Announce message after, compare with self physics network interface speed, if it is inequality, then the average line transmission delay that calculates is compensated, otherwise, do not compensate.
Main equipment can be further used for carrying the physics network interface rate information of self in the described notice message by send the notice message to slave unit, and the physics network interface rate information of self is informed slave unit.
Described main equipment was further used for before slave unit sends the notice message, the physics network interface rate information of self can be write in the territory number and the reserve bytes between the sign of field of described notice message.
Described slave unit can be further used for deducting delay time error by the average line transmission delay that will calculate, described clock jitter compensated, wherein,
Described delay time error is:
Figure BDA0000034422720000081
L 1Expression is whole frame length except that frame preamble and check digit, L 2Expression check bit length, L 3Expression frame preamble length, Sm represents that the physics network interface of main equipment transmits the time of every Bit data, Ss represents that the physics network interface of slave unit transmits the time of every Bit data.
Increase expression main equipment physics network interface speed application example below by one at the Announce message header and further specify the present invention.
Use 1588 models that carry out time synchronized as shown in Figure 2, a plurality of switches, router etc. may be passed through in the centre.
As shown in Figure 3, this example comprises the steps:
Step 301, main equipment writes the physics network interface rate information of self in the domainNumber of Announce message and the reserved byte between the flagField, wherein, 0001 expression 10M, 0010 expression 100M, 0100 expression 1000M, 1000 expression 10000M;
Former Announce message header can be referring to table 3, and the new Announce message header of this example can be referring to table 4;
Step 302, main equipment sends to slave unit with this Announce message;
After step 303, slave unit receive the Announce message, parse the physics network interface speed of main equipment;
Step 304, if slave unit the physics network interface speed ratio of the physics network interface speed of the main equipment that parses and slave unit identical, does not then compensate, if inequality, parses the length of message, and the value of calculating according to formula 11 compensates then.
According to above-mentioned steps, just can guarantee between the principal and subordinate under the inconsistent situation of physics network interface speed, can not produce because the asymmetric asymmetric problem of synchronous back phase place that causes of circuit.
The Announce message header of table 3 prior art
Figure BDA0000034422720000091
Figure BDA0000034422720000101
Table 4 should be used the Announce message header of example
One of ordinary skill in the art will appreciate that all or part of step in the said method can instruct related hardware to finish by program, described program can be stored in the computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of the foregoing description also can use one or more integrated circuits to realize, correspondingly, each the module/unit in the foregoing description can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. the method for a time synchronized comprises:
Main equipment is informed slave unit with the physics network interface rate information of self;
After slave unit is known the physics network interface speed of main equipment, compare,, then the average line transmission delay that calculates is compensated if inequality with self physics network interface speed, otherwise, do not compensate.
2. the method for claim 1 is characterized in that,
Described main equipment informs that with the physics network interface speed of self step of slave unit comprises:
Main equipment sends the notice message to slave unit, carries the physics network interface rate information of self in the described notice message.
3. method as claimed in claim 2 is characterized in that,
Described main equipment is before slave unit sends the notice message, and described main equipment writes self physics network interface rate information in the territory number and the reserve bytes between the identification field of described notice message.
4. as any described method in the claim 1～3, it is characterized in that,
In the described physics network interface rate information, adopt physics network interface speed, 0010 expression 100M physics network interface speed, 0100 expression 1000M physics network interface speed, the 1000 expression 10000M physics network interface speed of 0001 expression 10M.
5. as any described method in the claim 1～3, it is characterized in that,
Described slave unit deducts delay time error by the average line transmission delay that will calculate, described clock jitter compensated, wherein,
Described delay time error is:
Figure FDA0000034422710000011
L 1Expression is whole frame length except that frame preamble and check digit, L 2Expression check bit length, L 3Expression frame preamble length, Sm represents that the physics network interface of main equipment transmits the time of every Bit data, Ss represents that the physics network interface of slave unit transmits the time of every Bit data.
6. the system of a time synchronized comprises main equipment and one or more slave unit, it is characterized in that,
Main equipment is used for the physics network interface rate information of self is informed slave unit;
After slave unit is used to know the physics network interface speed of main equipment, compare,, then the average line transmission delay that calculates is compensated if inequality with self physics network interface speed, otherwise, do not compensate.
7. system as claimed in claim 6 is characterized in that,
Main equipment is further used for carrying the physics network interface rate information of self in the described notice message by send the notice message to slave unit, and the physics network interface rate information of self is informed slave unit.
8. system as claimed in claim 7 is characterized in that,
Described main equipment was further used for before slave unit sends the notice message, self physics network interface rate information was write in the territory number and the reserve bytes between the identification field of described notice message.
9. as any described system in the claim 6～8, it is characterized in that,
In the described physics network interface rate information, adopt physics network interface speed, 0010 expression 100M physics network interface speed, 0100 expression 1000M physics network interface speed, the 1000 expression 10000M physics network interface speed of 0001 expression 10M.
10. as any described system in the claim 6～8, it is characterized in that,
Described slave unit is further used for deducting delay time error by the average line transmission delay that will calculate, described clock jitter compensated, wherein,
Described delay time error is:
Figure FDA0000034422710000021
L 1Expression is whole frame length except that frame preamble and check digit, L 2Expression check bit length, L 3Expression frame preamble length, Sm represents that the physics network interface of main equipment transmits the time of every Bit data, Ss represents that the physics network interface of slave unit transmits the time of every Bit data.
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