WO2013091240A1

WO2013091240A1 - Method, device and system for data synchronization processing of external clock

Info

Publication number: WO2013091240A1
Application number: PCT/CN2011/084541
Authority: WO
Inventors: 熊良兵; 张魁
Original assignee: 华为技术有限公司
Priority date: 2011-12-23
Filing date: 2011-12-23
Publication date: 2013-06-27
Also published as: CN102549951A

Abstract

The present invention provides a method, a device and a system for data synchronization processing of an external clock. The method comprises: a first device receiving a first external clock data sent by a second device, the first external clock data comprising update clock data and a first verification result; verifying the update clock data by using an FEC algorithm to obtain a second verification result, and determining whether the first verification result and the second verification result are the same; and if it is determined that the first verification result and the second verification result are the same, performing synchronization processing on the clock in the first device according to the update clock data in the first external clock data when a second external clock data sent by the second device is received, the second external clock data being external clock data next to the first external clock data.

Description

External clock data synchronization processing method, device and system

Technical field

The present invention relates to communication technologies, and in particular, to an external clock data synchronization processing method, device and system. Background technique

The Network Time Protocol (NTP) has the ability to improve the timing synchronization between network devices. Currently, the synchronization time of the protocol can reach 200us, but it still cannot meet the accuracy required for measuring instruments and industrial control. degree. In order to solve the need of distributed network timing synchronization for measurement and control applications, a Institute of Electrical and Electronics Engineers (IEEE) 1588 is proposed. The full name of the IEEE1588 protocol can be: Precision clock synchronization protocol standard for measurement and control systems.

Currently, the IEEE1588 protocol is widely used in the field of communications for time synchronization and frequency synchronization within the network. In addition, in the specific protocol implementation, the IEEE1588 protocol can adopt the inband mode and the outband mode. The inband mode can be specifically the IEEE1588 protocol. The outband mode can be specifically a single line per second. Pulse (Pulse Per Second; PPS) external clock mode. For the single-line PPS external clock mode, it is mainly used between devices with non-Ethernet interfaces, that is, the master device transmits PPS pulses to the slave device through a single line in seconds, so that the slave device realizes time synchronization according to the PPS pulse. However, if an error occurs in the PPS pulse transmitted on a single line, an error will occur in the slave device time synchronization, resulting in an increased jitter deviation between the master device clock and the slave device clock. Summary of the invention

A first aspect of the present invention provides a method for synchronizing an external clock data, including: receiving, by a first device, first external clock data sent by a second device, where the first external clock data includes updated clock data and a first calibration Test result

The first device uses an FEC algorithm to check the updated clock data to obtain a second Checking the result, and determining whether the first verification result and the second verification result are the same; if the first device determines that the first verification result and the second verification result are the same, When receiving the second external clock data sent by the second device, synchronizing the clock of the first device according to the updated clock data in the first external clock data; wherein, the second outer The clock data is the latter outer clock data of the first outer clock data.

Another aspect of the present invention provides an external clock data synchronization processing device, including: a receiving module, configured to receive first external clock data sent by a second device, where the first external clock data includes updated clock data and a first Calibration result

a verification module, configured to perform verification on the updated clock data by using an FEC algorithm, obtain a second verification result, and determine whether the first verification result and the second verification result are the same;

a first synchronization processing module, configured to: when the verification module determines that the first verification result and the second verification result are the same, receive, by the receiving module, the second And synchronizing the clock of the first device according to the updated clock data in the first external clock data; wherein the second external clock data is after the first external clock data An external clock data.

Another aspect of the present invention provides an external clock data synchronization processing system including a first device and a second device;

Receiving, by the first device, first external clock data sent by the second device, where the first external clock data includes updated clock data and a first verification result;

The first device uses a forward error correction FEC algorithm to check the updated clock data, obtain a second verification result, and determine whether the first verification result and the second verification result are the same. If the first device determines that the first verification result and the second verification result are the same, when receiving the second external clock data sent by the second device, according to the first external clock The clock of the first device is synchronized with the updated clock data in the data; wherein the second external clock data is the latter external clock data of the first external clock data.

The technical effect of the present invention is: the first device uses the FEC algorithm to check the updated clock data of the first external clock data sent by the second device, obtains the second verification result, and determines the first external clock data. Whether the first verification result and the second verification result are the same, if the same, when the second external clock data sent by the second device is received, synchronizing the clock of the first device according to the updated clock data , because the first check result is added to the first outer clock data, and The FEC algorithm is used in a device, which increases the FEC check function of self-checking and self-correcting. Therefore, the reliability of the synchronous clock using the single-wire PPS external clock mode can be effectively improved, and the first device is effectively reduced. The jitter deviation between the clock and the clock of the second device. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a flowchart of an embodiment of an external clock data synchronization processing method according to the present invention; FIG. 2 is a schematic diagram of a format of a first external clock data according to the present invention;

FIG. 3 is a schematic diagram of another embodiment of an external clock data synchronization processing method according to the present invention; FIG. 4 is a schematic structural diagram of an external clock data synchronization processing device according to an embodiment of the present invention; FIG. 6 is a schematic structural diagram of an embodiment of an external clock data synchronization processing system according to the present invention. 1 is a flowchart of an embodiment of an external clock data synchronization processing method according to the present invention. As shown in FIG. 1, the method in this embodiment includes:

Step 101: The first device receives first external clock data sent by the second device, where the first external clock data includes updated clock data and a first verification result.

In this embodiment, FIG. 2 is a schematic diagram of a format of a first external clock data according to the present invention. As shown in FIG. 2, the first external clock data is borrowed from a Building Integrated Timing Supply (BITS) department. A serial transmission protocol is defined, that is, the first external clock data is 16 bytes of data, and each byte uses the start bit of the Ibit and the stop bit of the Ibit. In addition, the first external clock data is mainly composed of five data segments, including: a data segment (PPS segment), b data segment (wait segment), c data segment (serial information segment), d data segment (idle segment) And an FEC data segment, wherein the c data segment includes update clock data, and the FEC data segment includes a check result for the c data segment.

In addition, the second device is a Building Integrated Timing Supply (BITS) device, which is a clock source device with high maintenance level and high precision, and can be used to provide a stable clock in a certain area. Reference source; The first device is a slave clock device connected to the second device, and is a timing device that maintains a local clock through a timing process with a clock source. Step 102: The first device uses a Forward Error Correction (FEC) algorithm to check the updated clock data, obtain a second verification result, and determine the first verification result and the second Check if the results are the same.

Step 103: If the first device determines that the first verification result is the same as the second verification result, when receiving the second external clock data sent by the second device, according to the first external clock data The clock data is updated, and the clock of the first device is synchronized.

The second outer clock data is the next outer clock data of the first outer clock data. The format of the second outer clock data is the same as the format of the first outer clock data, that is, as shown in FIG. 2, and details are not described herein again.

In this embodiment, the first device uses the FEC algorithm to check the updated clock data of the first external clock data sent by the second device, obtain the second verification result, and determine the first external clock data. Whether the first verification result and the second verification result are the same, if the same, when the second external clock data sent by the second device is received, synchronizing the clock of the first device according to the updated clock data The first check result is added to the first outer clock data, and the FEC algorithm is used in the first device, that is, the self-checking and self-correcting FEC check function is added, so that the single line can be effectively improved. The PPS external clock mode synchronizes the reliability of the clock and effectively reduces the jitter deviation between the clock of the first device and the clock of the second device.

FIG. 3 is a flowchart of another embodiment of an external clock data synchronization processing method according to the present invention. On the basis of the foregoing embodiment shown in FIG. 1, as shown in FIG. 3, after step 102, the method may further include the following steps. :

Step 104: If the first device determines that the first verification result is different from the second verification result, the FEC algorithm is used to perform error correction processing on the updated clock data according to the first verification result.

In this embodiment, when the first device determines that the first verification result and the second verification result are different, if the first external clock data is abnormal, the first verification result may be obtained according to the first verification result (required error and error correction). Performance index), using the FEC algorithm, performing error correction processing on the updated clock data, thereby implementing error correction on the first outer clock data multi-bit.

Step 105: The first device uses the FEC algorithm to check the updated clock data after the error correction processing, and obtain a third verification result.

Step 106: The first device determines whether the third verification result and the first verification result are the same. Step 107: If the first device determines that the third verification result is the same as the first verification result, Then, when receiving the second external clock data, the clock of the first device is synchronized according to the updated clock data after the error correction processing.

Further, after step 105, the method may further include:

Step 108: If the first device determines that the third verification result is different from the first verification result, deleting the first external clock data.

In this embodiment, the first device uses the FEC algorithm to check the updated clock data of the first external clock data sent by the second device, obtain the second verification result, and determine the first external clock data. Whether the first verification result and the second verification result are the same. If not, the FEC algorithm is used to perform error correction processing on the updated clock data, and the updated clock data after the error correction processing is verified and obtained. a third verification result, determining whether the third verification result is the same as the first verification result, and if the same, receiving the second external clock data sent by the second device, according to the error correction processing Clock data, synchronizing the clock of the first device, adding a first check result in the first outer clock data, and adopting an FEC algorithm in the first device, that is, adding self-checking and self-correcting The FEC check function can effectively improve the reliability of the synchronous clock using the single-wire PPS external clock mode, and effectively reduce the clock of the first device and the second device. Deviation between the clock jitter.

4 is a schematic structural diagram of an embodiment of an external clock data synchronization processing device according to the present invention. As shown in FIG. 4, the device in this embodiment includes: a receiving module 11, a verification module 12, and a first synchronization processing module 13, where The receiving module 11 is configured to receive the first external clock data sent by the second device, where the first external clock data includes the updated clock data and the first verification result; the verification module 12 is configured to adopt an FEC algorithm, and the update clock is used. The data is verified, the second verification result is obtained, and the first verification result is determined to be the same as the second verification result. The first synchronization processing module 13 is configured to determine the first school if the verification module 12 determines And the second verification result is the same as the second verification result, when the receiving module 11 receives the second external clock data sent by the second device, according to the updated clock data in the first external clock data, the first device The clock is synchronized; wherein the second external clock data is the next external clock data of the first external clock data.

The external clock data synchronization processing device of this embodiment can perform the technical solution of the method embodiment shown in FIG. 1, and the principles are similar, and are not described herein.

In this embodiment, the first device uses the FEC algorithm to check the updated clock data of the first external clock data sent by the second device, obtain the second verification result, and determine the first outer time. Whether the first verification result and the second verification result in the clock data are the same, and if they are the same, when receiving the second external clock data sent by the second device, according to the updated clock data, the first device is Synchronizing the clock, because the first check result is added to the first outer clock data, and the FEC algorithm is used in the first device, that is, the self-checking and self-correcting FEC check function is added, so The reliability of the synchronous clock using the single-wire PPS external clock mode is improved, and the jitter deviation between the clock of the first device and the clock of the second device is effectively reduced.

5 is a schematic structural diagram of another embodiment of an external clock data synchronization processing device according to the present invention. On the basis of the foregoing embodiment shown in FIG. 4, as shown in FIG. 5, the external clock data synchronization processing device further includes: error correction The module 14 and the second synchronization processing module 15 are configured to: if the verification module 14 determines that the difference is not the same, the FEC algorithm is used to correct the updated clock data according to the first verification result. The error check processing is further configured to: use the FEC algorithm to perform verification on the updated clock data after the error correction processing, obtain a third check result, and determine the third check result and the first check Whether the result is the same; the second synchronization processing module 15 is configured to: when the verification module 12 determines that the third verification result is the same as the first verification result, when the receiving module 11 receives the second external clock data And synchronizing the clock of the first device according to the updated clock data after the error correction processing.

Further, the device further includes: deleting the module 16, configured to delete the first external clock data if the verification module 12 determines that the third verification result is different from the first verification result.

The external clock data synchronization processing device of this embodiment can perform the technical solution of the method embodiment shown in FIG. 3, and the principle is similar, and details are not described herein.

6 is a schematic structural diagram of an embodiment of an external clock data synchronization processing system according to the present invention, the system including a first device 61 and a second device 62. The first device and the second device may perform the above described FIG. 1 or FIG. The technical solution of the method embodiment shown in FIG. 3 is similar in principle, and is not described here.

Further, the first device 61 may be an external clock data synchronization processing device shown in FIG. 4 or FIG. 5; the second device 62 is a building integrated clock supply device.

In this embodiment, the first device uses the FEC algorithm to check the updated clock data of the first external clock data sent by the second device, obtain the second verification result, and determine the first external clock data. Whether the first verification result and the second verification result are the same. If not, the FEC algorithm is used to perform error correction processing on the updated clock data, and the number of updated clocks after error correction processing is used. According to the verification, the third verification result is obtained, and it is determined whether the third verification result is the same as the first verification result. If the same, the second external clock data sent by the second device is received, according to After the error correction processing, the clock data is synchronized, and the clock of the first device is synchronized. Since the first verification result is added to the first external clock data, and the FEC algorithm is used in the first device, the self-calibration is added. The self-correcting FEC check function can effectively improve the reliability of the synchronous clock using the single-wire PPS external clock mode, and effectively reduce the jitter deviation between the clock of the first device and the clock of the second device. .

One of ordinary skill in the art will appreciate that all or a portion of the steps to implement the various method embodiments described above can be accomplished by hardware associated with the program instructions. The aforementioned program can be stored in a computer readable storage medium. The program, when executed, performs the steps including the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

Finally, it should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting thereof; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

Claim

1. An external clock data synchronization processing method, characterized in that

The first device receives the first external clock data sent by the second device, where the first external clock data includes the updated clock data and the first verification result;

2. The external clock data synchronization processing method according to claim 1, further comprising:

If the first device determines that the first verification result and the second verification result are different, performing error correction processing on the updated clock data by using an FEC algorithm according to the first verification result. ;

The first device uses the FEC algorithm to check the updated clock data after the error correction processing, obtains a third verification result, and determines whether the third verification result and the first verification result are the same. ;

If the first device determines that the third verification result is the same as the first verification result, when the second external clock data is received, according to the updated clock data after the error correction processing, The clock of the first device is synchronized.

The external clock data synchronization processing method according to claim 2, further comprising:

If the first device determines that the third verification result is different from the first verification result, deleting the first external clock data.

The external clock data synchronization processing method according to claim 1, 2 or 3, wherein the second device is a building integrated clock supply device.

5. An external clock data synchronization processing device, comprising:

a receiving module, configured to receive first external clock data sent by the second device, where the first external clock data includes updated clock data and a first verification result; a verification module, configured to perform a forward error correction FEC algorithm, perform verification on the updated clock data, obtain a second verification result, and determine whether the first verification result and the second verification result are the same a first synchronization processing module, configured to: when the verification module determines that the first verification result and the second verification result are the same, receive, by the receiving module, the second device And synchronizing the clock of the first device according to the updated clock data in the first outer clock data; wherein the second outer clock data is the first outer clock data The latter external clock data.

The external clock data synchronization processing device according to claim 5, further comprising: an error correction module and a second synchronization processing module, wherein

The error correction module is configured to: if the verification module determines that the first verification result is different from the second verification result, use an FEC algorithm according to the first verification result, Updating the clock data for error correction processing;

The verification module is further configured to: use the FEC algorithm to perform verification on the updated clock data after the error correction processing, obtain a third verification result, and determine the third verification result and the first verification Whether the results are the same;

The second synchronization processing module is configured to: when the verification module determines that the third verification result is the same as the first verification result, receiving, by the receiving module, the second outer clock data And synchronizing the clock of the first device according to the updated clock data after the error correction processing.

7. The external clock data synchronization processing device according to claim 6, further comprising:

a deleting module, configured to delete the first external clock data if the verification module determines that the third verification result is different from the first verification result.

8. An external clock data synchronization processing system, comprising: a first device and a second device;

The first device uses a forward error correction FEC algorithm to check the updated clock data, obtain a second verification result, and determine whether the first verification result and the second verification result are the same. If the first device determines that the first verification result and the second verification result are the same, when receiving the second external clock data sent by the second device, according to the first external clock Data And updating the clock of the first device, wherein the second external clock data is the next external clock data of the first external clock data.

The external clock data synchronization processing system according to claim 8, wherein the first device determines that the first verification result and the second verification result are different, according to the The first verification result is performed by using an FEC algorithm to perform error correction processing on the updated clock data. The first device uses the FEC algorithm to verify the updated clock data after the error correction processing, and obtain a third check. a result, and determining whether the third verification result and the first verification result are the same;

The external clock data synchronization processing system according to claim 9, wherein the first device deletes the first verification result if the third verification result is different from the first verification result. First external clock data.