CN113411157A - Method, slave clock device, master clock device and system for clock synchronization - Google Patents
Method, slave clock device, master clock device and system for clock synchronization Download PDFInfo
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- CN113411157A CN113411157A CN202110957439.3A CN202110957439A CN113411157A CN 113411157 A CN113411157 A CN 113411157A CN 202110957439 A CN202110957439 A CN 202110957439A CN 113411157 A CN113411157 A CN 113411157A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
Abstract
Embodiments of the present disclosure relate to methods, slave clock devices, master clock devices and systems for clock synchronization. According to the method, a first time delay between the time when a received message reaches an interface between a physical layer and an MAC layer and the time when a time stamp is acquired to be transmitted is determined, and a second time delay between the time when the time stamp is transmitted and the time when the message to be transmitted is acquired is filled in the message to be transmitted; determining an acquisition time to acquire a first transmission timestamp in the periodic message via the interface; determining a stuffing time for stuffing a second transmission time stamp in the constructed synchronization request; sending a synchronization request; acquiring an arrival timestamp in the synchronous response, wherein the arrival timestamp indicates the time of the synchronous request arriving at the master clock device; and determining a path delay with the master clock device for synchronization based on the first delay, the second delay, the fetch time, the fill-in time, the first transmit timestamp, and the arrival timestamp. Thus, the path delay can be accurately determined.
Description
Technical Field
Embodiments of the present disclosure generally relate to the field of communications, and in particular, to a method, a slave clock device, a master clock device, and a system for clock synchronization.
Background
The synchronization of the symmetric network requires the path delay of the uplink message and the downlink message to be consistent; the existing method adopts a compensation method, namely after detecting the deviation of an uplink and a downlink, compensating to meet the performance requirement after reaching a set threshold value. The above approach does not substantially solve the problem from the message path; in actual use, the symmetry of the path depends on the precision of receiving and sending the benchmarks of the Ethernet messages.
Disclosure of Invention
A method for clock synchronization, a slave clock device, a master clock device and a communication system are provided, which can accurately determine path delay and facilitate accurate synchronization.
According to a first aspect of the present disclosure, a method for clock synchronization is provided. The method comprises the following steps: determining a first time delay between a time when a received message arrives at an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired through the interface, and a second time delay between a time when the transmission time stamp is filled in a message to be transmitted and a time when the message to be transmitted is acquired through the interface; determining an acquisition time to acquire a first transmit timestamp in a periodic message from a master clock device via an interface; determining a stuffing time for stuffing a second transmission time stamp in the constructed synchronization request; sending a synchronization request to a master clock device via an interface; acquiring an arrival timestamp in a synchronous response from the master clock device, wherein the arrival timestamp indicates the time when the synchronous request arrives at the master clock device; and determining a path delay with the master clock device for synchronization with the master clock device based on the first delay, the second delay, the acquisition time, the fill-in time, the first transmit timestamp, and the arrival timestamp.
According to a second aspect of the present disclosure, a method for clock synchronization is provided. The method comprises the following steps: determining a first time delay between a time when a received message arrives at an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired through the interface, and a second time delay between a time when the transmission time stamp is filled in a message to be transmitted and a time when the message to be transmitted is acquired through the interface; determining filling time for filling the transmission time stamp in the constructed periodic message; determining a transmission timestamp in the periodic message based on the fill-in time and the second delay for transmitting the periodic message to the slave clock device; determining a fetch time at which a send timestamp in a synchronization request from a clock device is fetched via the interface; determining the arrival time of the synchronous request to the interface based on the acquisition time and the first time delay; and sending a synchronization reply including the arrival time to the slave clock device.
According to a third aspect of the present disclosure, a slave clock device is provided. The slave clock device includes: a time determination unit configured to determine a first time delay between a time when the received message reaches an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired via the interface, and a second time delay between a time when the transmission time stamp is filled in the message to be transmitted and a time when the message to be transmitted is acquired via the interface; a time determination unit further configured to determine an acquisition time at which a first transmission timestamp in a periodic message from a master clock device is acquired via an interface; a message construction unit configured to determine a filling time for filling the second transmission time stamp in the constructed synchronization request; a message construction unit configured to send a synchronization request to a master clock device via an interface; a message analysis unit further configured to obtain an arrival timestamp in the synchronization reply from the master clock device, the arrival timestamp indicating a time when the synchronization request arrived at the master clock device; and a synchronization unit configured to determine a path delay with the master clock device for synchronization with the master clock device based on the first delay, the second delay, the acquisition time, the fill-in time, the first transmit timestamp, and the arrival timestamp.
According to a fourth aspect of the present disclosure, a master clock device is provided. The master clock device includes: a time determination unit configured to determine a first time delay between a time when the received message reaches an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired via the interface, and a second time delay between a time when the transmission time stamp is filled in the message to be transmitted and a time when the message to be transmitted is acquired via the interface; a message construction unit configured to determine a filling time for filling a transmission time stamp in the constructed periodic message; a message construction unit further configured to determine a transmission timestamp in the periodic message based on the fill-in time and the second time delay for transmitting the periodic message to the slave clock device; a time determination unit further configured to determine a fetch time at which a transmission time stamp in a synchronization request from a clock device is fetched via an interface; a time determination unit further configured to determine an arrival time of the synchronization request at the interface based on the acquisition time and the first time delay; and a message construction unit configured to send a synchronization reply including the arrival time to the slave clock device.
In a fifth aspect of the present disclosure, there is provided a communication system comprising: the slave clock device according to the third aspect; and a master clock device according to the fourth aspect.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements.
Fig. 1 is a schematic block diagram of a communication system 100 in accordance with an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a method 200 for clock synchronization according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a timing sequence 300 of an interface between a physical layer and a MAC according to an embodiment of the disclosure.
Fig. 4 is a schematic diagram of a method 400 for clock synchronization according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a process 500 for clock synchronization according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As described above, the symmetry of the path depends on the accuracy of receiving and sending the benchmarks through the ethernet packet, and the accuracy of the conventional scheme is often not high.
To address, at least in part, one or more of the above issues and other potential issues, an example embodiment of the present disclosure proposes a scheme for clock synchronization. In the scheme, a first time delay between the time when a received message reaches an interface between a physical layer and a MAC layer and the time when a sending time stamp in the received message is acquired through the interface is determined from a clock device, and a second time delay between the time when the sending time stamp is filled in the message to be sent and the time when the message to be sent is acquired through the interface is determined from the clock device; determining an acquisition time to acquire a first transmit timestamp in a periodic message from a master clock device via an interface; determining a stuffing time for stuffing a second transmission time stamp in the constructed synchronization request; sending a synchronization request to a master clock device via an interface; acquiring an arrival timestamp in a synchronous response from the master clock device, wherein the arrival timestamp indicates the time when the synchronous request arrives at the master clock device; and determining a path delay with the master clock device for synchronization with the master clock device based on the first delay, the second delay, the acquisition time, the fill-in time, the first transmit timestamp, and the arrival timestamp.
The method comprises the steps that a master clock device determines a first time delay between the time when a received message reaches an interface between a physical layer and a MAC layer and the time when a sending time stamp in the received message is acquired through the interface, and a second time delay between the time when the sending time stamp is filled in the message to be sent and the time when the message to be sent is acquired through the interface; determining filling time for filling the transmission time stamp in the constructed periodic message; determining a transmission timestamp in the periodic message based on the fill-in time and the second delay for transmitting the periodic message to the slave clock device; determining a fetch time at which a send timestamp in a synchronization request from a clock device is fetched via the interface; determining the arrival time of the synchronous request to the interface based on the acquisition time and the first time delay; and sending a synchronization reply including the arrival time to the slave clock device.
In this way, the path delay between the slave clock device and the master clock device can be accurately determined, facilitating accurate synchronization, in particular of a symmetric network.
Hereinafter, specific examples of the present scheme will be described in more detail with reference to the accompanying drawings.
Fig. 1 shows a schematic block diagram of a communication system 100 according to an embodiment of the present disclosure. Communication system 100 may include a master clock device 110 and a slave clock device 120. The master clock device 110 and the slave clock device 120 may be implemented by a dedicated circuit such as a field programmable gate array.
As for the slave clock device 120, it may include a time determination unit 121, a message construction unit 122, a message analysis unit 123, and a synchronization unit 124.
As for the time determination unit 121, it may be coupled between a physical layer (PHY) and a MAC layer. The time determination unit 121 may be configured to determine a first time delay between a time when the received message reaches an interface between the physical layer and the MAC layer and a time when a transmission time stamp in the received message is acquired via the interface, and a second time delay between a time when the transmission time stamp is filled in the message to be transmitted and a time when the message to be transmitted is acquired via the interface.
The time determination unit 121 may be further configured to determine a fetch time at which the first transmission timestamp in the periodic message from the master clock device 110 is fetched via the interface.
As for the message construction unit 122, it may be located at the MAC layer. The message construction unit 122 may be configured to determine a fill-in time to fill in the constructed synchronization request with the second transmission time stamp. Message building unit 122 may also be configured to send a synchronization request to master clock device 110 via an interface.
As for the message analysis unit 123, it may be located at the MAC layer. The message analysis unit 123 may be configured to obtain an arrival timestamp in the synchronization reply from the master clock device 110, the arrival timestamp indicating the time at which the synchronization request arrived at the master clock device 110. Further, the message analyzing unit 123 may be configured to trigger the synchronizing unit 124 to synchronize with the master clock device 110 in case it is determined that the periodic message is received, and to trigger the synchronizing unit 124 to determine a path delay with the master clock device 110 in case it is determined that the synchronization reply is received.
With respect to synchronization unit 124, it may be configured to determine a path delay with master clock device 110 for synchronization with master clock device 110 based on the first delay, the second delay, the acquisition time, the fill time, the first transmission timestamp, and the arrival timestamp.
In particular, the synchronization unit 124 may be configured to determine an arrival time of the periodic message at the interface based on the acquisition time and the first time delay; determining a transmission time of the synchronization request based on the filling time and the second time delay; determining a first path delay from master clock device 110 to the current device based on the arrival time and the first transmit timestamp; determining a second path delay from the current device to the master clock device 110 based on the transmit time and the arrival timestamp; and determining a path delay with master clock device 110 based on the first path delay and the second path delay.
With respect to the master clock device 110, it may comprise a time determination unit 111 and a message construction unit 112.
As for the time determination unit 111, it may be located between the physical layer and the MAC layer. The time determination unit 111 may be configured to determine a first time delay between a time when the received message reaches an interface between the physical layer and the MAC layer and a time when a transmission time stamp in the received message is acquired via the interface, and a second time delay between a time when the transmission time stamp is filled in the message to be transmitted and a time when the message to be transmitted is acquired via the interface.
After the master clock device 110 and the slave clock device 120 are implemented by a dedicated circuit such as a field programmable gate array, the first delay and the second delay are already fixed. The first delay and the second delay may be measured in advance and stored. Determining the first delay and the second delay may include obtaining a pre-stored first delay and second delay.
The time determination unit 111 may be further configured to determine a fetch time to fetch the transmission time stamp in the synchronization request from the slave clock device 120 via the interface; and determining an arrival time of the synchronous request to the interface based on the acquisition time and the first time delay.
As for the message construction unit 112, it may be located at the MAC layer. The message constructing unit 112 may be configured to determine a filling time for filling a transmission time stamp in the constructed periodic message; based on the fill-in time and the second time delay, a transmit timestamp in the periodic message is determined for transmitting the periodic message to the slave clock device.
The message building unit 112 may also be configured to send a synchronization reply including the arrival time to the slave clock device 120.
Furthermore, the slave clock device 120 and the master clock device 110 may further comprise a Receive (RX) synchronization unit 125 and 113, respectively, for synchronizing an interface of the respective physical layer (e.g. a GMII interface) to an interface of the respective internal clock domain (MAC clock domain) (e.g. a GMII interface).
Therefore, the interface between the physical layer and the MAC layer is directly accessed by using a special circuit mode such as FPGA, the interface information is directly read by using a clock with the same frequency as the interface, the message arrival time and the message sending time are more accurately determined, and the path delay is accurately determined. The precision of the message arrival time and the message sending time can reach 2 times of the period of an interface clock between the MAC layer and the physical layer, namely the clock deviation of the physical layer output clock of a receiving path to an FPGA internal clock for example, and the deviation of the sending path such as the FPGA internal clock to the internal clock period of the physical layer. In addition, the transmission path and the receiving path are both built in a special circuit mode such as FPGA, the paths are fixed, and the path asymmetry is controllable.
Fig. 2 shows a flow diagram of a method 200 for clock synchronization according to an embodiment of the present disclosure. For example, method 200 may be performed by slave clock device 120 as shown in fig. 1. It should be understood that method 200 may also include additional blocks not shown and/or may omit blocks shown, as the scope of the present disclosure is not limited in this respect.
At block 202, the slave clock device 120 determines a first time delay between a time when the received message reaches an interface between the physical layer and the MAC layer and a time when a transmission timestamp in the received message is acquired via the interface, and a second time delay between a time when the transmission timestamp is filled in the message to be transmitted and a time when the message to be transmitted is acquired via the interface.
The interface between the physical layer and the MAC layer includes, for example, but is not limited to, a GMII interface, an RMII interface, and the like.
As shown in fig. 3, a rising edge 310 of the receive enable signal rx _ dv of the GMII interface indicates a start position of the received message rx _ d, and a first time 320 (on the receive clock rx _ clk) corresponding to the rising edge 310 indicates a time when the received message rx _ d arrives at the GMII interface. The delay between the second time 340 (on the receive clock rx _ clk) and the first time 320 to obtain the transmit timestamp 330 in the received message rx _ d via the GMII interface is the first delay.
Fig. 3 also shows that the time 360 (on the transmit clock tx clk) of the transmit timestamp 350 in the message tx _ d to be transmitted is obtained via the GMII interface, while the transmit enable signal tx en of the GMII interface remains active, e.g., high.
Thus, the first time delay between the time when the received message arrives at the interface between the physical layer and the MAC layer and the time when the sending time stamp in the received message is acquired can be accurately determined, thereby facilitating the subsequent accurate determination of the message receiving time.
At block 204, the slave clock device 120 determines a fetch time to fetch via the interface a first transmit timestamp in a periodic message from the master clock device 110.
The manner of determining the obtaining time of the first sending timestamp in the periodic message is similar to the manner of determining the second time, which can be referred to above and is not described herein again.
At block 206, the slave clock device 120 determines a fill-in time to fill in the constructed synchronization request with the second transmission timestamp.
At block 208, slave clock device 120 sends a synchronization request to master clock device 110 via the interface.
At block 210, slave clock device 120 obtains an arrival timestamp in the synchronization reply from master clock device 110, the arrival timestamp indicating the time at which the synchronization request arrived at master clock device 110.
At block 212, the slave clock device 120 determines a path delay with the master clock device based on the first delay, the second delay, the fetch time, the fill time, the first transmit timestamp, and the arrival timestamp for synchronization with the master clock device.
In particular, the slave clock device 120 may determine an arrival time of the periodic message at the interface based on the acquisition time and the first delay. For example, the acquisition time minus the first delay determines the arrival time of the periodic message at the interface.
The slave clock device 120 may also determine a transmission time of the synchronization request based on the fill-in time and the second time delay. For example, the fill time is added to the second delay to determine the time of transmission of the synchronization request.
The slave clock device 120 may then determine a first path delay from the master clock device 110 to the current device based on the arrival time of the periodic message at the interface and the first transmission timestamp.
Finally, slave clock device 120 may determine a path delay with master clock device 110 based on the first path delay and the second path delay. For example, the first path delay and the second path delay are averaged to obtain the path delay with the master clock device 110.
Therefore, the actual sending time and the actual arrival time of the message can be more accurately determined through the interface between the physical layer and the MAC layer, so that the path delay can be more accurately determined, and more accurate synchronization is facilitated.
Fig. 4 shows a flow diagram of a method 400 for clock synchronization according to an embodiment of the present disclosure. For example, method 400 may be performed by master clock device 110 as shown in FIG. 1. It should be understood that method 400 may also include additional blocks not shown and/or may omit blocks shown, as the scope of the disclosure is not limited in this respect.
At block 402, master clock device 110 determines a first time delay between a time when a received message arrives at an interface between a physical layer and a MAC layer and a time when a transmit timestamp in the received message is obtained via the interface, and a second time delay between a time when the transmit timestamp is filled in the message to be transmitted and a time when the message to be transmitted is obtained via the interface.
The interface between the physical layer and the MAC layer includes, for example, but is not limited to, a GMII interface, an RMII interface, and the like.
At block 404, master clock device 110 determines a fill-in time to fill in the constructed periodic message with the transmission timestamp.
At block 406, master clock device 110 determines a transmit timestamp in the periodic message based on the fill-in time and the second delay for transmitting the periodic message to slave clock device 120.
For example, the filling time of the built periodic message filled with the transmission time stamp is added with the second time delay, and the transmission time stamp in the periodic message is determined, so that the transmission time stamp represents the time of the periodic message actually transmitted at the interface, and is more accurate.
At block 408, master clock device 110 determines a fetch time to fetch a transmit timestamp in a synchronization request from slave clock device 120 via the interface.
The manner of determining the obtaining time of the sending timestamp in the synchronization request is similar to the manner of determining the second time, which can be referred to above and is not described herein again.
At block 410, master clock device 110 determines an arrival time of the synchronization request at the interface based on the acquisition time and the first latency.
For example, subtracting the first time delay from the acquisition time of the transmission time stamp in the synchronization request acquired from the slave clock device 120 via the interface may result in the arrival time of the synchronization request at the interface.
At block 412, master clock device 110 sends a synchronization reply including the arrival time to slave clock device 120.
Therefore, the sending time stamp in the periodic message is the time when the periodic message is actually sent at the physical layer interface, and the arrival time indicated in the synchronization response is the time when the synchronization request actually arrives at the interface, so that the slave clock device can calculate the path delay more accurately, and the synchronization is realized more accurately.
The overall process for clock synchronization is described below in conjunction with fig. 5.
At initialization, the master clock device 110 determines a first time delay MD1 between the time when a received message reaches the interface between the physical layer and the MAC layer and the time when a transmission time stamp in the received message is acquired via the interface, and a second time delay MD2 between the time when the transmission time stamp is filled in the message to be transmitted and the time when the message to be transmitted is acquired via the interface, the slave clock device 110 determines a first time delay SD1 between the time when the received message reaches the interface between the physical layer and the MAC layer and the time when the transmission time stamp in the received message is acquired via the interface, and a second time delay SD2 between the time when the transmission time stamp is filled in the message to be transmitted and the time when the message to be transmitted is acquired via the interface.
The master clock device 110 sends periodic messages 502 to the slave clock device 120 including a send timestamp t1= t11+ MD2, where t11 represents the fill-in time of the send timestamp.
The periodic message 502 from the master clock device 110 is received from the slave clock device 120, and the arrival time t2= t21-SD1 of the periodic message is determined, where t21 represents the acquisition time of the transmission time stamp in the periodic message.
The slave clock device 120 sends the synchronization request 504 to the master clock device 110, determining the sending time of the synchronization request t3= t31+ SD2, where t31 represents the fill-in time of the sending timestamp in the synchronization request.
The master clock device 110 receives the synchronization request 504 from the slave clock device 120, determines the arrival time of the synchronization request t4= t41-MD1, where t41 represents the acquisition time of the transmission timestamp in the synchronization request.
The slave clock device 120 receives the synchronization reply 506 from the master clock device 110, obtains t4, and determines the path delay between the slave clock device 120 and the master clock device 110 for synchronization based on the formula ((t2-t1) + (t4-t 3))/2.
Therefore, the interface between the physical layer and the MAC layer is directly accessed by using a special circuit mode such as FPGA, the interface information is directly read by using a clock with the same frequency as the interface, the message arrival time and the message sending time are more accurately determined, and the path delay is accurately determined. The precision of the message arrival time and the message sending time can reach 2 times of the period of an interface clock between the MAC layer and the physical layer, namely the clock deviation of the physical layer output clock of a receiving path to an FPGA internal clock for example, and the deviation of the sending path such as the FPGA internal clock to the internal clock period of the physical layer. In addition, the transmission path and the receiving path are both built in a special circuit mode such as FPGA, the paths are fixed, and the path asymmetry is controllable.
The present disclosure relates to methods, apparatuses, systems, electronic devices, computer-readable storage media and/or computer program products. The computer program product may include computer-readable program instructions for performing various aspects of the present disclosure.
In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processing unit of a special purpose computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the special purpose computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a special purpose computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer-readable program instructions may also be loaded onto a special purpose computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (7)
1. A method for clock synchronization, comprising:
determining a first time delay between a time when a received message arrives at an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired through the interface, and a second time delay between a time when the transmission time stamp is filled in a message to be transmitted and a time when the message to be transmitted is acquired through the interface;
determining an acquisition time at which a first transmit timestamp in a periodic message from a master clock device is acquired via the interface;
determining a stuffing time for stuffing a second transmission time stamp in the constructed synchronization request;
sending the synchronization request to the master clock device via the interface;
acquiring an arrival timestamp in a synchronization response from the master clock device, wherein the arrival timestamp indicates the time when the synchronization request arrives at the master clock device; and
determining a path delay with the master clock device for synchronization with the master clock device based on the first delay, the second delay, the acquisition time, the fill-in time, the first transmit timestamp, and the arrival timestamp.
2. The method of claim 1, wherein determining a path delay with the master clock device comprises:
determining an arrival time of the periodic message at the interface based on the acquisition time and the first time delay;
determining a sending time of the synchronization request based on the filling time and the second time delay;
determining a first path delay from the master clock device to a current device based on the arrival time and the first transmit timestamp;
determining a second path delay from a current device to the master clock device based on the transmit time and the arrival timestamp; and
and determining the path delay between the master clock device and the second clock device based on the first path delay and the second path delay.
3. A method for clock synchronization, comprising:
determining a first time delay between a time when a received message arrives at an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired through the interface, and a second time delay between a time when the transmission time stamp is filled in a message to be transmitted and a time when the message to be transmitted is acquired through the interface;
determining filling time for filling the transmission time stamp in the constructed periodic message;
determining a transmission timestamp in the periodic message based on the fill-in time and the second delay for transmitting the periodic message to a slave clock device;
determining a fetch time at which to fetch a transmit timestamp in a synchronization request from the slave clock device via the interface;
determining an arrival time of the synchronization request at the interface based on the acquisition time and the first time delay; and
sending a synchronization reply including the arrival time to the slave clock device.
4. A slave clock device, comprising:
a time determination unit configured to determine a first time delay between a time when a received message arrives at an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired via the interface, and a second time delay between a time when the transmission time stamp is filled in a message to be transmitted and a time when the message to be transmitted is acquired via the interface;
the time determination unit is further configured to determine an acquisition time at which a first transmission timestamp in a periodic message from a master clock device is acquired via the interface;
a message construction unit configured to determine a filling time for filling the second transmission time stamp in the constructed synchronization request;
the message building unit configured to send the synchronization request to the master clock device via the interface;
a message analysis unit further configured to obtain an arrival timestamp in a synchronization reply from the master clock device, the arrival timestamp indicating a time at which the synchronization request arrived at the master clock device; and
a synchronization unit configured to determine a path delay with the master clock device for synchronization with the master clock device based on the first delay, the second delay, the acquisition time, the fill-in time, the first transmit timestamp, and the arrival timestamp.
5. The device of claim 4, wherein the synchronization unit is further configured to:
determining an arrival time of the periodic message at the interface based on the acquisition time and the first time delay;
determining a sending time of the synchronization request based on the filling time and the second time delay;
determining a first path delay from the master clock device to a current device based on the arrival time and the first transmit timestamp;
determining a second path delay from a current device to the master clock device based on the transmit time and the arrival timestamp; and
and determining the path delay between the master clock device and the second clock device based on the first path delay and the second path delay.
6. A master clock device, comprising:
a time determination unit configured to determine a first time delay between a time when a received message arrives at an interface between a physical layer and a MAC layer and a time when a transmission time stamp in the received message is acquired via the interface, and a second time delay between a time when the transmission time stamp is filled in a message to be transmitted and a time when the message to be transmitted is acquired via the interface;
a message construction unit configured to determine a filling time for filling a transmission time stamp in the constructed periodic message;
the message construction unit is further configured to determine a sending timestamp in the periodic message based on the filling-in time and the second time delay, so as to send the periodic message to a slave clock device;
the time determination unit is further configured to determine a fetch time for fetching a transmission timestamp in a synchronization request from the slave clock device via the interface;
the time determination unit is further configured to determine an arrival time of the synchronization request at the interface based on the acquisition time and the first delay; and
the message construction unit configured to send a synchronization reply including the arrival time to the slave clock device.
7. A communication system, comprising:
the slave clock device of any of claims 4-5; and
the master clock device of claim 6.
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