CN112887046B - Digital time synchronization method and system for boundary clock and common clock - Google Patents
Digital time synchronization method and system for boundary clock and common clock Download PDFInfo
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- CN112887046B CN112887046B CN201911205265.4A CN201911205265A CN112887046B CN 112887046 B CN112887046 B CN 112887046B CN 201911205265 A CN201911205265 A CN 201911205265A CN 112887046 B CN112887046 B CN 112887046B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
Abstract
The invention discloses a digital time synchronization method and a digital time synchronization system for a boundary clock and a common clock, which relate to the technical field of packet time synchronization. Wherein the second domain bias information is provided to the time stamping unit for use in generating a local time stamp; the nanosecond domain information is provided for a synchronization protocol stack for use, and is used for correcting the local timestamp information, and synchronizing the upstream time source and sending the time information to the downstream on the basis of the local timestamp information; the method can effectively solve the problems of slow synchronous tracking process, synchronous oscillation, even incapability of convergence and the like of a Boundary Clock (BC) and a common clock (OC) in the traditional synchronous framework, and improves the synchronous response speed and stability of the system. The synchronous tracking link is reduced, the synchronous algorithm loss is reduced, and the method is beneficial to improving the synchronous precision.
Description
Technical Field
The invention relates to the technical field of packet time synchronization, in particular to a digital time synchronization method and a digital time synchronization system for a boundary clock and a common clock.
Background
High precision time synchronization is one of the key requirements for 5G bearers. Different synchronization accuracies need to be provided according to different technical implementations or service scenarios. The 5G synchronization requirement is mainly embodied in three aspects: basic service time synchronization requirements, collaborative service time synchronization requirements and new service synchronization requirements. The requirement of 5G basic service time synchronization precision is 3us, the requirement of cooperative service time synchronization precision is 300ns, and the requirements of positioning and other new service time synchronization are improved to 10 ns.
Time synchronization networks are usually networked by using Boundary Clock (BC) and common clock (OC) models. The requirement on the time synchronization precision is improved, the synchronization index distribution also has the precision requirement that max | TE | (maximum time error) <5ns on the time synchronization precision of the bearing node, and the synchronization precision, the response speed and the stability need to be considered at the same time.
Based on IEEE1588-2008, a system synchronization architecture generally adopted in the current industry needs to adjust a phase of a local time phase-locked loop according to a calculated time deviation when a Boundary Clock (BC) or an Ordinary Clock (OC) is implemented, so as to track an upstream. And then, synchronizing the time stamp unit by utilizing the synchronized time signal to finish the synchronization in the system, wherein the synchronization is used as the basis for subsequent time synchronization and sending time information to a downstream node.
Fig. 1 is a block diagram of a conventional boundary clock implementation. The above synchronization architecture adopted by the system has the following main problems:
1. in the process of synchronous tracking adjustment, because the time information is in dynamic adjustment, when the time stamp unit at the port is synchronous with the master clock module through the clock bus, the synchronous adjustment lag inevitably exists. Thus, in this process, a Precision Time Protocol (PTP) is run to track the upstream time source, and the generated timestamp information is not accurate. The inaccurate timestamp is used for synchronous calculation to obtain time deviation, and is also used for local clock tracking adjustment, so that the caused synchronous oscillation can influence the synchronous tracking process and the synchronous precision. Damping control is usually performed through an algorithm, so that the synchronous oscillation amplitude is gradually reduced, and synchronous convergence is finally realized. However, the problems of long synchronization time, oscillation of synchronization performance and the like still exist, and even the phenomenon that synchronization cannot be converged occurs.
2. Because the local clock is in the dynamic tracking adjustment, the synchronization in the system can be realized only by requiring the rapid tracking of the time stamping unit, and the design difficulty of the time stamping unit is increased. The matching degree of the adjusting algorithm of the main clock module and the time stamp unit is also a limiting factor to be considered in the design and model selection. Tracking errors caused by dynamic adjustment can affect the time synchronization precision;
3. the local clock tracks and adjusts according to the time deviation information, and the error generated in the link also influences the time synchronization precision.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method and a system for synchronizing the digitized time of a boundary clock and a common clock, so as to improve the node synchronization precision.
In order to achieve the above purposes, the technical scheme adopted by the invention is as follows: a digital time synchronization method of a boundary clock and a common clock comprises the following steps:
after the node is powered on, the local clock generates local time information and sends the local time information to each port through a clock bus;
receiving a synchronous message sent by an upstream node from a port in a clock state, generating a timestamp, carrying the timestamp and port information on the synchronous message, and forwarding the synchronous message to a synchronous protocol stack through a data bus; the synchronous protocol stack receives and transmits synchronous messages and corrects the timestamps according to the PTP protocol, and sends matched timestamp information to the synchronous deviation processing module;
the synchronous deviation processing module acquires matched timestamp information provided by a synchronous protocol stack, performs synchronous operation and generates time deviation information;
the synchronous deviation processing module provides second domain information in the time deviation information to the port time stamp unit to generate a local time stamp; and providing the nanosecond domain information in the time deviation information to a synchronous protocol stack, and correcting the local timestamp by the synchronous protocol stack according to the nanosecond domain information.
On the basis of the technical scheme, a synchronous message sent by an upstream node is received from a port in a clock state, a timestamp is generated, and the synchronous message carrying the timestamp and port information is forwarded to a synchronous protocol stack through a data bus; the synchronization protocol stack receives and transmits synchronization messages and corrects the timestamps according to a PTP (precision time protocol), and sends paired timestamp information to a synchronization deviation processing module, and the synchronization protocol stack specifically comprises the following steps:
receiving a synchronous message sent by an upstream node from a port in a clock state to generate a time stamp TSL2(ii) a Time stamp TSL2After being matched with the synchronous message, the port information is carried and transferred to a synchronous protocol stack through a data bus;
the synchronous protocol stack extracts the source time stamp field and the correction domain information from the synchronous message forwarded by the upstream node to generate a time stamp T1And generating a time stamp TS for the port by using the time deviation nanosecond informationL2Correcting to obtain time stamp T2；
The synchronous protocol stack sends a delay request message to the port through the data bus according to a set period; when the port receives the delay request message, it generatesTimestamp TSL3And time stamp TSL3Carrying port information and transferring the port information to a synchronous protocol stack through a data bus;
the synchronous protocol stack extracts the time-delay response time stamp field and the correction domain information from the time-delay response message forwarded by the upstream node to form a time stamp T4And generating a time stamp TS for the port by using the time deviation nanosecond informationL3Correcting to obtain time stamp T3；
Synchronizing timestamp information (T) of a pair to be paired by a protocol stack1、T2) And (T)3、T4) And sending the data to a synchronization deviation processing module.
On the basis of the technical proposal, the device comprises a shell,
the method comprises the following steps that the synchronous protocol stack corrects the local timestamp according to nanosecond domain information:
the synchronous protocol stack sends a synchronous message to a port in a master clock state according to a set period, extracts time deviation second domain information and adds the time deviation second domain information into a synchronous message correction domain;
the synchronization messages are transferred via a data bus to a port in the master clock state, the port time stamping unit generating a time stamp TSL1Time stamp TSL1And filling the synchronous message source timestamp field, and sending the message to a downstream slave clock port.
On the basis of the technical scheme, the synchronization protocol stack corrects the local timestamp according to the nanosecond domain information, and specifically comprises the following steps:
the port in the master clock state receives the time stamp TS generated by the delay request message sent by the port in the downstream slave clock stateL4Time, synchronization protocol stack utilizes time-biased nanosecond information to timestamp TSL4Correcting to obtain time stamp T4；
When packaging the corresponding delay response message, the timestamp T is used4Filling into a delayed response timestamp field; and transmitting the delay response message to the port in the master clock state through a data bus, and transmitting the delay response message to the opposite-end synchronous port.
On the basis of the technical scheme, when the synchronous deviation processing module provides the second domain information in the time deviation information to the port timestamp unit to complete second domain synchronization, the sending of the second domain information of the time deviation is synchronous with the second pulse of the local clock.
The invention also provides a digital time synchronization system of the boundary clock and the common clock, which comprises:
a local clock to: after the node is powered on, the local clock generates local time information and sends the local time information to each port through a clock bus;
a plurality of ports for: receiving a synchronous message sent by an upstream node, generating a timestamp, carrying the timestamp and port information on the synchronous message, and forwarding the synchronous message to a synchronous protocol stack through a data bus; each port carries out second domain synchronization according to the second domain information;
a synchronization protocol stack to: receiving and transmitting synchronous messages and correcting timestamps according to a PTP (precision time protocol), and sending paired timestamp information to a synchronous deviation processing module; the synchronous protocol stack corrects the local timestamp according to the nanosecond domain information;
a synchronization deviation processing module to: acquiring paired timestamp information provided by a synchronous protocol stack, and performing synchronous operation to generate time deviation information; providing second domain information in the time deviation information to a port timestamp unit, and providing nanosecond domain information in the time deviation information to a synchronous protocol stack;
a clock bus for: transmitting the local time information of the local clock and the time deviation information of the synchronous deviation processing module to each port;
a data bus for: the synchronization messages and timestamps are communicated between the ports and the synchronization protocol stack.
On the basis of the above technical solution, the port is specifically configured to: receiving a synchronous message sent by an upstream node from a port in a clock state to generate a time stamp TSL2(ii) a Time stamp TSL2After being matched with the synchronous message, the port information is carried and transferred to a synchronous protocol stack through a data bus; generating time stamp TS when receiving time delay request message sent by synchronous protocol stackL3And time stamp TSL3Carrying port information and transferring the port information to a synchronous protocol stack through a data bus;
the synchronization protocol stack is specifically configured to: extracting source time stamp field and correction domain information from synchronous message forwarded from upstream node to generate time stamp T1And generating a time stamp TS for the port by using the time deviation nanosecond informationL2Correcting to obtain time stamp T2(ii) a According to a set period, sending a delay request message to the port; extracting the time-delay response time stamp field and the correction domain information from the time-delay response message forwarded by the upstream node to form a time stamp T4And generating a time stamp TS for the port by using the time deviation nanosecond informationL3Correcting to obtain time stamp T3(ii) a Timestamp information (T) to be paired1、T2) And (T)3、T4) And sending the data to a synchronization deviation processing module.
On the basis of the technical scheme, the synchronization protocol stack corrects the local timestamp according to the nanosecond domain information, and the method specifically comprises the following steps:
the synchronous protocol stack sends a synchronous message to a port in a master clock state according to a set period, extracts time deviation second domain information and adds the time deviation second domain information into a synchronous message correction domain;
the synchronization messages are transferred via a data bus to a port in the master clock state, the port time stamping unit generating a time stamp TSL1Time stamp TSL1And filling the synchronous message source timestamp field, and sending the message to a downstream slave clock port.
On the basis of the technical scheme, the synchronization protocol stack corrects the local timestamp according to the nanosecond domain information, and specifically comprises the following steps:
the port in the master clock state receives the time stamp TS generated by the delay request message sent by the port in the downstream slave clock stateL4Time, synchronization protocol stack utilizes time-biased nanosecond information to timestamp TSL4Correcting to obtain time stamp T4(ii) a When packaging the corresponding delay response message, the timestamp T is used4Filling into a delayed response timestamp field; will delayThe time response message is transferred to the port of the master clock state through the data bus and is sent to the opposite end synchronous port.
On the basis of the technical scheme, when the synchronization deviation processing module provides the second domain information in the time deviation information to the port timestamp unit to complete second domain synchronization, the sending of the second domain information of the time deviation is synchronized with the second pulse of the local clock.
Compared with the prior art, the invention has the advantages that:
the time deviation information measured and calculated through a precision time algorithm (PTP) is shaped through a synchronization algorithm, and output results are stored as second domain and nanosecond domain deviation information. Wherein the second domain bias information is provided to the time stamping unit for use in generating the local time stamp. The nanosecond domain information is provided for a synchronization protocol stack for use, and is used for correcting the local timestamp information, and synchronizing the upstream time source and sending the time information to the downstream on the basis of the local timestamp information; the method can effectively solve the problems of slow synchronous tracking process, synchronous oscillation, even incapability of convergence and the like of a Boundary Clock (BC) and a common clock (OC) in the traditional synchronous framework, and improves the synchronous response speed and stability of the system. According to the invention, the local clock of the node no longer tracks the upstream time source information, and after the node is synchronized, the adjustment is not needed under normal conditions, so that frequent tracking adjustment and synchronous tracking oscillation of a timestamp unit are avoided; the synchronous tracking link is reduced, the synchronous algorithm loss is reduced, and the method is beneficial to improving the synchronous precision. And the synchronous port output interface symbol international standard can be in seamless connection with the synchronous node of the traditional scheme.
Drawings
FIG. 1 is a block diagram of a conventional boundary clock implementation of the background art;
fig. 2 is a block diagram of an implementation of the boundary clock and ordinary clock digital time synchronization method according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
The embodiment of the invention provides a digital time synchronization method of a boundary clock and a common clock, which comprises the following steps:
after the node is powered on, the local clock generates local time information and sends the local time information to each port through a clock bus;
receiving a synchronous message sent by an upstream node from a port in a clock state, generating a timestamp, carrying the timestamp and port information on the synchronous message, and forwarding the synchronous message to a synchronous protocol stack through a data bus; the synchronous protocol stack receives and transmits synchronous messages and corrects the timestamps according to the PTP protocol, and sends matched timestamp information to the synchronous deviation processing module;
the synchronous deviation processing module acquires matched timestamp information provided by a synchronous protocol stack, performs synchronous operation and generates time deviation information;
the synchronous deviation processing module provides second domain information in the time deviation information to the port time stamp unit to generate a local time stamp; and providing the nanosecond domain information in the time deviation information to a synchronous protocol stack, and correcting the local timestamp by the synchronous protocol stack according to the nanosecond domain information.
As a preferred embodiment, a synchronization message sent by an upstream node is received from a port in a clock state, a timestamp is generated, and the synchronization message carrying the timestamp and port information is forwarded to a synchronization protocol stack through a data bus; the synchronization protocol stack receives and transmits synchronization messages and corrects the timestamps according to a PTP (precision time protocol), and sends paired timestamp information to a synchronization deviation processing module, and the synchronization protocol stack specifically comprises the following steps:
receiving a synchronous message sent by an upstream node from a port in a clock state to generate a time stamp TSL2(ii) a Time stamp TSL2After being matched with the synchronous message, the port information is carried and transferred to a synchronous protocol stack through a data bus;
the synchronous protocol stack extracts the source time stamp field and the correction domain information from the synchronous message forwarded by the upstream node to generate a time stamp T1And generating a time stamp TS for the port by using the time deviation nanosecond informationL2Correcting to obtain time stamp T2；
The synchronous protocol stack sends a delay request message to the port through the data bus according to a set period; when the port receives the delay request messageGenerating a time stamp TSL3And time stamp TSL3Carrying port information and transferring the port information to a synchronous protocol stack through a data bus;
the synchronous protocol stack extracts the time-delay response time stamp field and the correction domain information from the time-delay response message forwarded by the upstream node to form a time stamp T4And generating a time stamp TS for the port by using the time deviation nanosecond informationL3Correcting to obtain time stamp T3；
Synchronizing timestamp information (T) of a pair to be paired by a protocol stack1、T2) And (T)3、T4) And sending the data to a synchronization deviation processing module.
As a preferred embodiment, the synchronization protocol stack corrects the local timestamp according to the nanosecond domain information, and specifically includes the following steps:
the synchronous protocol stack sends a synchronous message to a port in a master clock state according to a set period, extracts time deviation second domain information and adds the time deviation second domain information into a synchronous message correction domain;
the synchronization messages are transferred via a data bus to a port in the master clock state, the port time stamping unit generating a time stamp TSL1Time stamp TSL1And filling the synchronous message source timestamp field, and sending the message to a downstream slave clock port.
As a preferred embodiment, the synchronization protocol stack corrects the local timestamp according to the nanosecond domain information, and specifically includes the following steps:
the port in the master clock state receives the time stamp TS generated by the delay request message sent by the port in the downstream slave clock stateL4Time, synchronization protocol stack utilizes time-biased nanosecond information to timestamp TSL4Correcting to obtain time stamp T4；
When packaging the corresponding delay response message, the timestamp T is used4Filling into a delayed response timestamp field; and transmitting the delay response message to the port in the master clock state through a data bus, and transmitting the delay response message to the opposite-end synchronous port.
In a preferred embodiment, the synchronization deviation processing module provides the second domain information in the time deviation information to the port time stamping unit, and when the second domain synchronization is completed, the second domain information of the time deviation is transmitted in synchronization with the second pulse of the local clock.
Referring to fig. 2, an example of a process of completing synchronization by a boundary clock node according to the embodiment of the present invention is described, which includes the following specific steps:
1. after the node is powered on, the local clock generates local time information and sends the local time information to the ports 1-n through the clock bus. At this time, the second domain and nanosecond domain information of the time offset are both "0" values. The time stamp units of all ports of the node realize the synchronization with the local clock module and the second domain information of the time deviation module through a clock bus;
2. assume that port 1 is operating in a slave clock (slave) state and the precision time protocol is operating in one-step mode (one step). Receiving a synchronization message (Sync) sent by an upstream node, and generating a Time Stamp (TS)L2). After the timestamp is matched with the synchronous message, the port information is carried and transferred to a synchronous protocol stack for processing through a data bus. The synchronization protocol stack extracts the source timestamp (originTimestamp) field and the Correction Field (CF) information from the forwarded synchronization message to generate a timestamp T1And Time Stamp (TS) generated for local port 1 using time offset nanosecond informationL2) Correcting to obtain time stamp T2；
3. The synchronous protocol stack sends a Delay request message (Delay _ Req) to the port 1 according to a set period. The message arrives at port 1 via the data bus, generating a Time Stamp (TS)L3). When a Delay response message (Delay _ Resp) returned by an upstream Master clock (Master) port is received, a pairing Timestamp (TS) is matchedL3) The port information is carried and transferred to the synchronous protocol stack for processing through a data bus. The synchronous protocol stack extracts a delay response timestamp (requestReceiptTimestamp) field and correction domain (CF) information from the forwarded delay response message to form a timestamp T4. And Time Stamp (TS) generated for local port 1 using time offset nanosecond informationL3) Correcting to obtain time stamp T3；
4. Synchronizing timestamp information (T) of a pair to be paired by a protocol stack1、T2) And (T)3、T4) And sending the time information to a synchronous deviation processing module for synchronous operation to obtain time deviation information. And updating the time deviation information periodically according to the pulse per second information output by the local clock. And the second domain information in the time deviation is provided for the port timestamp unit through a clock bus to complete second domain synchronization, and the nanosecond domain information is provided for a synchronization protocol stack to realize the correction of the local timestamp. The node thus completes synchronization with the upstream time source. The synchronization algorithm can filter abnormal changes from the network in the calculation process;
5. the boundary clock has multiple synchronous ports, and the port n is assumed to work in a Master clock (Master) state. And the synchronous protocol stack sends a synchronous message (Sync) to the port n according to the set period. When the message is packaged, the information of the time deviation sodium second domain is extracted and added into a synchronous message correction domain (CF). The message is forwarded to port n via the data bus. Assuming that port n operates in one-step mode (one step), a Time Stamp (TS) is generated in a time stamp unitL1) Filling the field into a synchronous message source timestamp (originTimestamp), and sending the field to a downstream slave clock port along with the message;
6. the port n receives a Delay request message (Delay _ Req) sent by a downstream slave clock port and generates a Time Stamp (TS)L4). After the timestamp is matched with the synchronous message, the port information is carried and transferred to a synchronous protocol stack for processing through a data bus. Synchronization protocol stack utilizes time-biased nanosecond information versus Time Stamp (TS)L4) Correcting to obtain time stamp T4. When the corresponding Delay response message (Delay _ Resp) is encapsulated, the timestamp T is used4Padding to a delayed response timestamp (requestReceiptTimestamp) field. The message is transferred to the port via the data bus and then sent to the opposite end synchronous port. Therefore, the node also completes the sending of the time information to the downstream;
7. another way of synchronizing the output of time information is through a synchronization output module. The module performs time offset correction on the basis of local time, outputs a signal synchronous with a time reference source and provides the signal for other applications.
Through the implementation of the above scheme, a Boundary Clock (BC) or an Ordinary Clock (OC) synchronization node can be constructed. Due to the synchronous digitization of the nodes, the tracking adjustment of the upstream by the local clock phase is not needed, a tracking conversion link is reduced, and the improvement of the node synchronization precision is facilitated. Meanwhile, internal synchronous oscillation caused by a traditional mode is eliminated, synchronous tracking speed and stability are improved, and tracking difficulty of the time stamp unit is reduced. And the output interface symbol of the synchronous port is an international standard and can be in seamless connection with the synchronous node of the traditional scheme.
The embodiment of the invention also provides a digital time synchronization system of the boundary clock and the common clock, which comprises:
a local clock to: after the node is powered on, the local clock generates local time information and sends the local time information to each port through a clock bus;
a plurality of ports for: receiving a synchronous message sent by an upstream node, generating a timestamp, carrying the timestamp and port information on the synchronous message, and forwarding the synchronous message to a synchronous protocol stack through a data bus; each port carries out second domain synchronization according to the second domain information;
a synchronization protocol stack to: carrying out synchronous message receiving and sending and timestamp correction, and sending paired timestamp information to a synchronous deviation processing module; the synchronous protocol stack corrects the local timestamp according to the nanosecond domain information;
a synchronization deviation processing module to: acquiring paired timestamp information provided by a synchronous protocol stack, and performing synchronous operation to generate time deviation information; providing second domain information in the time deviation information to a port timestamp unit, and providing nanosecond domain information in the time deviation information to a synchronous protocol stack;
a clock bus for: transmitting the local time information of the local clock and the time deviation information of the synchronous deviation processing module to each port;
a data bus for: the synchronization messages and timestamps are communicated between the ports and the synchronization protocol stack.
The embodiment of the invention is used for realizing the Boundary Clock (BC) or the common clock (OC) defined by IEEE 1588-2008. Compared with the standard recommended framework in the background technology, the method has the advantages of simplified internal synchronization, fast and stable time synchronization, standard interface compatibility and the like. The following describes a specific embodiment with reference to fig. 2.
Fig. 2 is a block diagram of a digital synchronization implementation of a boundary clock. For a common clock, a scenario with a port number of 1 can be considered, i.e., n is 1. The functional blocks in fig. 2 are explained first:
1. local clock module
The local clock module is used for maintaining local time information.
For 5G applications, due to the requirement for accuracy of time synchronization being raised, the time synchronization scheme in the industry is normalized to complete frequency synchronization based on physical layer synchronization technologies such as synchronous ethernet (SyncE), and on the basis, time synchronization is realized through 1588v 2. The local clock frequency of the method synchronizes the upstream node through the physical layer clock.
The local clock module maintains local nanosecond domain time, the local clock module is randomly generated when initialized, and the time information is represented by a pulse per second (1PPS) phase. Unlike conventional implementations, the local nanosecond domain time does not require phase adjustment of the pulse-per-second (1PPS) based on upstream time information. In the normal operation process of the node, the local nanosecond domain time can be kept stable and cannot be adjusted.
The local clock module provides a synchronous pulse per second (1PPS) signal to the port via the clock bus.
2. Time deviation processing module
The time deviation processing module is used for calculating and maintaining time deviation information.
The module can acquire the matching timestamp information provided by the synchronous protocol stack, and forms time deviation information after the matching timestamp information is processed through the operation of the synchronization algorithm submodule. The synchronization algorithm sub-module performs the following functions:
1) and analyzing the time stamp. Analyzing the timestamp information acquired from the synchronous protocol stack, filtering abnormal data in the timestamp information, and ensuring the accuracy of a subsequent deviation calculation result;
2) and (6) smoothing operation. By adopting the filtering algorithm, the calculated time deviation information can be smoothed, so that the output time information is kept stable. Algorithm parameters can be set;
3) and outputting the time deviation information. The time deviation information is updated to be consistent with a pulse per second (1PPS) signal output by the local clock module. When the second pulse rising edge of the local clock arrives, updating the time deviation information;
because the method does not adjust the local clock, the deviation of the output of the synchronization algorithm directly represents the deviation of the local time and the upstream reference source and does not tend to be zero.
The time deviation information is divided into a second domain and a nanosecond domain, and the second domain and the nanosecond domain are respectively stored. The second domain information is transmitted to a port timestamp unit through a clock bus for use; the nanosecond domain information is provided to the synchronization protocol stack and acts on the synchronization output module. When the synchronous link is abnormal and the synchronous protocol stack can not provide enough timestamp information for synchronous operation, the second domain information can automatically maintain the addition of 1 to each second pulse; whereas the nanosecond domain information remains unchanged.
3. Synchronous protocol stack module
The synchronization protocol stack is responsible for processing a Precision Time Protocol (PTP) and finishing receiving and transmitting of a synchronization message and correction processing of a timestamp, and has the following specific functions:
1) running precision time protocol
Due to the adoption of a centralized processing mode, the PTP message is transferred through a data bus. The protocol stack needs to complete the receiving and sending of the synchronous message, the analysis and encapsulation of the message, the extraction of the protocol data and the maintenance of the integrity of the protocol according to the synchronous working state of the PTP port.
2) Timestamp correction
Because the local clock does not track the upstream time, the locally generated timestamp information needs to be corrected before accurately representing the time information and sending the time information to a downstream node or calculating the synchronization deviation. The specific method comprises the following steps:
a) for a PTP port working in a Master clock (Master) state, nanosecond domain information (T) acquired from a time deviation processing module is transmitted when a Sync message is transmittedoffset.ns) Added to the correction domain (CF), namely:
CF＝CF+Toffset.ns；
in the two-step mode (two step), nanosecond domain information (T) may also be usedoffset.ns) And adding the message into a Correction Field (CF) corresponding to the Follow message (Follow _ Up).
b) Time Stamp (TS) generated by time stamp unit for local portL) Nanosecond domain information (T) acquired from the time offset processing module needs to be addedoffset.ns) Corrected to generate time stamp information (T) in accordance with the time reference sourcen) Namely:
Tn＝TSL+Toffset.ns；
in the PTP protocol, for a PTP port operating in a Slave clock (Slave) state, for a locally generated T2And T3The time stamp needs to be corrected according to the method and then is provided to the time deviation processing module.
For PTP ports with Master clock (Master) status, for locally generated T4The timestamp needs to be corrected according to the method, and then is filled in a Delay response (Delay _ Resp) message for sending.
1) Time information interface
Two information interfaces are maintained:
a) providing paired and corrected timestamp information (T)1、T2) And (T)3、T4) The time deviation processing module is used;
b) and updating the clock data set by extracting corresponding protocol data when the message is received. When a message is packaged and sent, reading corresponding data from the clock data set and filling the corresponding data into a corresponding field of the message;
different from the traditional protocol stack distribution and port scheme, the synchronous protocol stack module adopts a centralized processing scheme and is deployed close to a time deviation processing module. Therefore, nanosecond domain information can be synchronously acquired in real time and used for correcting the time stamp.
4. Clock bus
The clock bus is used for transmitting the information of the master clock module and the time deviation processing module to all the ports (1-n) of the nodes and the synchronous output module. The method comprises the following specific steps:
transmitting local time information by using pulse per second (1 PPS);
the second domain information of the time offset is transmitted. The information is sent synchronously with the pulse per second (1PPS) of the local clock, namely when the rising edge of the pulse per second is sent, the second domain information of the time deviation is also sent;
the time information is different from the time information after the synchronization of the local clock transmitted by the clock bus in the traditional scheme.
5. Data bus
The data bus is responsible for transmitting information such as synchronous messages and timestamps between the node port and the synchronous protocol stack module. The synchronization message needs to carry a port identifier, and the timestamp information needs to be transferred in a matching manner with the corresponding message.
The time offset information transmitted by the data bus differs in the transmission content from the conventional scheme.
6. Synchronous port
The synchronous ports of the boundary clock and the common clock node need to complete the following functions:
1) synchronous message processing
And identifying a synchronous message, and distinguishing an event message from a common message, wherein the event message needs to be subjected to timestamp operation. And finishing the sending and receiving of the synchronous message to an external network and the pairing and forwarding of the internal data bus.
2) Time stamping unit
The time stamp unit realizes internal synchronization through a clock bus: and the second domain is synchronous with the second domain information of the time deviation processing unit, and the nanosecond domain is a synchronous local clock.
The timestamp unit detects the sending of the synchronization message (Sync) and generates a Timestamp (TS)L1). Time Stamp (TS)L1) And writing the source timestamp field of the payload of the synchronization message (Sync) or the accurate source timestamp field (preciseOriginginTimestamp) of the matched payload of the following message (Follow _ Up), and sending the message to the opposite node.
From the view of the opposite end node, the synchronous ports of the common clock and the boundary clock node realized by the method have no difference with the traditional realization scheme and can be completely compatible. Opposite terminalThe node obtains the Time Stamp (TS) from the synchronous message (Sync)L1) Information and Correction Field (CF) information, using a standardized operation, a timestamp (T) consistent with a time reference source is obtained1) Namely:
T1＝TSL1+CF；
7. synchronous output module
The synchronization output module provides synchronization time information for other applications. The module needs to correct the time deviation on the basis of local time and output a signal synchronous with a time reference source. The output signal of the module is not applied to the synchronization system itself.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A digital time synchronization method of a boundary clock and a common clock is characterized by comprising the following steps:
after the node is powered on, the local clock generates local time information and sends the local time information to each port through a clock bus;
receiving a synchronous message sent by an upstream node from a port in a clock state, generating a timestamp, carrying the timestamp and port information on the synchronous message, and forwarding the synchronous message to a synchronous protocol stack through a data bus; the synchronous protocol stack receives and transmits synchronous messages and corrects the timestamps according to the PTP protocol, and sends matched timestamp information to the synchronous deviation processing module;
the synchronous deviation processing module acquires matched timestamp information provided by a synchronous protocol stack, performs synchronous operation and generates time deviation information;
the synchronous deviation processing module provides second domain information in the time deviation information to the port time stamp unit to generate a local time stamp; and providing the nanosecond domain information in the time deviation information to a synchronous protocol stack, and correcting the local timestamp by the synchronous protocol stack according to the nanosecond domain information.
2. The method of claim 1, wherein:
receiving a synchronous message sent by an upstream node from a port in a clock state, generating a timestamp, carrying the timestamp and port information on the synchronous message, and forwarding the synchronous message to a synchronous protocol stack through a data bus; the synchronization protocol stack receives and transmits synchronization messages and corrects the timestamps according to a PTP (precision time protocol), and sends paired timestamp information to a synchronization deviation processing module, and the synchronization protocol stack specifically comprises the following steps:
receiving a synchronous message sent by an upstream node from a port in a clock state to generate a time stamp TSL2(ii) a Time stamp TSL2After being matched with the synchronous message, the port information is carried and transferred to a synchronous protocol stack through a data bus;
the synchronous protocol stack extracts the source time stamp field and the correction domain information from the synchronous message forwarded by the upstream node to generate a time stamp T1And generating a time stamp TS for the port by using the time deviation nanosecond informationL2Correcting to obtain time stamp T2；
The synchronous protocol stack sends a delay request message to the port through the data bus according to a set period; when the port receives the delay request message, a time stamp TS is generatedL3And time stamp TSL3Carrying port information and transferring the port information to a synchronous protocol stack through a data bus;
the synchronous protocol stack extracts the time-delay response time stamp field and the correction domain information from the time-delay response message forwarded by the upstream node to form a time stamp T4And generating a time stamp TS for the port by using the time deviation nanosecond informationL3Correcting to obtain time stamp T3；
Synchronizing timestamp information (T) of a pair to be paired by a protocol stack1、T2) And (T)3、T4) And sending the data to a synchronization deviation processing module.
3. The method of claim 1, wherein:
the method comprises the following steps that the synchronous protocol stack corrects the local timestamp according to nanosecond domain information:
the synchronous protocol stack sends a synchronous message to a port in a master clock state according to a set period, extracts time deviation second domain information and adds the time deviation second domain information into a synchronous message correction domain;
the synchronization messages are transferred via a data bus to a port in the master clock state, the port time stamping unit generating a time stamp TSL1Time stamp TSL1And filling the synchronous message source timestamp field, and sending the message to a downstream slave clock port.
4. The method of claim 1, wherein: the synchronization protocol stack corrects the local timestamp according to the nanosecond domain information, and specifically comprises the following steps:
the port in the master clock state receives the time stamp TS generated by the delay request message sent by the port in the downstream slave clock stateL4Time, synchronization protocol stack utilizes time-biased nanosecond information to timestamp TSL4Correcting to obtain time stamp T4；
When packaging the corresponding delay response message, the timestamp T is used4Filling into a delayed response timestamp field; and transmitting the delay response message to the port in the master clock state through a data bus, and transmitting the delay response message to the opposite-end synchronous port.
5. The method of claim 1, wherein: and when the synchronous deviation processing module provides the second domain information in the time deviation information to the port timestamp unit to complete second domain synchronization, the sending of the second domain information of the time deviation is synchronous with the second pulse of the local clock.
6. A boundary clock and ordinary clock digitized time synchronization system, comprising:
a local clock to: after the node is powered on, the local clock generates local time information and sends the local time information to each port through a clock bus;
a plurality of ports for: receiving a synchronous message sent by an upstream node, generating a timestamp, carrying the timestamp and port information on the synchronous message, and forwarding the synchronous message to a synchronous protocol stack through a data bus; each port carries out second domain synchronization according to the second domain information;
a synchronization protocol stack to: receiving and transmitting synchronous messages and correcting timestamps according to a PTP (precision time protocol), and sending paired timestamp information to a synchronous deviation processing module; the synchronous protocol stack corrects the local timestamp according to the nanosecond domain information;
a synchronization deviation processing module to: acquiring paired timestamp information provided by a synchronous protocol stack, and performing synchronous operation to generate time deviation information; providing second domain information in the time deviation information to a port timestamp unit, and providing nanosecond domain information in the time deviation information to a synchronous protocol stack;
a clock bus for: transmitting the local time information of the local clock and the time deviation information of the synchronous deviation processing module to each port;
a data bus for: the synchronization messages and timestamps are communicated between the ports and the synchronization protocol stack.
7. The system of claim 6, wherein:
the port is specifically configured to: receiving a synchronous message sent by an upstream node from a port in a clock state to generate a time stamp TSL2(ii) a Time stamp TSL2After being matched with the synchronous message, the port information is carried and transferred to a synchronous protocol stack through a data bus; generating time stamp TS when receiving time delay request message sent by synchronous protocol stackL3And time stamp TSL3Carrying port information and transferring the port information to a synchronous protocol stack through a data bus;
the synchronization protocol stack is specifically configured to: extracting source time stamp field and correction domain information from synchronous message forwarded from upstream node to generate time stamp T1And generating a time stamp TS for the port by using the time deviation nanosecond informationL2Correcting to obtain time stamp T2(ii) a According to a set period, sending a delay request message to the port;extracting the time-delay response time stamp field and the correction domain information from the time-delay response message forwarded by the upstream node to form a time stamp T4And generating a time stamp TS for the port by using the time deviation nanosecond informationL3Correcting to obtain time stamp T3(ii) a Timestamp information (T) to be paired1、T2) And (T)3、T4) And sending the data to a synchronization deviation processing module.
8. The system of claim 6, wherein:
the method for correcting the local timestamp by the synchronous protocol stack according to the nanosecond domain information specifically comprises the following steps:
the synchronous protocol stack sends a synchronous message to a port in a master clock state according to a set period, extracts time deviation second domain information and adds the time deviation second domain information into a synchronous message correction domain;
the synchronization messages are transferred via a data bus to a port in the master clock state, the port time stamping unit generating a time stamp TSL1Time stamp TSL1And filling the synchronous message source timestamp field, and sending the message to a downstream slave clock port.
9. The system of claim 6, wherein: the synchronization protocol stack corrects the local timestamp according to the nanosecond domain information, and specifically comprises the following steps:
the port in the master clock state receives the time stamp TS generated by the delay request message sent by the port in the downstream slave clock stateL4Time, synchronization protocol stack utilizes time-biased nanosecond information to timestamp TSL4Correcting to obtain time stamp T4(ii) a When packaging the corresponding delay response message, the timestamp T is used4Filling into a delayed response timestamp field; and transmitting the delay response message to the port in the master clock state through a data bus, and transmitting the delay response message to the opposite-end synchronous port.
10. The system of claim 6, wherein: and when the synchronous deviation processing module provides the second domain information in the time deviation information to the port timestamp unit to finish the second domain synchronization, the sending of the second domain information of the time deviation is synchronous with the second pulse of the local clock.
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