WO2012151808A1

WO2012151808A1 - Method and system for improving synchronization precision based on precision time protocol

Info

Publication number: WO2012151808A1
Application number: PCT/CN2011/078997
Authority: WO
Inventors: 万娟
Original assignee: 中兴通讯股份有限公司
Priority date: 2011-07-18
Filing date: 2011-08-26
Publication date: 2012-11-15
Also published as: CN102244572B; CN102244572A

Abstract

Disclosed are a system and a method for improving synchronization precision based on a precision time protocol, for measuring in real time a delay value when a packet passes through a hardware delay node. When the packet is a precision time protocol packet, a time stamp pressed before the precision time protocol packet enters the hardware delay node is extracted; and corresponding delay compensation is performed according to the delay value and the time stamp. Compared with the prior art, the delay value measured by using the technical solution of the present invention is more precise, so that the time stamp can be correspondingly adjusted according to the measured precise delay value when the precision time protocol packet passes through the hardware delay node and the extracted time stamp, thereby improving the synchronization precision of the precision time protocol packet.

Description

Method and system for improving synchronization accuracy based on precise clock protocol

The present invention relates to the field of communications technologies, and in particular, to a method and system for improving synchronization accuracy based on an accurate clock protocol (Precision Clock Protocol) of IEEE 1588 (accurate clock synchronization protocol standard for network measurement and control systems). . Background technique

The Accurate Clock Protocol is a distributed Ethernet accurate synchronous clock protocol defined by IEEE1588. It can realize the synchronization between various systems by using widely used and low-cost Ethernet, which greatly reduces the cost of system clock synchronization. Its synchronization accuracy can reach microseconds.

The precision clock protocol draws on NTP technology and features easy configuration, fast convergence, and low network bandwidth and resource consumption. Its main synchronization principle is to periodically synchronize the clocks of all nodes in the network through a synchronization signal, so that the Ethernet-based distributed system can be accurately synchronized, and the precise clock protocol clock synchronization technology can be applied to any group. Broadcast in the network.

The basic principles of precise clock protocol synchronization include the recording of time-issued and received time information (such precise clock protocol time information frames are also called 1588 messages or precise clock protocol messages), and a "time stamp" is added to each message. The system's top-level clock (grandmaster clock) defines the overall reference source for the system. With time recording, the slave's slave clock can calculate its own clock error and delay in the network, thus making clock adjustments and synchronizing its own clock. Go to the system top level clock for synchronization purposes.

It can be seen that the synchronization accuracy of the precise clock protocol message is closely related to the time stamp and the time information. The closer the time stamp time is to the real transmission time, the higher the synchronization precision. The timestamp should be generated as close as possible to the physical layer, which can make the generated timestamp more accurate Reflects the delivery time of the message and adds the timestamp to the subsequent message sent.

In the process of synchronizing the system based on the precise clock protocol, different timestamp points may be selected according to actual conditions, for example, the hardware layer, the software driver layer or the software application layer may be selected as a time stamp point. The most accurate method is to detect the accurate clock protocol message at the hardware layer and stamp the time stamp. Because the accuracy of the software layer stamping time is also related to the timing characteristics and load of the software operating system, the software timing is not as accurate as the hardware timing. Therefore, the current common practice of improving the synchronization accuracy of the system is as follows: The media independent interface (Media Independent Interface, ΜΠ) between the MAC layer and the physical layer chip is used as the time stamping time of the time stamp. The accuracy of the synchronization accuracy of this method depends on the timing characteristics and transmission delay characteristics of the physical layer chip.

The transmission delay of the hardware layer is relatively fixed relative to the delay of the software layer. At present, existing schemes generally calculate the hardware layer transmission delay as a fixed value. However, in fact, the hardware layer's transmission delay is not completely fixed. This is because the hardware may be upgraded or modified, so that the hardware delay after the change is not the same as the delay before the change. At the same time, the hardware itself also exists. The delay of the second level fluctuates, so the hardware delay is not completely fixed. Since the fluctuation of the hardware layer transmission delay is neglected in the prior art, there is a certain influence on the final synchronization accuracy. Summary of the invention

The main technical problem to be solved by the present invention is to provide a method and system for improving synchronization accuracy based on an accurate clock protocol, which can perform corresponding delay compensation according to a real-time measured delay value and an extracted time stamp, thereby improving an accurate clock. Synchronization accuracy of protocol packets.

In order to achieve the above object, the present invention adopts the following technical solutions:

A system for improving synchronization accuracy based on an accurate clock protocol, including:

The delay measurement module is configured to measure the delay value of the message passing through the hardware delay module in real time and send it to the delay compensation module;

a clock extraction module, configured to: when determining that the packet is a precise clock protocol packet, extract a time stamp stamped by the precise clock protocol packet before entering the hardware delay module, and send the time stamp to the The delay compensation module;

The delay compensation module is configured to perform corresponding delay compensation according to the received delay value and the time stamp.

The system further includes a physical layer message transmission module and a media independent interface module, where the physical layer message transmission module is configured to receive the message from the Ethernet, and transmit the message to the device through the media independent interface module. The hardware delay module.

The delay compensation module includes an interface communication unit and a delay compensation unit. The interface communication unit is respectively connected to the delay measurement module and the clock extraction module, and configured to receive the delay value and the time stamp. The delay compensation unit is configured to perform corresponding delay compensation according to the delay value and the time stamp.

The hardware delay module, the clock extraction module, and the delay measurement module are integrated in the same FPGA.

The hardware delay module is a first in first out module.

The delay measurement module is a counter.

The clock extraction module is a media access control module with a timestamp management function. A method for improving synchronization accuracy based on an accurate clock protocol, including:

The time delay value of the packet passing through the hardware delay node is measured in real time; when the packet is an accurate clock protocol packet, the time stamp stamped by the precise clock protocol packet before entering the hardware delay node is extracted;

Corresponding delay compensation is performed according to the delay value and the time stamp.

Before measuring the delay value, the method further includes: determining whether the physical layer receives the packet.

The process of the delay value of the real-time measurement message passing through the hardware delay node includes: marking the measurement start point signal as the measurement starting point of the delay value when the message enters the hardware delay node And, when the message is out of the hardware delay node, the tag measurement An end point signal, as a measurement end point of the delay value;

The delay value is calculated based on the measurement start point and the measurement end point.

The beneficial effects of the present invention are: performing real-time measurement of the delay value of a precise clock protocol message through a hardware delay node, and the extracted time stamp of the precise clock protocol message before entering the hardware delay node Ground delay compensation. Since the delay value generated by the precise clock protocol packet through different hardware delay modules is dynamically changed, the delay value measured by applying the present invention is more accurate, so that the accurate clock protocol message obtained according to the measurement can pass through a certain The precise delay value of the hardware delay node and the extracted time stamp adjust the corresponding time stamp, which improves the synchronization precision of the accurate clock protocol message compared with the prior art. DRAWINGS

Figure 1 is a schematic view showing the structure of the system of the present invention;

2 is a schematic structural diagram of a system according to an embodiment of the present invention;

Figure 3 is a flow chart of the method of the present invention;

4 is a flow chart of a method in accordance with an embodiment of the present invention. detailed description

The present invention will be further described in detail below with reference to the accompanying drawings.

When the system based on the precise clock protocol synchronizes the accurate clock protocol packets (PTP packets), it is considered that the transmission delay of the hardware layer is relatively fixed. Therefore, the PTP packets are stamped on the media independent interface. After the stamping and transmission at the hardware layer, the transmission delay value of the hardware layer is calculated as a fixed value.

In fact, since the transmission delay of the hardware layer also has a certain fluctuation, it is not fixed, so the synchronization accuracy of the PTP message in the existing scheme will be affected to some extent. In order to minimize the influence of transmission delay fluctuations of the hardware layer on synchronization accuracy, the present invention proposes a method and system for improving synchronization accuracy based on an accurate clock protocol. The main idea of the present invention is: Since the delay values of different PTP packets passing through the same hardware node may be different, the delay values of the same PTP packet passing through different hardware nodes may be different, and the same hardware The point in time at which the hardware delay fluctuation occurs in the node is uncertain. Therefore, by measuring the delay value of the current PTP packet passing through a hardware delay node in real time, and simultaneously extracting the timestamp of the PTP packet before passing through the hardware node, according to the delay value and the extracted timestamp, The current timestamp of the PTP packet after the hardware delay node is dynamically adjusted, so that the clock skew and delay calculation of the PTP packet are more accurate, thereby improving the synchronization precision of the PTP packet.

In accordance with this concept, the present invention proposes a system for improving synchronization accuracy based on an accurate clock protocol. As shown in FIG. 1, the system 1 includes a hardware delay module 11, a delay measurement module 12, a clock extraction module 13 and a delay compensation module 14. The hardware delay module 11 is configured to transmit packets on the packet transmission and reception path, and perform clock domain conversion on the packet to ensure that the locally obtained data is reliable. Since the hardware delay module is a delay indeterminate module, the transmission delay generated when the message passes through the hardware delay module is also uncertain.

The function of the delay measurement module 12 is to measure the time taken by the message to enter the hardware delay module 11 and the hardware delay module 11 in real time, that is, the delay value, and transmit the delay value to the delay compensation module 14. The function of the clock extraction module 13 is to extract the time stamped information of the PTP message before entering the hardware delay module 11 when determining that the packet transmitted by the hardware delay module 11 is a PTP message, and This time stamp is transmitted to the delay compensation module 14. The delay compensation module 14 dynamically adjusts the current timestamp of the PTP message output by the hardware delay module according to the received delay value and timestamp, and performs corresponding delay compensation.

The delay measurement module performs real-time measurement of the delay value of a PTP message through a hardware delay module, and the time stamp of the PTP message extracted by the clock extraction module before entering the hardware delay module, to perform corresponding delay compensation. . Since the delay value generated by the PTP message through different hardware delay modules is dynamically changed, the system of the present invention is used to measure the delay value in real time. In order to make the measurement of the delay value more accurate. Therefore, the delay compensation module can adjust the timestamp according to the precise delay value of the PTP message through a hardware delay module, and improve the synchronization precision of the PTP message compared with the prior art.

It should be noted that the delay value of the PTP packet measured by the present invention is a delay value generated when the PTP packet is time stamped and transmitted on the hardware delay module, and the PTP packet of the present invention enters. Just before the hardware delay module, it has just been stamped with a timestamp. Therefore, the timestamp information extracted by the clock extraction module is a time stamp stamped before the PTP message enters the hardware delay module.

Another point to be noted is that the delay compensation module of the present invention can be implemented in a software language and run on a CPU. In this way, the CPU can output the delay measurement module according to the delay value reported by the received delay measurement module and the time stamp reported by the clock extraction module.

The current timestamp of the PTP packet is adjusted accordingly to improve the synchronization accuracy of the PTP packet.

As shown in FIG. 2, in the actual operation of the system, the functions of the hardware delay module 11, the delay measurement module 12, and the clock extraction module 13 can be implemented by a Field Programmable Gate Array (FPGA). Implementation, that is, on the same FPGA, the above three modules are integrated. By using the FPGA, real-time measurement of the transmission delay of the Ethernet layer in the hardware layer can be realized, and the measured delay value and the extracted time stamp are reported together to the delay compensation module, thus eliminating the traditional Delay measuring instruments such as oscilloscopes are simple and convenient to use and low in cost. Moreover, the delay measurement module of the present invention can be implemented by a hardware language or by a software language, and has high versatility. The system can adapt to the network port rate and realize dynamic delay compensation under 1000M, 100M, and 10M networks. Under 125M working clock, the measurement accuracy of the delay value is 8ns. Moreover, the system can further improve the measurement accuracy of the delay value by increasing the working clock rate.

As shown in FIG. 2, in the embodiment of the present invention, the system further includes a physical layer message transmission module (PHY transmission module) 15 and a media independent interface (ΜΠ interface) module 16. The physical layer message transmission module 15 is configured to perform a packet received from the Ethernet through a media independent interface. Block 16 is transmitted to hardware delay module 11 in the FPGA. The physical layer packet transmission module receives the packet from the physical layer and adds a timestamp to the media independent interface module, so that the packet timestamp is generated as close as possible to the physical layer, and the packet transmission is more accurately reflected. time.

In the embodiment of the present invention, as shown in FIG. 2, the delay compensation module 14 includes an interface communication unit 141 and a delay compensation unit 142. The interface communication unit 141 is connected to the delay measurement module 12 and the clock extraction module 13, respectively, for receiving the transmitted delay value and time stamp, and transmitting it to the delay compensation unit 142. The delay compensation unit 142 is configured to implement an accurate clock protocol and complete the synchronization process. Specifically, according to the acquired delay value and time stamp, the data is processed according to an accurate clock protocol, and the PTP report output by the hardware delay module is dynamically adjusted. The current timestamp of the text, corresponding delay compensation, to achieve clock synchronization. For example, the time stamp of the extracted PTP message plus the measured delay value can be used as the current time stamp of the PTP message output by the hardware delay module.

In the embodiment of the present invention, as shown in FIG. 2, the hardware delay module refers to a module that generates delay fluctuations when a message passes, such as a first-in first-out FIFO module, and of course, other transmissions. A delayed hardware module is generated when the message is sent. The clock extraction module marks the message entering the FIFO module, that is, the measurement start signal when the message enters the FIFO module, and the measurement end point signal when the message output FIFO module is marked, and transmits the two signals to Delay measurement module. The delay measurement module can be a counter. Specifically, the counter uses the received measurement start signal as the measurement starting point of the delay value, and uses the measurement end point signal as the measurement end point of the delay value, and passes the phase difference between the two signals by itself. Count, to calculate the delay value. The delay value thus calculated accurately reflects the transmission time of the PTP message through the FIFO module, so that an accurate delay value can be obtained in the subsequent clock synchronization process.

It should be noted that, because the hardware delay fluctuation caused by the FIFO module is usually in the range of several tens to hundreds of ns, which is related to the depth of the FIFO module, the present invention can effectively improve the synchronization precision of the PTP message. As shown in FIG. 2, in the embodiment of the present invention, the clock extraction module is a media access control MAC module with a timestamp management function. The MAC module is configured to implement parsing of PTP packets, obtain timestamps, and complete transmission and reception of time-stamped packets according to the communication standard IEEE802.3, and transmit the extracted timestamps to the delay compensation module.

After the system shown in Figure 2 starts working, the MAC module with timestamp management starts to detect whether the FIFO module receives the message. After confirming the receipt of the message, not only the corresponding flag message enters the measurement start signal/measurement end point signal of the FIFO module/out FIFO module. At the same time, it is determined whether the packet is a PTP packet. If yes, the MAC module needs to process the packet and extract timestamp and other information. The information such as the measured delay value and the extracted time stamp is reported to the delay compensation unit through the communication interface unit, and the delay compensation unit calls the CPU resource according to the delay value obtained by the real-time measurement and the extracted time stamp, and further Corresponding delay compensation is performed to improve the synchronization performance of PTP packets.

Meanwhile, as shown in FIG. 3, the present invention also provides a method for improving synchronization accuracy based on an accurate clock protocol, including the following steps:

The real-time measurement packet passes the delay value of the hardware delay node. Meanwhile, if the packet is determined to be a precise clock protocol packet (PTP packet), the PTP packet is extracted and inserted into the hardware delay node. Timestamp

52. Perform corresponding delay compensation according to the delay value and the time stamp.

Through the above two steps, the dynamic delay compensation of PTP packets can be performed according to the timestamp of the PTP packet and the delay value obtained by real-time measurement. Compared with the calculation of the conventional layered delay value as a fixed value, the delay value of the hardware layer obtained by the invention is closer to the true delay value of the PTP message, so that the subsequent delay compensation processing is more accurate. , improve the synchronization accuracy of PTP messages.

In fact, before the measurement of the delay value, there is a judging step of judging whether a message has passed through the hardware delay node, or it can be said to determine whether the physical layer receives the message. If physics The layer does not receive the packet, that is, it does not need to perform subsequent operations, and continues to detect whether the packet is received. The delay value is measured only after the physical layer receives the packet, and the timestamp and other information are extracted when the packet is a PTP packet. If it is not a PTP packet, no subsequent delay is required. Compensation operation.

As shown in FIG. 4, it is a flowchart of a method according to an embodiment of the present invention, which is specifically:

First, it detects whether the physical layer receives the packet, and if it does not receive the packet, continues to detect. If the packet is received, the received packet is processed, and a measurement is marked when the packet enters the hardware delay node. The start point signal marks a measurement end point signal when the message leaves the hardware delay node.

Secondly, the delay value is calculated, specifically, the measurement start point signal is used as the measurement starting point for calculating the start delay value, and the measurement end point signal is used as the measurement end point calculated by the end delay value, and the delay is calculated according to the measurement start point and the measurement end point. value. At the same time, it is determined whether the packet of the hardware delay node is a PTP packet, and if it is a PTP packet, the timestamp of the PTP packet is extracted.

Finally, the current timestamp of the PTP packet is adjusted according to the calculated delay value and the extracted timestamp.

By applying the invention, the time consumed by the PTP message passing through a certain hardware delay node, that is, the delay value, can be measured in real time, and the delay value measured by the invention is more accurate than the existing solution; The PTP packet enters the timestamp of the hardware delay node and the delay value obtained by the real-time measurement, and performs dynamic delay compensation on the PTP packet outputted by the hardware delay node, thereby improving the synchronization precision of the PTP packet. It is to be understood that the specific embodiments of the invention are limited only by the description. It is to be understood by those skilled in the art that the present invention may be practiced without departing from the spirit and scope of the invention.

Claims

Claim

1. A system for improving synchronization accuracy based on an accurate clock protocol, comprising:

a clock extraction module, configured to: when determining that the packet is an accurate clock protocol packet, extract a time stamp stamped before the precise clock protocol packet enters the hardware delay module, and send the time stamp to the delay compensation Module

2. The system according to claim 1, wherein the system further comprises a physical layer message transmission module and a media independent interface module, and the physical layer message transmission module is configured to receive the message from an Ethernet. And transmitting to the hardware delay module by the media independent interface module.

3. The system according to claim 1, wherein the delay compensation module comprises an interface communication unit and a delay compensation unit; the interface communication unit is respectively connected to the delay measurement module and the clock extraction module, and is configured to Receiving the delay value and the timestamp; the delay compensation unit is configured to perform corresponding delay compensation according to the delay value and the timestamp.

4. The system according to any one of claims 1 to 3, wherein the hardware delay module, the clock extraction module, and the delay measurement module are integrated in the same FPGA.

The system according to any one of claims 1 to 3, wherein the hardware delay module is a first in first out module.

The system according to any one of claims 1 to 3, wherein the delay measurement module is a counter.

The system according to any one of claims 1 to 3, wherein the clock tear block is a media access control module having a time stamp management function.

8. A method for improving synchronization accuracy based on an accurate clock protocol, comprising: The time delay value of the packet passing through the hardware delay node is measured in real time; when the packet is an accurate clock protocol packet, the time stamp stamped by the precise clock protocol packet before entering the hardware delay node is extracted;

9. The method according to claim 8, wherein before measuring the delay value, further comprising the step of determining whether the physical layer receives the message.

10. The method according to claim 8 or 9, wherein the process of delaying the value of the real-time measurement message through the hardware delay node comprises:

When the message enters the hardware delay node, marking a measurement start signal as a measurement starting point of the delay value; and, when the message is out of the hardware delay node, marking a measurement end point signal, As the measurement end point of the delay value;