CN114221733B - Error compensation method for synchronizing time stamps - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
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Abstract
The application discloses an error compensation method for synchronizing time stamps, and belongs to the technical field of programmable logic devices. The method specifically comprises the following steps: step 101: acquiring datum point position information of message data of a physical coding sublayer receiving end in a code word searching module; step 102: acquiring message header position information of message data of the physical coding sublayer receiving end in a searching codeword module; step 103: determining the timestamp error of the message data of the receiving end of the physical coding sublayer according to the datum point position information and the message head position information; step 104: and compensating the timestamp error for the timestamp of the message data of the physical coding sublayer receiving end. By the technical scheme, the time stamp error of the message data of the receiving end of the physical coding sublayer is compensated, and the time stamp accuracy of the message data of the receiving end of the physical coding sublayer is improved.
Description
Technical Field
The application belongs to the technical field of programmable logic devices, and particularly relates to an error compensation method for synchronizing time stamps.
Background
IEEE 1588, a precision clock synchronization protocol known as the networked measurement and control system, is commonly used for time synchronization in ethernet and also for time stamp synchronization in programmable logic devices.
The physical coding sublayer receiving end in the FPGA is formed by cascading hsst quad (high-speed serial transceiver module) and emac quad (Ethernet medium access control module), in order to keep the accuracy of message data time stamps of the physical coding sublayer receiving end, a land block sync module in the emac quad is moved into the hsst quad, however, the message data of the hsst quad can shift bit positions in the message data after passing through the land block sync, so that the message head positions of the message data are changed, and when the reference points and the message head positions of the message data are used for time stamp synchronization, time stamp errors are generated in the land block sync module. Under the IEEE 1588 protocol, there are 100GB BASE-R PCS, 50GB BASE-R PCS, 40GB BASE-R PCS and 25GB BASE-R PCS, under these protocols, the timestamp of the message data will generate timestamp errors in the Lane block sync module, so the timestamp errors generated by the timestamp compensation of the message data of the receiving end based on the physical coding sublayer of these protocols need to be compensated.
Disclosure of Invention
The application aims to provide an error compensation method for synchronizing time stamps, which aims to solve the technical problem of the background technology.
In order to solve the technical problems, the technical scheme of the application is as follows:
there is provided an error compensation method of time stamp synchronization, including:
step 101: acquiring datum point position information of message data of a physical coding sublayer receiving end in a code word searching module, wherein the datum point position is defined in an IEEE 1588 protocol and is used for indicating the message data of the physical coding sublayer receiving end;
step 102: acquiring message header position information of message data of a physical coding sublayer receiving end in a searching codeword module;
step 103: determining the time stamp error of the message data of the receiving end of the physical coding sublayer according to the datum point position information and the message head position information;
step 104: and compensating the time stamp error to the time stamp of the message data of the receiving end of the physical coding sublayer.
In some embodiments, step 101 comprises:
and acquiring the reference point position information of the PCS lane format message data in a code word searching module of the physical coding sublayer receiving end, wherein the PCS lane format is a physical coding sublayer data channel format.
In some embodiments, step 101 further comprises:
acquiring reference point position information of hsst lane format message data in a searching codeword module of a physical coding sublayer receiving end, wherein the hsst lane format is a high-speed serial transceiver data channel format;
datum point position information of the message data in the pcs lane format, namely datum point position information of the message data in the hsst lane format;
the message data in the pcs lane format is converted in a searching code word module of the physical coding sublayer receiving end by the message data in the hsst lane format.
In some embodiments, step 102 comprises:
and acquiring the message header position information of the PCS Lane format message data of the physical coding sublayer receiving end in an Emac XGMII interface module of the physical coding sublayer receiving end, wherein the Emac XGMII interface is a 10Gb media independent interface of an Ethernet media access module.
In some embodiments, step 102 further comprises:
determining bit numbers separated from the datum point position and the message head position of the PCS Lane format message data of the physical coding sublayer receiving end according to the datum point position and the message head position of the PCS Lane format message data of the physical coding sublayer receiving end, namely the bit numbers separated from the datum point position and the message head position of the message data after the physical coding sublayer receiving end searches the codeword module;
and determining bit numbers with a distance between the datum point position of the hsst lane format message data in the searching codeword module of the physical coding sublayer receiving end and the message head position of the hsst lane format message data in the physical coding sublayer receiving end according to the datum point position information of the hsst lane format message data in the searching codeword module of the physical coding sublayer receiving end and the message head position information of the pcs lane format message data in the physical coding sublayer receiving end.
In some embodiments, step 103 comprises:
according to the bit number of the reference point position and the message head position of the hsst lane format message data in the searching codeword module of the physical coding sublayer receiving end and the bit number of the reference point position and the message head position of the pcs lane format message data, determining that the timestamp error of the message data converted into the pcs lane format message data in the searching codeword module of the physical coding sublayer receiving end is Q bit, namely the timestamp error of the message data of the physical coding sublayer receiving end is Q bit.
In some embodiments, comprising:
determining the time T corresponding to the time stamp error Q bit of the message data of the receiving end of the physical coding sublayer;
the time T corresponding to the time stamp error Q bit is subtracted from the time stamp of the message data of the receiving end of the physical coding sublayer to compensate the time stamp of the message data of the receiving end of the physical coding sublayer.
The application has the beneficial effects that:
the application provides a time stamp error compensation method, which is characterized in that a code word searching module at a physical coding sublayer receiving end is respectively determined by acquiring hsst lane format message data and PCS lane format message data in a code word searching module, wherein the reference point position information and the message head position information of the hsst lane format message data and the reference point position information and the bit number of the PCS lane format message data are separated, the hsst lane format message data is converted into PCS lane format message data in the code word searching module, after conversion, the reference point position of the physical coding sublayer receiving end and the bit number of the message head position are changed by Q bit, namely the time stamp error of the message data is Q bit, the time stamp error Q bit is converted into corresponding time T, and the time stamp of the message data at the physical coding sublayer receiving end is subtracted by the time T to compensate the time stamp of the message data. By the technical scheme, the time stamp error of the message data of the receiving end of the physical coding sublayer is compensated, and the time stamp accuracy of the message data of the receiving end of the physical coding sublayer is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a transmission flow chart of message data at a receiving end of a physical coding sublayer in this embodiment.
Fig. 2 is a conversion chart of converting hsst lane format message data into pcs lane format message data in this embodiment.
Fig. 3 is a time stamp error compensation chart in the present embodiment.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application provides an error compensation method for synchronizing time stamps, which comprises the following steps:
step 101: acquiring datum point position information of message data of a physical coding sublayer receiving end in a code word searching module;
step 102: acquiring message header position information of message data of a physical coding sublayer receiving end in a searching codeword module;
step 103: determining the time stamp error of the message data of the receiving end of the physical coding sublayer according to the datum point position information and the message head position information;
step 104: and compensating the time stamp error to the time stamp of the message data of the receiving end of the physical coding sublayer.
Specifically, step 101 includes:
and acquiring the reference point position information of the PCS lane format message data in a code word searching module of the physical coding sublayer receiving end, wherein the PCS lane format is a physical coding sublayer data channel format.
Specifically, step 101 further includes:
acquiring reference point position information of hsst lane format message data in a searching codeword module of a physical coding sublayer receiving end, wherein the hsst lane format is a high-speed serial transceiver data channel format;
the datum point position information of the message data in the pcs lane format is consistent with the datum point position information of the message data in the hsst lane format;
the message data in the pcs lane format is converted in a searching code word module of the physical coding sublayer receiving end by the message data in the hsst lane format.
In this embodiment, as a preferred implementation manner of this embodiment, under the 100GB BASE-R PCS protocol, in order to fully utilize bandwidths of hsst Lane and emac Lane, two 25GB emac Lanes are connected to 1 hsst Lane under the 100GB BASE-R PCS protocol. Fig. 2 is a conversion chart of converting hsst lane format message data into pcs lane format message data in this embodiment. As shown in fig. 2, the 128-bit hsst lane format message data is converted into 2 64-bit emac lane format message data by the bit_demultiplexer 1, because the emac interface of the physical coding sublayer receiving end is 66 bits, the 64-bit emac lane bit width needs to be converted into 66 bits, in the IEEE 802.3 protocol under IEEE 1588, in the mapping of the pcs lane, the conversion relationship between the emac lane and the pcs lane is 1:5, the pcs lane bit width is 66 bits, the 5-period 66-bit emac lane format message data is converted into 5-pcs lane format message data by the bit_demultiplexer 2, and then the reference point position information of the pcs lane format message data is obtained by the lane block sync module, because the reference point position information of the physical coding sublayer receiving end message data does not change, so that the position information of the pcs lane message data is the hss lane format message data.
It should be noted that, the process of converting hsst lane format message data into pcs lane format message data is a module for searching code words in the process of transmitting data of a receiving end message of a physical coding sublayer, the process of converting hsst lane format message data into 64bit emac lane format message data is converted into 66bit emac lane format message data, and the process of converting 66bit emac lane format message data with 5 periods into pcs lane format message data belongs to conventional technical means in the art, so the process of converting is not described herein, and the process of transmitting data of a receiving end message of a physical coding sublayer is shown in the transmission flow chart of receiving end message data of a physical coding sublayer in the embodiment of fig. 1 in the embodiment.
Specifically, step 102 includes:
and acquiring the message header position information of the PCS Lane format message data of the physical coding sublayer receiving end in an Emac XGMII interface module of the physical coding sublayer receiving end, wherein the Emac XGMII interface is a 10Gb media independent interface of an Ethernet media access module.
Specifically, step 102 further includes:
determining the bit number of the distance between the datum point position information and the message head position information of the PCS Lane format message data of the physical coding sublayer receiving end according to the datum point position information and the message head position information of the PCS Lane format message data of the physical coding sublayer receiving end, namely the bit number of the distance between the datum point position information and the message head position information of the message data of the physical coding sublayer receiving end after searching the code word module;
and determining bit numbers which are separated from the datum point position information of the hsst lane format message data in the searching codeword module of the physical coding sublayer receiving end and the message head position information of the hsst lane format message data in the physical coding sublayer receiving end according to the datum point position information of the hsst lane format message data in the searching codeword module of the physical coding sublayer receiving end and the message head position information of the pcs lane format message data.
In this embodiment, as a preferred implementation manner of this embodiment, under the 100GB BASE-R PCS protocol, in order to make full use of bandwidths of hsst lane and emac lane, 1 hsst lane under the 100GB BASE-R PCS protocol is connected to two emac lanes of 25GB, as shown in a physical coding sublayer receiving end packet data transmission flow chart in fig. 1, when packet data of the physical coding sublayer receiving end is transmitted to an emac XGMII interface, header position information of the physical coding sublayer receiving end packet data is obtained, and after the packet data is found in a codeword searching module of the physical coding sublayer receiving end, the packet data is transmitted in a PCS lane format at the physical coding sublayer receiving end, so that the header position information is the header position information of the PCS lane format packet data in the codeword searching module;
in the searching codeword module, the message data in hsst lane format is converted into the message data in pcs lane format, the message head position information of the message data is changed relative to the reference end position information, so that errors can be generated when the message data time stamp of the receiving end of the physical coding sublayer is calculated by using the reference end position information and the message head position information, the time stamp of the message data of the receiving end of the physical coding sublayer is compensated, in the message data in hsst lane format, the message data are ordered according to bits, and fig. 3 is a time stamp error compensation diagram in the embodiment, as shown in the input module of fig. 3, the message data sequence of one hsst lane is lane 00 bit, lane2 0bit … … lane18 bit, lane 01 bit, lane2 1bit … … bit 18 128bit, and the message data sequence of the other hsst lane is lane 10 bit, lane … … bit 19 bit, lane1 1bit 3 1bit 128bit; among the message data in the pcs lane format, the message data are ordered by lane, that is, as shown in the output module of fig. 3, one message data is in the order of lane0[65:0], lane2[65:0] … … lane18[65:0], and the other message data is in the order of lane1[65:0], lane3[65:0] … … lane19[ 65:0: 0], said pcs lane refers to lane0[65:0], lane1[65 ] of the module: 0] … … lane19[65:0];
as shown in fig. 3, the bit number between the reference point position of the hsst lane format message data in the searching codeword module of the physical coding sublayer receiving end and the message header position is n/2; as shown in fig. 3, the bit number between the reference point position and the header position of the pc s lane format message data at the receiving end of the physical coding sublayer is 66×n-n/2, that is, the bit number between the reference point position and the header position of the message data at the receiving end of the physical coding sublayer after searching the codeword module is 66×n-n/2, and lane n is lane0-lane19 in fig. 3;
as shown in fig. 3, assuming hsst lane format message data, the datum point is 00 bit in lane, and the message header position is 0bit in lane, the hsst lane format message data, the datum point position and the message header position differ by 2/2bit, i.e. 1bit; in the PCS Lane format message data, the datum point is 0bit of Lane0[65:0], the message header is 0bit of Lane2[65:0], and the difference between the datum point position and the message header position is 66 x 2-1bit.
In some embodiments, step 103 comprises:
according to the bit number of the reference point position and the message head position of the hsst lane format message data in the searching codeword module of the physical coding sublayer receiving end and the bit number of the reference point position and the message head position of the pcs lane format message data, determining that the timestamp error of the message data converted into the pcs lane format message data in the searching codeword module of the physical coding sublayer receiving end is Q bit, namely the timestamp error of the message data of the physical coding sublayer receiving end is Q bit.
In this embodiment, as a preferred implementation manner of this embodiment, under the 100GB BASE-R PCS protocol, in order to make full use of bandwidths of hsst lane and emac lane, 1 hsst lane under the 100GB BASE-R PCS protocol is connected to two emac lanes of 25GB, as shown in fig. 3, after message data in hsst lane format at the receiving end of the physical coding sublayer is converted into message data in PCS lane format in the searching codeword module, the resulting timestamp error is 66 x n-n/2bit; assuming hsst lane format message data, a datum point is in lane 00 bit, a message header position is in lane2 0bit, in the ps lane format message data, the datum point is in lane0[65:0] 0bit, the message header is in lane2[65:0] 0bit, the difference between the datum point position and the message header position is 66 x 2-1bit, namely, after the message data in the hsst lane format of a physical coding sublayer receiving end is converted into the message data in the ps lane format in a searching codeword module, the time stamp error is 66 x n-n/2bit.
In some embodiments, step 104 comprises:
determining the time T corresponding to the time stamp error Q bit of the message data of the receiving end of the physical coding sublayer;
the time T corresponding to the time stamp error Q bit is subtracted from the time stamp of the message data of the receiving end of the physical coding sublayer to compensate the time stamp of the message data of the receiving end of the physical coding sublayer.
In this embodiment, as a preferred implementation manner of this embodiment, under the 100GB BASE-R PCS protocol, in order to make full use of bandwidths of hsst lane and emac lane, 1 hsst lane under the 100GB BASE-R PCS protocol is connected to two emac lanes of 25GB, as shown in fig. 3, after the message data in hsst lane format at the receiving end of the physical coding sublayer is converted into the message data in PCS lane format in the searching codeword module, a timestamp error is generated as 66×n-n/2 bits, because a time corresponding to each bit is 1 s/(frequency×bit width), and a time corresponding to the timestamp error is [ (66×n-n/2)/(frequency×bit width) ] seconds.
It should be understood that this embodiment shows error compensation for timestamp synchronization of message data at the receiving end of the physical coding sublayer when 1 hsst lane under 100GB BASE-R PCS protocol is connected to two 25GB emac lanes in order to make full use of bandwidths of hsst lanes and emac lanes under 100GB BASE-R PCS protocol, and under IEEE 1588 protocol, there are 50GB BASE-R PCS protocol, 40GB BASE-R PCS protocol, and 25GB BASE-R PCS protocol.
In addition, the embodiment of the application shows that under the 100GB BASE-R PCS protocol, in order to fully utilize the bandwidths of hsst lane and emac lane, when 1 hsst lane under the 100GB BASE-R PCS protocol is connected with two 25GB emac lanes, error compensation is performed on the time stamp synchronization of message data of a receiving end of a physical coding sublayer, for the receiving end of the physical coding sublayer, the conversion relationship between the hsst lane and the emac lane is not limited to 1:2, the maximum bit width of the hsst lane is 50GB, the bit width of the emac lane is selected from 10GB, 25GB, 50GB and 100GB, the conversion relationship between the hsst lane and the emac lane can be freely paired based on the bandwidths, and the time stamp error compensation is still satisfied for the 50GB BASE-R PCS protocol, the 40GB BASE-R PCS protocol and the 25GB BASE-R PCS protocol.
The foregoing is a further detailed description of the application in connection with specific embodiments, and is not intended to limit the practice of the application to such description. It will be apparent to those skilled in the art that several simple deductions or substitutions can be made without departing from the spirit of the application, and the scope of the application is to be considered as the scope of the application.
Claims (6)
1. A method of error compensation for time stamp synchronization, the method comprising:
step 101: acquiring datum point position information of message data of a physical coding sublayer receiving end in a code word searching module;
step 102: acquiring message header position information of message data of the physical coding sublayer receiving end in a searching codeword module;
step 103: determining the timestamp error of the message data of the receiving end of the physical coding sublayer according to the datum point position information and the message head position information;
step 104: compensating the timestamp error for the timestamp of the message data of the physical coding sublayer receiving end;
wherein, the step 103 includes:
and determining that the timestamp error of the message data in the hsstlane format of the physical coding sublayer receiving end converted into the message data in the pcslot format in the searching codeword module is Qbit according to the bit number of the reference point of the message data in the hsstlane format in the searching codeword module and the bit number of the reference point of the message data in the pcslot format and the bit number of the message head, namely the timestamp error of the message data in the physical coding sublayer receiving end is Qbit.
2. The error compensation method of time stamp synchronization according to claim 1, wherein said step 101 comprises:
and acquiring the datum point position information of the pcslot format message data in a code word searching module of the physical coding sublayer receiving end, wherein the pcslot format is a physical coding sublayer data channel format.
3. The error compensation method of time stamp synchronization according to claim 2, wherein said step 101 further comprises:
acquiring reference point position information of hsstlane format message data in a code word searching module of the physical coding sublayer receiving end, wherein the hsstlane format is a high-speed serial transceiver data channel format;
the datum point position information of the message data in the pcslane format, namely the datum point position information of the message data in the hsstlane format;
and converting the message data in the pcslane format into a code word searching module of the receiving end of the physical coding sublayer by the message data in the hsstlane format.
4. The error compensation method of time stamp synchronization as recited in claim 3, wherein said step 102 comprises:
and acquiring the message header position information of the pcslane format message data of the physical coding sublayer receiving end in an EmacXGMII interface module of the physical coding sublayer receiving end, wherein the EmacXGMII interface is a 10Gb media independent interface of an Ethernet media access module.
5. The error compensation method of timestamp synchronization of claim 4, wherein said step 102 further comprises:
determining bit numbers separated from the datum point position and the message head position of the pcslave format message data of the physical coding sublayer receiving end according to the datum point position information and the message head position information of the pcslave format message data of the physical coding sublayer receiving end, namely the bit numbers separated from the datum point position and the message head position of the message data after the physical coding sublayer receiving end searches a code word module;
and determining bit numbers with a distance between the datum point position of the hsstlane format message data in the searching codeword module of the physical coding sublayer receiving end and the message head position of the pcslane format message data in the physical coding sublayer receiving end according to the datum point position information of the hsstlane format message data in the searching codeword module of the physical coding sublayer receiving end and the message head position information of the pcslane format message data in the physical coding sublayer receiving end.
6. The error compensation method of time stamp synchronization according to claim 1, wherein said step 104 comprises:
determining the time T corresponding to the timestamp error Qbit of the message data of the physical coding sublayer receiving end;
subtracting the time T corresponding to the time stamp error Q bit from the time stamp of the message data of the receiving end of the physical coding sublayer to compensate the time stamp of the message data of the receiving end of the physical coding sublayer.
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| CN202111620531.7A CN114221733B (en) | 2021-12-27 | 2021-12-27 | Error compensation method for synchronizing time stamps |
| PCT/CN2022/117198 WO2023124197A1 (en) | 2021-12-27 | 2022-09-06 | Timestamp synchronization error compensation method, apparatus, electronic device, and storage medium |
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| CN104113517A (en) * | 2013-04-22 | 2014-10-22 | 华为技术有限公司 | Timestamp generation method, device and system |
| CN110224775A (en) * | 2018-03-01 | 2019-09-10 | 中兴通讯股份有限公司 | A kind of method, device and equipment that temporal information determines |
| CN111245542A (en) * | 2018-11-28 | 2020-06-05 | 中兴通讯股份有限公司 | Method for acquiring time stamp and time synchronization system |
| CN111611147A (en) * | 2020-06-28 | 2020-09-01 | 中国人民解放军国防科技大学 | Method, system and medium for detecting and analyzing performance of universal interface in processor |
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| WO2023124197A1 (en) | 2023-07-06 |
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