WO2023124197A1

WO2023124197A1 - Timestamp synchronization error compensation method, apparatus, electronic device, and storage medium

Info

Publication number: WO2023124197A1
Application number: PCT/CN2022/117198
Authority: WO
Inventors: 周天浩; 宣学雷; 李宁; 曾智鸣
Original assignee: 深圳市紫光同创电子有限公司
Priority date: 2021-12-27
Filing date: 2022-09-06
Publication date: 2023-07-06
Also published as: CN114221733B; CN114221733A

Abstract

Disclosed by the present application are a timestamp synchronization error compensation method, apparatus, electronic device, and storage medium, belonging to the technical field of programmable logic devices. Specifically comprised is: obtaining reference point position information of message data of a receiving end of a physical coding sublayer in a code word searching module; obtaining message header position information of the message data of the physical coding sublayer receiving end in the code word searching module; determining a timestamp error of the physical coding sublayer receiving end message data according to the reference point position information and the message header position information; compensating the timestamp error to the timestamp of the receiving end message data of the physical coding sublayer. By means of the above technical solution, the present application compensates the timestamp error of the message data of the receiving end of the physical coding sublayer, and improves the timestamp precision of the message data of the receiving end of the physical coding sublayer.

Description

Error compensation method, device, electronic equipment and storage medium for time stamp synchronization

Cross References to Related Applications

This application claims priority to a Chinese patent application with application number CN202111620531.7 and titled "An Error Compensation Method for Time Stamp Synchronization" filed with the China Patent Office on December 27, 2021, the entire contents of which are hereby incorporated by reference In this application.

technical field

The present application belongs to the technical field of programmable logic devices, and in particular relates to a time stamp synchronization error compensation method, device, electronic equipment and storage medium.

Background technique

The full name of IEEE 1588 is a precision clock synchronization protocol for networked measurement and control systems. It is often used in time synchronization in Ethernet and in time stamp synchronization of programmable logic devices.

The receiving end of the physical coding sublayer in the FPGA is composed of hsst quad (high-speed serial transceiver module) and emac quad (Ethernet media access control module) cascaded, in order to maintain the accuracy of the time stamp of the message data at the receiving end of the physical coding sublayer The lane block sync module in the emac quad will be moved into the hsst quad. However, the message data of the hsst quad will shift the bit position in the message data after passing through the lane block sync, so that the message header of the message data When the position changes, when using the reference point of the message data and the position of the message header to synchronize the time stamp, a time stamp error will be generated in the lane block sync module. Under the IEEE 1588 protocol, there are 100GB BASE-R PCS, 50GB BASE-R PCS, 40GB BASE-R PCS, and 25GB BASE-R PCS. Under these protocols, the time stamp of the message data will be generated in the lane block sync module Therefore, it is necessary to compensate the generated time stamp error to the time stamp of the receiving end message data based on the physical coding sublayer of these protocols.

Contents of the invention

The purpose of the present application is to provide a time stamp synchronization error compensation method, device, electronic equipment and storage medium, so as to solve the technical problems of the background technology.

In order to solve the problems of the technologies described above, the technical scheme of the present application is as follows:

In the first aspect, the present application provides an error compensation method for time stamp synchronization, including:

Obtaining the message data at the receiving end of the physical coding sublayer is looking for the reference point position information in the codeword module;

Obtain the message data at the receiving end of the physical coding sublayer and search for the message header position information in the codeword module;

Determine the time stamp error of the message data at the receiving end of the physical coding sublayer according to the position information of the reference point and the position information of the message header;

Compensate the time stamp error to the time stamp of the message data at the receiving end of the physical coding sublayer.

In some embodiments, obtaining the reference point position information of the message data at the receiving end of the physical coding sublayer in the codeword module includes:

Obtain the reference point position information of the message data in the pcs lane format in the codeword search module of the receiving end of the physical coding sublayer, and the pcs lane format is the data channel format of the physical coding sublayer.

In some embodiments, the method also includes:

Obtain the reference point position information of the hsst lane format message data in the search codeword module of the receiving end of the physical coding sublayer, and the hsst lane format is a high-speed serial transceiver data channel format;

Determine the reference point position information of the pcs lane format message data according to the reference point position information of the hsst lane format message data;

Wherein, the pcs lane format message data is obtained by converting the hsst lane format message data in the code word module of the receiving end of the physical coding sublayer.

In some embodiments, obtaining the packet header position information in the codeword module of the packet data at the receiving end of the physical coding sublayer includes:

Obtain the header position information of the pcs lane format message data at the receiving end of the physical coding sublayer in the Emac XGMII interface module of the receiving end of the physical coding sublayer. The Emac XGMII interface is a 10Gb independent media interface of the Ethernet media access module.

In some embodiments, the method also includes:

According to the reference point position and the message header position of the pcs lane format message data at the receiving end of the physical coding sublayer, determine the number of bits between the reference point position and the message header position of the pcs lane format message data at the receiving end of the physical coding sublayer ;

According to the reference point position information of the hsst lane format message data in the search codeword module of the receiving end of the physical encoding sublayer and the message header position information of the pcs lane format message data of the receiving end of the physical encoding sublayer, determine the receiving end of the physical encoding sublayer The number of bits between the reference point position of the hsst lane format message data and the message header position in the end search codeword module.

In some embodiments, determining the time stamp error of the packet data at the receiving end of the physical coding sublayer according to the position information of the reference point and the position information of the packet header includes:

Find the number of bits between the reference point position of the hsst lane format message data and the message header position in the codeword module according to the receiving end of the physical coding sublayer, and the distance between the reference point position of the pcs lane format message data and the message header position Determine the number of bits of the physical coding sublayer receiving end hsst lane format message data in the search codeword module to convert the time stamp error of pcs lane format message data to Q bit, that is, the message data of the physical coding sublayer receiving end The timestamp error of is Q bit; among them, Q is a positive integer.

In some embodiments, the time stamp error is compensated for the time stamp of the message data at the receiving end of the physical coding sublayer, including:

Determine the time T corresponding to the time stamp error Q bit of the message data at the receiving end of the physical coding sublayer;

Subtract the time T corresponding to the timestamp error Q bit from the time stamp of the message data at the receiving end of the physical coding sublayer to compensate the time stamp of the message data at the receiving end of the physical coding sublayer.

In a second aspect, the present application provides an error compensation device for time stamp synchronization, the device includes:

The first obtaining unit is used to obtain the reference point position information of the message data at the receiving end of the physical coding sublayer in the code word search module;

The second obtaining unit is used to obtain the message data of the receiving end of the physical coding sublayer in the message header position information in the code word module;

A determining unit, configured to determine the time stamp error of the message data at the receiving end of the physical coding sublayer according to the reference point position information and the message header position information;

The compensation unit is configured to compensate the time stamp error for the time stamp of the message data at the receiving end of the physical coding sublayer.

In a third aspect, the present application provides an electronic device, including:

at least one processor; and,

memory communicatively coupled to at least one processor; wherein,

The memory stores instructions executable by at least one processor, and the instructions are executed by at least one processor, so that the at least one processor can execute the error compensation method for time stamp synchronization in the first aspect.

In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable the electronic device to perform the time stamp synchronization as in the first aspect. compensation method.

The beneficial effect of this application:

The present application provides a time stamp error compensation method, device, electronic equipment and storage medium, the method comprising: searching for a codeword module by obtaining hsst lane format message data and pcs lane format message data at the receiving end of the physical coding sublayer The position information of the reference point and the position information of the message header in the frame respectively determine the search codeword module at the receiving end of the physical coding sublayer, the message data in the hsst lane format, and the position information of the reference point and the message data in the pcs lane format The number of bits between the header position information, the hsst lane format message data is converted into the pcs lane format message data in the code word search module, after conversion, the message data reference point position and the message header position of the receiving end of the physical coding sublayer The number of bits apart changes by Q bit, that is, the time stamp error of the message data is Q bit, the time stamp error Q bit is converted into the corresponding time T, and the time stamp of the message data at the receiving end of the physical coding sublayer is subtracted from this time T to compensate for the timestamp of the packet data. Through the above technical solutions, the present application compensates the time stamp error of the message data at the receiving end of the physical coding sublayer, and improves the time stamp accuracy of the message data at the receiving end of the physical coding sublayer.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only for the present application For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without creative effort.

FIG. 1 is a schematic flowchart of a time stamp synchronization error compensation method provided by an embodiment of the present application.

FIG. 2 is a schematic diagram of a transmission flow of message data at a receiving end of a physical coding sublayer of a time stamp synchronization error compensation method provided by an embodiment of the present application.

FIG. 3 is a schematic diagram of converting message data in hsst lane format into message data in pcs lane format in an error compensation method for time stamp synchronization provided by an embodiment of the present application.

FIG. 4 is a schematic diagram of time stamp error compensation in a time stamp synchronization error compensation method provided by an embodiment of the present application.

FIG. 5 is a schematic structural diagram of an error compensation device for time stamp synchronization provided by an embodiment of the present application.

FIG. 6 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

FIG. 7 is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be clear that the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application. An embodiment of the present application provides an error compensation method for time stamp synchronization, please refer to FIG. 1 . FIG. 1 is a schematic flow chart of an error compensation method for time stamp synchronization provided by an embodiment of the present application. As shown in Figure 1, the method 100 includes:

Step 110: Obtain the position information of the reference point of the message data at the receiving end of the physical coding sublayer in the codeword search module.

The position of the reference point has its position specified in the IEEE 1588 protocol, which is used to indicate the message data of the receiving end of the physical coding sublayer. In this embodiment, because of the conversion of the message data format, the position of the reference point of the two formats The relative change of , caused the error.

Step 120: Obtain the message header position information of the message data at the receiving end of the physical coding sublayer in the code word search module.

Step 130: Determine the time stamp error of the packet data at the receiving end of the physical coding sublayer according to the position information of the reference point and the position information of the packet header.

Step 140: Compensate the time stamp error to the time stamp of the packet data at the receiving end of the physical coding sublayer.

Specifically, step 110 includes:

Obtain the reference point position information of the message data in the pcs lane format in the codeword search module at the receiving end of the physical coding sublayer, and the pcs lane format is the physical coding sublayer (Physical Coding Sublayer, PCS) data channel format.

Specifically, the time stamp synchronization error compensation method 100 provided in the embodiment of the present application further includes:

Obtain the reference point position information of the hsst lane format message data in the search codeword module of the receiving end of the physical coding sublayer, and the hsst lane format is a high speed serial transceiver (High speed serial transceiver, HSST) data channel format;

The reference point position information of the pcs lane format message data is consistent with the reference point position information of the hsst lane format message data, so the reference point position information of the pcs lane format message data can be determined according to the reference point position information of the hsst lane format message data location information;

The message data in the pcs lane format is converted by the message data in the hsst lane format in the code word search module at the receiving end of the physical coding sublayer.

In this embodiment, as a preferred implementation of this embodiment, under the 100GB BASE-R PCS protocol, in order to make full use of the bandwidth of the hsst lane and emac lane, one hsst lane under the 100GB BASE-R PCS protocol is connected to two 25GB emac lane. FIG. 3 is a schematic diagram of converting message data in hsst lane format into message data in pcs lane format in an error compensation method for time stamp synchronization provided by an embodiment of the present application. As shown in Figure 3, the 128bit hsst lane format message data is converted into two 64bit emac lane format message data through the bit_demultiplexer 1, because the emac interface of the receiving end of the physical coding sublayer is 66bit, so It is necessary to convert the bit width of 64bit emac lane to 66bit. In the IEEE 802.3 protocol under IEEE 1588, in the mapping of pcs lane, the conversion relationship between emac lane and pcs lane is 1:5, and the bit width of pcs lane is 66bit. 5 cycles of 66bit emac lane format message data are converted into 5 pcs lane format message data by bit_demultiplexer 2, and then the reference point position of pcs lane format message data is obtained by the lane block sync module information, because the reference point position information of the message data at the receiving end of the physical coding sublayer will not change, so the reference point position information of the message data in the pcs lane format is the reference point position information of the message data in the hsst lane format.

Emac lane is an Ethernet media access control (EMAC) data channel.

It should be noted that the process of converting message data in hsst lane format into message data in pcs lane format, the codeword module that the message data at the receiving end of the physical coding sublayer passes through in the transmission process, and the conversion of message data in hsst lane format It is 64bit emac lane format message data, 64bit emac lane format message data is converted to 66bit emac lane format message data, and the conversion process of 5 cycle 66bit emac lane format message data into pcs lane format message data, all It belongs to the usual technical means in the field, so the conversion process will not be described here. The flow chart of message data transmission at the receiving end of the physical coding sublayer is shown in Figure 2. An error compensation for time stamp synchronization provided by the embodiment of the present application A schematic diagram of the transmission process of the message data at the receiving end of the physical coding sublayer of the method.

Specifically, step 120 includes:

According to the reference point position information and message header position information of the pcs lane format message data at the receiving end of the physical coding sublayer, determine the distance between the reference point position information and the message header position information of the pcs lane format message data at the receiving end of the physical coding sublayer The number of bits;

According to the reference point position information of the hsst lane format message data in the search codeword module of the receiving end of the physical encoding sublayer and the message header position information of the pcs lane format message data of the receiving end of the physical encoding sublayer, determine the receiving end of the physical encoding sublayer The number of bits between the reference point position information and the message header position information of the hsst lane format message data in the codeword module of the terminal.

In this embodiment, as a preferred implementation of this embodiment, under the 100GB BASE-R PCS protocol, in order to make full use of the bandwidth of the hsst lane and emac lane, one hsst lane under the 100GB BASE-R PCS protocol is connected to two 25GB emac lane, the message data transmission flow chart of the receiving end of the physical coding sublayer shown in Figure 2, when the message data of the receiving end of the physical coding sublayer is transmitted to the emac XGMII interface, the message of the receiving end of the physical coding sublayer is obtained The message header position information of the data, the message data is transmitted in the pcs lane format at the receiving end of the physical coding sublayer after the codeword module is searched at the receiving end of the physical coding sublayer. Therefore, the message header position information is the codeword searching The message header position information of the pcs lane format message data in the module;

In the code word search module, the hsst lane format message data is converted into pcs lane format message data, and the message header position information of the message data changes relative to the reference end position information. Therefore, when using the reference point position information and the report Errors will occur when calculating the timestamp of the message data at the receiving end of the physical coding sublayer based on the position information of the header. Sorting, Figure 4 is a schematic diagram of time stamp error compensation of a time stamp synchronization error compensation method provided by the embodiment of the present application, as shown in the input module of Figure 4, the message data sequence of an hsst lane is lane0 0bit, lane2 0bit ...lane18 0bit, lane0 1bit, lane2 1bit...lane 18 128bit, the data sequence of another hsst lane is lane1 0bit, lane3 0bit...lane19 0bit, lane1 1bit, lane3 1bit...lane19 128bit; in pcs lane format In the message data, the message data is sorted by lane, that is, as shown in the output module in Figure 4, the order of a message data is lane0[65:0], lane2[65:0]...lane18[65:0] , the order of another message data is lane1[65:0], lane3[65:0]...lane19[65:0], the pcs lane refers to the module’s lane0[65:0], lane1[65:0] ]...lane19[65:0];

As shown in Figure 4, the number of bits between the reference point position of the hsst lane format message data and the message header position in the search codeword module of the receiving end of the physical encoding sublayer is n/2; as shown in Figure 4, the physical encoding The number of bits between the reference point position of the pcs lane format message data at the receiving end of the sublayer and the position of the message header is 66*n-n/2, that is, the reference point of the message data after the receiving end of the physical coding sublayer searches for the codeword module The number of bits between the point position and the message header position is 66*n-n/2, and lane n is lane0-lane19 in Figure 4;

As shown in Figure 4, assuming that the hsst lane format message data, the reference point is at lane00bit, and the packet header position is at lane 20bit, then the hsst lane format message data, the reference point position and the packet header position differ by 2/2bit, that is, 1bit ;In the pcs lane format message data, the reference point is at 0bit of lane0[65:0], and the packet header is at 0bit of lane2[65:0]. The difference between the reference point and the packet header is 66*2-1bit.

In some embodiments, step 130 includes:

In this embodiment, as a preferred implementation of this embodiment, under the 100GB BASE-R PCS protocol, in order to make full use of the bandwidth of the hsst lane and emac lane, one hsst lane under the 100GB BASE-R PCS protocol is connected to two 25GB emac lane, as shown in Figure 4, after the hsst lane format message data at the receiving end of the physical coding sublayer is converted into pcs lane format message data in the codeword search module, the resulting time stamp error is 66*n-n/2bit ; Assume that the hsst lane format message data, the reference point is at lane00bit, and the packet header position is at lane 20bit, then in the pcs lane format message data, the reference point is at 0bit of lane0[65:0], and the packet header is at lane2[ 0bit at 65:0], the difference between the reference point position and the message header position is 66*2-1bit, that is, after the message data in hsst lane format at the receiving end of the physical coding sublayer is converted into message data in pcs lane format in the codeword search module , resulting in a timestamp error of 66*n-n/2bit.

In some implementation manners, if n/2 in the formula for calculating the timestamp error: 66*n-n/2bit is not an integer, it may be an integer according to a preset rule. Exemplarily, the preset rule is a rounding rule, and n/2 is 4.5 bits, then it is determined according to the preset rules that n/2 is 5 bits.

In some embodiments, step 140 includes:

In this embodiment, as a preferred implementation of this embodiment, under the 100GB BASE-R PCS protocol, in order to make full use of the bandwidth of the hsst lane and emac lane, one hsst lane under the 100GB BASE-R PCS protocol is connected to two 25GB emac lane, as shown in Figure 4, after the hsst lane format message data at the receiving end of the physical coding sublayer is converted into pcs lane format message data in the codeword search module, the resulting time stamp error is 66*n-n/2bit , because the time corresponding to each bit is 1s/(frequency*bit width), the time corresponding to the timestamp error is [(66*n-n/2)/(frequency*bit width)] seconds.

It should be understood that this embodiment shows that under the 100GB BASE-R PCS protocol, in order to fully utilize the bandwidth of the hsst lane and emac lane, when one hsst lane under the 100GB BASE-R PCS protocol is connected to two 25GB emac lanes , error compensation for time stamp synchronization error of message data at the receiving end of the physical coding sublayer, under the IEEE 1588 protocol, there are also 50GB BASE-R PCS protocol, 40GB BASE-R PCS protocol, 25GB BASE-R PCS protocol, this application The error compensation method proposed for timestamp synchronization is also applicable to these protocols.

In addition, the embodiment of the present application shows that under the 100GB BASE-R PCS protocol, in order to make full use of the bandwidth of the hsst lane and emac lane, one hsst lane under the 100GB BASE-R PCS protocol is connected to two 25GB When using the emac lane, the time stamp synchronization error compensation for the receiving end of the physical coding sublayer is compensated. For the receiving end of the physical coding sublayer, the conversion relationship between hsst lane and emac lane is not limited to 1:2. The hsst lane The maximum bit width is 50GB, and the bit width of emac lane has 10GB, 25GB, 50GB, and 100GB options. The conversion relationship between hsst lane and emac lane can be freely matched based on this. For 50GB BASE-R PCS protocol, 40GB BASE-R The time stamp error compensation of the PCS protocol and the 25GB BASE-R PCS protocol, these pairing relationships still hold.

Please refer to FIG. 5 again. FIG. 5 is a schematic structural diagram of an error compensation device for time stamp synchronization provided by an embodiment of the present application. As shown in FIG. 5 , the error compensation apparatus 200 for timestamp synchronization includes: a first acquisition unit 210 , a second acquisition unit 220 , a determination unit 230 and a compensation unit 240 .

The first acquiring unit 210 is configured to acquire the position information of the reference point of the packet data at the receiving end of the physical coding sublayer in the codeword search module.

The second acquisition unit 220 is configured to sample the second time stamp pulse signal input to the message receiving end to the source clock, and the second time stamp pulse signal is used to indicate the position of the reference point during the message data transmission process of the message receiving end.

The determining unit 230 is configured to determine the timestamp error of the packet data at the receiving end of the physical coding sublayer according to the position information of the reference point and the position information of the packet header.

The compensation unit 240 is configured to compensate the time stamp error for the time stamp of the packet data at the receiving end of the physical coding sublayer.

It should be noted that, for the device-type embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for relevant parts, refer to the part of the description of the method embodiments. Any of the processing methods described in the method embodiments can be implemented by corresponding processing modules in the device embodiments, and details will not be repeated in the device embodiments.

In addition, each functional module in each embodiment of the present application may be integrated into one processing module, each module may exist separately physically, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.

Please refer to FIG. 6 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present application. As shown in FIG. 6 , the electronic device 300 includes: one or more processors 310 and a memory 320 , and one processor 310 is taken as an example in FIG. 6 .

The processor 310 and the memory 320 may be connected through a bus or in other ways, and connection through a bus is taken as an example in FIG. 6 .

The processor 310 is configured to obtain the reference point position information of the message data at the receiving end of the physical coding sublayer in the codeword module; obtain the message header position information of the message data at the receiving end of the physical coding sublayer in the codeword module ; Determine the time stamp error of the message data at the receiving end of the physical coding sublayer according to the position information of the reference point and the position information of the message header; compensate the time stamp error for the time stamp of the message data at the receiving end of the physical coding sublayer.

The memory 320, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs and modules, such as the error compensation method for time stamp synchronization in the embodiment of the present application program instructions/modules. The processor 310 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions and modules stored in the memory 320 , that is, implements the error compensation method for time stamp synchronization in the above method embodiment.

The memory 320 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created according to the use of the electronic device, and the like. In addition, the memory 320 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 320 may optionally include memory located remotely from the processor 310, and these remote memories may be connected to the controller through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

One or more modules are stored in the memory 320, and when executed by one or more processors 310, execute the error compensation method for time stamp synchronization in any of the above method embodiments.

Please refer to FIG. 7 , which is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present application. The computer-readable storage medium 400 stores a program code 410, and the program code 410 can be invoked by a processor to execute the time stamp synchronization error compensation method described in the above method embodiments.

The computer readable storage medium 400 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium 400 has a storage space for program codes for executing any method steps in the error compensation method for time stamp synchronization described above. These program codes can be read from or written into one or more computer program products. The program code can eg be compressed in a suitable form.

The above content is a further detailed description of the present application in combination with specific implementation modes, and it cannot be determined that the specific implementation of the present application is only limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, some simple deduction or substitutions can be made without departing from the concept of this application, which should be regarded as the protection scope of this application.

Claims

An error compensation method for time stamp synchronization, wherein the method includes:

Obtaining the message data at the receiving end of the physical coding sublayer is looking for the reference point position information in the codeword module;

Obtaining the message data at the receiving end of the physical coding sublayer is looking for message header position information in the codeword module;

determining the time stamp error of the message data at the receiving end of the physical coding sublayer according to the position information of the reference point and the position information of the message header;

Compensating the time stamp error to the time stamp of the packet data at the receiving end of the physical coding sublayer.
The error compensation method for time stamp synchronization according to claim 1, wherein said obtaining the message data of the receiving end of the physical coding sublayer is looking for reference point position information in the codeword module, comprising:

Obtain the reference point position information of the pcs lane format message data in the code word module of the receiving end of the physical coding sublayer, and the pcs lane format is the data channel format of the physical coding sublayer.
The error compensation method for time stamp synchronization according to claim 2, wherein said method further comprises:

Obtain the reference point position information of the hsst lane format message data in the search codeword module of the receiving end of the physical coding sublayer, and the hsst lane format is a high-speed serial transceiver data channel format;

Determine the reference point position information of the pcs lane format message data according to the reference point position information of the hsst lane format message data;

Wherein, the message data of the pcs lane format is obtained by converting the message data of the hsst lane format in the code word search module of the receiving end of the physical coding sublayer.
The error compensation method for time stamp synchronization according to any one of claims 1-3, wherein said obtaining the message data at the receiving end of the physical coding sublayer is looking for the message header position information in the codeword module, including :

Obtain the message header position information of the pcs lane format message data of the physical encoding sublayer receiving end in the Emac XGMII interface module of the receiving end of the physical encoding sublayer, and the Emac XGMII interface is an independent 10Gb of the Ethernet media access module interface to the media.
The error compensation method for time stamp synchronization according to claim 4, wherein the method further comprises:

According to the reference point position information and the message header position information of the pcs lane format message data of the receiving end of the physical coding sublayer, determine the reference point position and the message header of the pcs lane format message data of the receiving end of the physical coding sublayer The number of bits apart from each other;

According to the reference point position information of the hsst lane format message data in the code word module of the receiving end of the physical coding sublayer and the message header position information of the pcs lane format message data of the physical coding sublayer receiving end, determine the The number of bits between the reference point position of the hsst lane format message data in the search codeword module of the receiving end of the physical coding sublayer and the message header position.
The error compensation method for time stamp synchronization according to any one of claims 1-5, wherein said receiving end message of said physical coding sublayer is determined according to said reference point position information and said message header position information Timestamp errors of data, including:

According to the number of bits apart from the reference point of the hsst lane format message data in the receiving end of the physical coding sublayer and the message header position in the codeword module, and the reference point position and the message header position of the pcs lane format message data The number of bits apart determines that the timestamp error of the hsst lane format message data at the receiving end of the physical coding sublayer converted into pcs lane format message data in the codeword module is Q bit, that is, the physical coding sublayer The time stamp error of the message data at the receiving end is Q bit; where, Q is a positive integer.
The error compensation method for timestamp synchronization according to any one of claims 1-6, wherein said compensating the timestamp error for the timestamp of the message data at the receiving end of the physical coding sublayer comprises:

Determine the time T corresponding to the timestamp error Q bit of the physical coding sublayer receiving end message data;

The time T corresponding to the time stamp error Q bit is subtracted from the time stamp of the message data at the receiving end of the physical coding sublayer to compensate the time stamp of the message data at the receiving end of the physical coding sublayer.
An error compensation device for time stamp synchronization, wherein the device includes:

The first obtaining unit is used to obtain the reference point position information of the message data at the receiving end of the physical coding sublayer in the code word search module;

The second obtaining unit is used to obtain the message header position information of the message data at the receiving end of the physical coding sublayer in the code word search module;

A determining unit, configured to determine the time stamp error of the packet data at the receiving end of the physical coding sublayer according to the position information of the reference point and the position information of the packet header;

A compensation unit, configured to compensate the time stamp error for the time stamp of the packet data at the receiving end of the physical coding sublayer.
An electronic device, comprising:

at least one processor; and,

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can perform the method described in any one of claims 1-7. An error compensation method for timestamp synchronization.
A computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable an electronic device to execute the time stamp according to any one of claims 1-7 Synchronous error compensation method.