CN113228564A

CN113228564A - Stamping processing method and device

Info

Publication number: CN113228564A
Application number: CN201880100455.7A
Authority: CN
Inventors: 林涛; 刘永志; 史永杰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-12-24
Filing date: 2018-12-24
Publication date: 2021-08-06
Anticipated expiration: 2038-12-24
Also published as: CN113228564B; WO2020132834A1

Abstract

The application relates to the technical field of communication, and discloses a stamping processing method and device, which are used for improving the accuracy of stamping processing and further ensuring the accuracy of delay measurement. The method comprises the following steps: respectively inputting a first timestamp into a plurality of PTP messages received by the Ethernet port by the network node; the Ethernet port is provided with a plurality of lanes, and the plurality of PTP messages are received by the network node through the plurality of lanes; after the plurality of PTP messages cross a clock domain, the network node respectively inputs first time stamp values of first time stamps into the plurality of PTP messages and updates the first time stamp values into target time stamp values corresponding to target PTP messages received by a target Lane in the plurality of LANes; and the network node determines the time delay between the network node and the network node for sending the plurality of PTP messages according to the difference value between the timestamp value of the target and the timestamp values of the sending timestamps of the plurality of PTP messages.

Description

Stamping processing method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for processing a stamp.

Background

With the continuous increase of the speed of the ethernet port, the bandwidth of the ethernet port that needs to support a precision time synchronization protocol (PTP) is also increasing, such as 100 Gigabit Ethernet (GE), 200GE, and 400GE, and the current ethernet port of a single data path (lane) is not enough to support the deployment of PTP protocol functions, and PTP protocol functions need to be deployed at the ethernet ports of multiple lanes. When a multi-lane ethernet port applies a PTP message to measure the delay between two network nodes, for the sending direction, the PTP protocol requires that multiple lanes of the same ethernet port are necessarily sent in alignment, that is, the timestamp values of the timestamps sent by multiple PTP messages of the same beat of the multiple lanes of the same ethernet port are the same, and are affected by the transmission environments of the multiple lanes, such as fiber transmission of the multiple lanes, and the like, the multiple lanes cannot guarantee the delay to be consistent, so the PTP protocol defines that, in the receiving direction, the timestamp values of the timestamps of the PTP messages received by the multiple lanes need to be compensated and aligned to the same reference lane, and the currently defined reference lane is the lane with the longest delay.

In the prior art, in the receiving direction, a network node performs delay difference alignment on PTP messages received by each lane of an ethernet port through a delay difference alignment buffer (deskew fifo), wherein fifo refers to a first input first output buffer (first input first output), after the network node buffers the PTP message received by each lane through deskew fifo, reading out the PTP message received by each lane through deskew fifo, the network node is used for aligning the delay differences of the PTP messages received by each lane, the network node reads out the time according to the PTP messages received by each lane, generating a time stamp for receiving the PTP message according to the difference value of the time length of the PTP message cached in the deskew fifo, and according to the delay difference of the plurality of lanes relative to the reference lane, compensating the timestamp values of the timestamps of the PTP messages received by the plurality of lanes to the timestamp values of the timestamps of the PTP messages received by the reference lane so as to measure the delay among the network nodes.

However, the situation of asynchronous deskew fifo may occur in various scenarios, for example, when a multi-rate ethernet port mixes with a same set of Media Access Control (MAC) logic, a write clock (wr _ clk) followed by deskew fifo writing a PTP packet and a read clock (rd _ clk) followed by reading a PTP packet occur in the ethernet port of the network node, for the asynchronous deskew fifo, the PTP packet crosses a clock domain during the deskew fifo, and the timestamp generated by the network node for receiving the PTP packet is inaccurate due to the difference in frequency and/or phase of wr _ clk and rd _ clk. Illustratively, taking PTP packet 1 received by lane1 as an example, the time when the network node writes PTP packet 1 in deskew fifo according to wr _ clk is 23 minutes 1.02 seconds at 19 days at 11 months 23 days at 2018, because the frequencies and/or phases of rd _ clk and wr _ clk are different, the time length when deskew fifo read by the network node buffers PTP packet 1 is 0.1 seconds, and the time when deskew fifo reads PTP packet 1 is 23 minutes 1.13 seconds at 19 days at 11 months 23 days at 2018 months 23 days at 11 months 23 days at 2018, resulting in a calculated time stamp value of the time stamp of PTP packet 1 being 23 minutes 1.03 seconds at 19 days at 11 months 23 days at 2018, and an error exists with the time when PTP packet 1 at 19 days at 11 months 23 days at 2018 years, thereby causing inaccurate measurement of delay between network nodes.

Disclosure of Invention

The application provides a stamping processing method and device, which are used for solving the problem that in the prior art, delay measurement among network nodes is inaccurate due to inaccurate stamping processing.

In a first aspect, the present application provides a method for stamping, where the method may be implemented by a network node, and the method includes: respectively inputting a first timestamp into a plurality of PTP messages received by the Ethernet port by the network node; the Ethernet port is provided with a plurality of lanes, and the plurality of PTP messages are received by the network node through the plurality of lanes; after the plurality of PTP messages cross a clock domain, the network node respectively inputs first timestamp values of first timestamps into the plurality of PTP messages and updates the first timestamp values into target timestamp values corresponding to target PTP messages in the plurality of PTP messages; the target PTP message is a PTP message received by a target lane in the plurality of lanes, and the target lane is the lane with the shortest delay or the lane with the longest delay; and the network node determines the time delay between the network node and the network node for sending the plurality of PTP messages according to the difference value between the timestamp value of the target and the timestamp values of the sending timestamps of the plurality of PTP messages. In the method, a network node stamps before the PTP messages received by each lane of an Ethernet port cross a clock domain, namely before the PTP messages received by each lane are written into deskew fifo, and after the PTP messages cross the clock domain, namely when the deskew fifo outputs the PTP messages, the time stamp value stamped by the PTP messages received by each lane is compensated to the time stamp value of the PTP message received by a specified target lane, so that delay time difference alignment is realized, errors caused by asynchronous deskew fifo are avoided, the accuracy of stamping processing is improved, and the accuracy of delay determination among network nodes is ensured; meanwhile, the stamping occurs before the PTP message is written into the deskew fifo, the frequency of a write clock and the frequency of a read clock which do not need the deskew fifo are kept consistent or in a multiple relation, so that Ethernet ports with different rates can share one set of stamping processing logic, each Ethernet port supports high-precision stamping processing, and the application range of the stamping processing is also enlarged.

In one possible design, the network node respectively stamps in first timestamps for a plurality of PTP messages received by an ethernet port, including: the network node respectively inputs a first timestamp to a first bit (bit) of a plurality of PTP messages received by the Ethernet port. By the method, the time stamp value of the time stamp injected into the PTP message received by each lane can be quickly compensated to the time stamp value of the time stamp injected into the target PTP message received by the target lane when the delay differences are aligned.

In one possible design, the network node respectively stamps in first timestamps for a plurality of PTP messages received by an ethernet port, including: the network node respectively inputs first time stamps into the set bits of the PTP messages received by the Ethernet port; the network node determines a first transmission time from the time when the plurality of PTP messages respectively correspond to the first bit to the set bit based on the distance between the plurality of PTP messages respectively corresponding to the set bit and the first bit; and the network node respectively inputs first time stamp values of first time stamps into the plurality of PTP messages and corrects the first time stamp values into a difference value between the first time stamp values and first transmission time lengths corresponding to the PTP messages. By the method, the stamping schemes of the network nodes are enriched, and the proper stamping scheme is selected conveniently according to the network environment where the network nodes are located.

In one possible design, the network node respectively stamps in first timestamps for a plurality of PTP messages received by an ethernet port, including: the network node respectively inputs first timestamps into a plurality of PTP messages received by the Ethernet port according to the measurement period and the stamping time respectively corresponding to a plurality of lanes of the Ethernet port in the current measurement period; the network node determines second transmission time lengths from the time when the plurality of PTP messages respectively correspond to the first bit to the time when the target bit with the first timestamp is embedded into the PTP messages respectively and correspondingly based on the distance between the target bit with the first timestamp embedded into the PTP messages and the first bit; and the network node respectively inputs first time stamp values of first time stamps into the plurality of PTP messages and corrects the first time stamp values into a difference value between the first time stamp values and second transmission time lengths corresponding to the PTP messages. By the method, the stamping schemes of the network nodes are enriched, and the proper stamping scheme is selected conveniently according to the network environment where the network nodes are located.

In a possible design, the updating the first timestamp values of the first timestamps into the PTP messages respectively to the target timestamp values corresponding to the target PTP messages in the PTP messages includes: the network node updates the first time stamp values of the first time stamps respectively injected into the PTP messages according to the sum of the first time stamp values of the first time stamps respectively injected into the PTP messages and the delay difference of the Lane receiving the PTP messages relative to the target Lane; the delay difference of each land relative to the target land is determined according to the difference between a second time stamp value obtained by adding a second time stamp to the set bit of the PTP message received by the target land before clock domain crossing and a second time stamp value obtained by adding the second time stamp to the set bit of the PTP message received by each land. By the method, the target PTP message does not need to be identified during each stamping process, and the stamping process flow is simplified.

In one possible design, the determining a target lane may comprise: and when the network node establishes a link at the Ethernet port, determining the lane corresponding to the target PTP message with the maximum timestamp value or the lane corresponding to the target PTP message with the minimum timestamp value in third timestamp values of third timestamps respectively input into a plurality of PTP messages received by the Ethernet port as the target lane. In this way, accurate determination of the target lane is facilitated, and accuracy of the stamping process is guaranteed.

In a second aspect, the present application provides a stamping processing apparatus having functionality to implement the method of the first aspect and any one of the possible designs. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.

In one possible design, the device may be a chip or an integrated circuit.

In one possible design, the apparatus includes a transceiver and a processor for executing a set of programs, and when the programs are executed, the apparatus may perform the method of the first aspect and any one of the possible designs.

In one possible design, the apparatus further includes a memory for storing a program executed by the processor.

In one possible design, the apparatus is a network node.

In a third aspect, the present application provides a computer storage medium storing a computer program comprising instructions for performing the method of the first aspect or any one of the possible designs of the first aspect.

In a fourth aspect, the present application provides a computer program product comprising instructions which, when run on a network node, cause the network node to perform the method of the first aspect described above or any one of the possible designs of the first aspect.

In a fifth aspect, a chip is provided, where the chip is connected to a memory, and is configured to read and execute a software program stored in the memory, so as to implement the method in the first aspect or any one of the possible designs of the first aspect.

Drawings

FIG. 1 is a schematic diagram of a delayed request response mechanism according to an embodiment of the present application;

FIG. 2 is a schematic diagram of deskew fifo mechanism of lane in the embodiment of the present application;

FIG. 3A is a schematic diagram of a communication system according to an embodiment of the present application;

FIG. 3B is a second schematic diagram of a communication system according to an embodiment of the present invention;

FIG. 4 is a third exemplary diagram of a communication system according to the present invention;

FIG. 5 is a schematic diagram of a stamping process in an embodiment of the present application;

fig. 6 is a schematic structural diagram of a network node in an embodiment of the present application;

fig. 7 is a second schematic structural diagram of a network node in the embodiment of the present application.

Detailed Description

The application provides a stamping processing method and a stamping processing device, which are used for improving the accuracy of stamping processing so as to ensure the accuracy of time delay measurement among network nodes, wherein the method and equipment are based on the same invention concept, and because the principles of solving problems of the method and the equipment are similar, the implementation of the equipment and the method can be mutually referred, and repeated parts are not repeated.

Hereinafter, some terms in the present application are explained to be understood by those skilled in the art.

The embodiment of the invention relates to a network node, and in a network system consisting of independent computers, workstations, servers, terminals, network equipment and the like which are connected with each other, each equipment with a unique network address can be called a network node. Currently, the network node may be a switch, a router, a computer, a tablet computer, a palm computer, a mobile phone (mobile phone), and the like.

The PTP protocol, also called IEEE1588 protocol, is issued by the Institute of Electrical and Electronics Engineers (IEEE) and is used for synchronizing clocks of network nodes in a network. The time delay between two network nodes is measured by time stamping t1, t2, t3, t4 and the like on the transmitting and receiving positions of the Ethernet ports of the two network nodes in the network. As shown in fig. 1, a slave node (slave node) sends a t1 timestamp of a synchronization message (sync) according to a master node (master node), the slave node receives a t2 timestamp of the sync, the slave node sends a t3 timestamp of a delay request message (delay _ request), the master node receives a t4 timestamp of the delay _ request, and determines a delay between the master node and the slave node, wherein the slave node knows the timestamp of the message sent by the master node, and the master node can also inform the sending timestamp of the slave node message by a following message recorded with the timestamp of the message sending, for example, after the master node sends the sync, the following message (follow _ up) recorded with the timestamp of the sync sending (t 1) is sent to the slave node, and in addition, the slave node (slave node) sends a timestamp of the slave node (delay _ request message 4 for facilitating the sending of the slave node. The delay (path delay) between the master node and the slave node is (t2-t1) or (t4-t3), the average delay (mean path delay) is [ (t2-t1) + (t4-t3) ]/2 or [ (t2-t3) + (t4-t1) ]/2, and generally, the mean path delay is adopted in the delay measurement in order to ensure the accuracy of the delay measurement. In the prior art, in an ethernet port of multiple lanes, after time stamp values of time stamps of PTP messages received by multiple lanes are compensated and aligned to time stamp values of time stamps of PTP messages received by a reference lane in a receiving direction, the time stamp of any lane receiving a PTP message can be used as the time stamp of receiving the PTP message when measuring delay.

The timestamp, also called timestamp (timestamp), is usually a sequence of characters uniquely identifying a time of a certain moment, and the timestamp value referred to in this application is the time of the certain moment identified by the timestamp, such as 45 minutes 32 seconds at 17 hours 17 of 23.11.2018.

The sending time of the PTP message and the receiving time of the PTP message, wherein the sending time of the PTP message in the application refers to the time of sending the first bit of the PTP message; the receiving time of the PTP message, also called the arrival time of the PTP message, is the time to receive the first bit of the PTP message.

Deskew fifo of a lane, that is, alignment of delay differences of data channels, means that PTP messages received by a plurality of lanes are aligned according to the lane with the longest delay. Illustratively, as shown in fig. 2, a serial data stream to be transmitted is 123456789, 3 lanes are established at a transmitting (tx) end and a receiving (rx) end, where the lanes are lane0, lane1, and lane2, respectively, and transmission data (tx data) corresponding to lane0, that is, a PTP message is 147, a tx data corresponding to lane1 is 258, a tx data corresponding to lane2 is 369, a lane0, a lane1, and a lane2 at the tx end simultaneously transmit PTP messages 147, 258, and 369, and time stamp events (time stamp events) at the tx end and the rx end all occur at a first bit of the PTP message, for example, the first bit "2" of the PTP message 258. The rx end receives PTP messages 147, 258 and 369 on lane0, lane1 and lane2 respectively, because link delays (link delays) corresponding to lane0, lane1 and lane2 are different, so that the receiving time of the rx end for receiving the PTP messages on lane0, lane1 and lane2 is different, the rx end writes the PTP received by each lane into deskew fifo, the received PTP messages are buffered through the deskew fifo, and the deskew fifo aligns the time of receiving the PTP messages by each lane which has received the PTP messages with the receiving time of receiving the PTP messages by the lane which has newly received the PTP messages. As shown in fig. 2, the most recently received PTP message is lane2, and the receiving time of PTP message received by each lane is aligned with the receiving time of PTP message received by lane 2.

Through deskew fifo of lane, the delay difference between lanes can also be calculated, for example: the sending time of the PTP message of each lane is 0, and the receiving time of the PTP message of each lane is the link delay of the lane. The implementation of deskew fifo may cause the buffer delay (deskew buffer delay) of each lane to increase by 3, which is caused by the deskew fifo implementation and needs to be eliminated. The total delay (total delay) of lane2 read by an rx end through deskew fifo is 108, the link delay of lane2 is 108-3-105, similarly, the link delay of lane0 is 100, the link delay of lane1 is 103, the delay difference between lane0 and lane2 is 8-3-5, and the delay difference between lane1 and lane2 is 5-3-2, but all the above are achieved based on the complete coincidence of wr _ clk and rd _ clk of deskew fifo, but actually, wr _ clk and rd _ clk of ethernet ports are different, so that errors exist in the determined total delay and/or deskew delay, and further the link delay of each lane is calculated inaccurately, that is, the receiving time of each lane PTP packet is not calculated accurately, and the timestamp value generated according to the receiving time is also inaccurate.

In addition, it is to be understood that a plurality referred to in the present application means two or more; in the description of the present application, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 3A is a communication system architecture applicable to a stamping process according to an embodiment of the present application, and as shown in fig. 3A, the communication system includes: a network node 1 and a network node 2, where an ethernet port 1 of the network node 1 establishes a link with the ethernet port of the network node 2 through a Physical Media Dependent (PMD) interface of the network node 1 and the PMD of the network node 2, and as shown in fig. 3A, 0 to N, and N +1 lanes are established between the network node 1 and the network node 2. Wherein the Ethernet port of the network node comprises: MAC, physical coding layer (PCS), physical medium attachment layer (PMA).

It should be understood that the embodiments of the present application may also be applied to other communication systems, and also applied to a case where a third party node exists between the network node 1 and the network node 2, as shown in fig. 4, a transparent transmission node (tc node) exists between the network node 1 and the network node 2. If a third-party node exists between the network node 1 and the network node 2, when the delay between the network node 1 and the network node 2 is determined, the delay caused by the third-party node needs to be removed. Referring to fig. 4, the path delay between the network node 1 and the network node 2 is (t2-t1-CF1) or (t4-t3-CF2), and the mean path delay is [ (t2-t1-CF1) + (t4-t3-CF2) ]/2 or [ (t2-t3) + (t4-t1) - (CF1+ CF2) ]/2, where CF1 is the delay caused by the tc node for transmitting the PTP message (sync) between the network node 1 and the network node 2, and CF2 is the delay caused by the tc node for transmitting the PTP message (delay _ request) between the network node 1 and the network node 2.

Still taking fig. 3A as an example, taking network node 1 as a tx end, network node 2 as an rx end, and performing a stamping process on N +1 lanes established between

ethernet ports

1 and 2 of network node 1 and network node 2 to send and receive a beat of PTP messages (such as sync, delay _ request, and the like), where the number of the beat of PTP messages is the same as the number of lanes, and each lane transmits one PTP message in the same beat.

A. An Ethernet port 1 of a network node 1 simultaneously sends PTP messages at lanes 0-N, each lane sends one PTP message, and PMA of the Ethernet port 1 generates sending timestamps (such as a t1 timestamp, a t3 timestamp and the like); B. an Ethernet port 2 of a network node 2 receives a plurality of PTP messages sent by the network node 1 through lanes 0-N, and before the PTP messages received by each lane cross a clock domain, namely before the PTP messages received by each lane are written into deskew fifo, a first timestamp is added to the PTP messages received by each lane. Such as: first time stamps are respectively input into a plurality of received PTP (precision time stamps) near an inlet of a serializer/deserializer (serdes) of the PMA, and the input first time stamps are accompanied with PTP message transmission.

C. After the lans 0-N receive the multiple PTP messages sent by the network node 1 and cross the clock domain, that is, after the received multiple PTP messages are written into the deskew fifo and output through the deskew fifo, the network node 2 adds the first timestamp values of the first timestamps into the received multiple PTP messages respectively, updates the target timestamp values corresponding to the target PTP messages in the multiple PTP messages, and realizes the delay difference alignment of the PTP messages received by each lane.

The target PTP message is a PTP message received by a target lane in the plurality of lanes, and the target lane is the lane with the shortest delay or the lane with the longest delay.

Specifically, if the target lane is a lane with the longest delay among lanes 0 to N, the PTP message with the largest first time stamp value with the first time stamp is dropped into the multiple PTP messages received by the network node 2, and the PTP message is a PTP message received by a lane with the longest delay among lanes 0 to N, and the network node 2 may drop the first time stamp value with the first time stamp into the PTP message received by each lane and update the first time stamp value with the largest first time stamp value in the first time stamp value with the first time stamp dropped into the multiple PTP messages received by the network node 2; similarly, if the target lane is the lane with the shortest delay among lanes 0-N, the network node 2 may add the first time stamp value of the first time stamp into the PTP message received by each lane, and update the first time stamp value to the smallest first time stamp value among the first time stamp values added with the first time stamps into the multiple PTP messages received by the network node 2, so as to implement compensation and alignment of the time stamp values of the time stamps of the PTP messages received by each lane onto the same target lane, and the target lane of the present application is compatible with the reference lane of the existing protocol, that is, the lane with the longest delay. After updating, the network node 2 can determine the time delay between the network node 1 and the network node 2 according to the difference between the first time stamp value (target time stamp value) of the updated first time stamp of the PTP message received by any lane and the time stamp values of the sending time stamps of the plurality of PTP messages sent by the network node 1, wherein for the time stamp values of the sending time stamps of the plurality of PTP messages sent by the network node 1, the following messages carrying the sending time stamps of the plurality of PTP messages sent by the network node 2 can be known after the network node 1 sends the plurality of PTP messages.

Taking lane1 as a target lane and PTP message 1 received by network node 2 through lane1 as an example, receiving time of PTP message 1 received by B and network node 1 is 23 minutes 1.02 seconds at 19 days at 11 months 23 days at 2018, a first timestamp is added into PTP message 1, the first timestamp value of the first timestamp is 1.02 seconds at 19 minutes 23 days at 11 months 23 days at 2018, and deskaew fifo is written into PTP message 1 to align delay time differences of multiple lanes; C. when deskew fifo outputs the PTP message, the first time stamp value of the first time stamp of the PTP message 1 is updated to the first time stamp value of the first time stamp of the target PTP message received by the target lane, and the first time stamp value is still equal to 19 minutes, 23 minutes and 1.02 seconds in 11, 23 and 19 months in 2018. Referring to the communication system architecture of the prior art stamping process shown in fig. 4, in the prior art, the stamping "B" of the PTP packet received by each lane occurs after the PTP packet is written into deskew fifo, because of wr _ clk of the ethernet port, that is, the clock (e.g. serdes clock) of the external PTP packet input is different from rd _ clk, that is, the internal clock of the ethernet port, so that the timestamp value of the receive timestamp of each lane determined by the network node is inaccurate, if the first timestamp value of the first timestamp of the PTP message 1 is determined to be 1.03 seconds at 19 hours 23 at 11 months 23 days 2018, and further, delay among network nodes is measured inaccurately, but the method stamps 'B' on the PTP message received by each lane before the PTP message is written into deskew fifo, and the PTP message does not cross a clock domain during stamping, so that the accuracy of stamping the PTP message received by each lane is ensured, and the accuracy of delay measurement among network nodes is ensured.

Optionally, for the confirmation of the target lane, when the

ethernet ports

1 and 2 of the

network nodes

1 and 2 initialize link establishment or reestablish a link, the network node 2 may respectively enter a third timestamp into PTP messages, which are sent by the ethernet port 1, of the network node 1 and received by each lane of the ethernet ports 2, and if the target lane is a lane with the minimum delay, determine the lane of the PTP message with the minimum third timestamp value, into which the third timestamp is entered, as the target lane; and if the target lane is the lane with the largest delay, determining the lane of the PTP message with the largest third time stamp value, into which the third time stamp is input, as the target lane. When initializing link establishment or reestablishing a link, the network node 2 adds a third timestamp to the PTP message received by each lane of the ethernet port 2, which may occur before the PTP message is written into the deskew fifo or after the PTP message is written into the deskew fifo.

Optionally, before crossing the clock domain, the network node 2 may enter first timestamps into the PTP messages received by the ethernet port 2, respectively, in the following manner:

the first method is as follows:

the network node 2 adds a first timestamp to a first bit of the PTP messages received by the ethernet port 2.

Specifically, for each lane of the ethernet port 2, the network node 2 impresses a first timestamp into the PTP message before the lane receives the PTP message and crosses the clock domain. The receiving time of the PTP message can be truly reflected by the timestamp value of the first timestamp which is input into the first bit of the PTP message, so that the timestamp value of the first timestamp of the PTP message does not need to be corrected, and the stamping processing flow is simplified.

The second method comprises the following steps:

the network node 2 inputs first timestamps into the set bits of the plurality of PTP messages received by the Ethernet port 2 respectively. The set bit may be a first bit, a third bit, a seventh bit, and the like of the PTP message, and optionally, the set bit is located in a message header (sop bit) of the PTP.

Specifically, for each lane of the ethernet port 2, the network node 2 impresses a first timestamp into the PTP message before the lane receives the PTP message and crosses the clock domain.

Since the set bit may be a third bit, a seventh bit, or the like, the first timestamp value of the first timestamp is added to the set bit of the PTP message, and the receiving time of the PTP message cannot be reflected really. Specifically, the network node 2 determines, for a PTP message received by each lane, a first transmission time length from the first bit to the set bit of the PTP message in the network node based on a distance between the set bit and the first bit of the PTP, because the set bit is the same for each lane, the first transmission time length from the first bit to the set bit of the PTP message received by each lane is the same, and the network node 2 adds a first time stamp value of the first time stamp into the PTP message and corrects the first time stamp value to a difference value between the first time stamp value and the first transmission time length. Optionally, the network node 2 corrects the timestamp value of the first timestamp added into each received PTP message to the receiving time of the first bit of the PTP message, and the correction can be implemented before the PTP message crosses the clock domain, or after the PTP message crosses the clock domain, as long as before the first timestamp value of the first timestamp added into the PTP message is updated to the target timestamp value corresponding to the target PTP message.

Illustratively, taking the PTP message 3 received by lane3 and setting bit to be the 7 th bit as an example, the first timestamp value of the first timestamp embedded in the PTP message 3 is 1.05 seconds from 11 months in 2018 to 23 days in 19 hours in 23 days, the first transmission time length of the PTP message 3 from the first bit to the seventh bit is "0.1 seconds", and the first timestamp value of the first timestamp of the PTP message 3 after correction is 1.04 seconds from 23 hours in 19 days in 11 months in 2018.

The third method comprises the following steps:

according to the measurement period, the network node 2 respectively stamps a plurality of PTP messages received by the Ethernet port 2 with first timestamps before the PTP messages cross a clock domain according to the respective corresponding stamping time of a plurality of lanes of the Ethernet port 2 in the current measurement period.

The measurement cycle of the delay measurement between the network node 1 and the network node 2 is known, the network node 2 can know the time period in which each lane of the ethernet port 2 can necessarily receive the PTP message in the current measurement cycle, and can determine the stamping time of each lane of the ethernet port 2 to stamp the received PTP message in the current measurement cycle according to the time period in which each lane can necessarily receive the PTP message in the current measurement cycle, optionally, the first timestamp of the stamping time of each lane of the ethernet port 2 to stamp the received PTP message in the current measurement cycle is located in the header of the PTP message received by each lane. The network node 2 stamps a first timestamp into the PTP message received by each lane of the ethernet port 2 according to the stamping time for stamping the PTP message received by each lane of the ethernet port 2 in the current measurement period.

Since the target bit with the first timestamp added in the PTP message may be the first bit of the PTP message, or may be the second bit, the fifth bit, or the like, the receiving time of the PTP message cannot be reflected really, in this application, the network node 2 is further required to correct the timestamp value with the first timestamp added in each PTP message received to the receiving time of the first bit of the PTP message. Specifically, the network node 2 determines, for a PTP message received by each lane, a second transmission time period from transmission of the PTP message from a first bit to transmission of a target bit with a first timestamp in the network node based on a distance between the target bit with the first timestamp and the first bit of the PTP, and the network node 2 corrects a first timestamp value with the first timestamp in the PTP message to a difference value between the first timestamp value and the first transmission time period. Optionally, the network node 2 corrects the timestamp value of the first timestamp added into each received PTP message to the receiving time of the first bit of the PTP message, and the correction can be implemented before the PTP message crosses the clock domain, or after the PTP crosses the clock domain, as long as before the first timestamp value of the first timestamp added into the PTP message is updated to the target timestamp value corresponding to the target PTP message.

Of course, when the network node 2 updates the first time stamp value of the first time stamp, which is respectively entered into the PTP messages received by the ethernet port 2, to the target time stamp value corresponding to the target PTP message in the received PTP messages, the network node may further update the first time stamp value of the first time stamp, which is entered into the PTP message, according to the sum of the first time stamp value of the first time stamp, which is entered into the PTP message, and the delay difference of the lane receiving the PTP message relative to the target lane, for each received PTP message.

Specifically, the network node 1 may send a PTP message at lanes 0 to N of the ethernet port 1 in advance, the ethernet port 2 of the network node 2 impresses a second timestamp into the bit of the PTP message received by each lane before the PTP message received by each lane of the ethernet port 2 crosses the clock domain, and determines the delay difference of each lane with respect to the destination lane according to a difference between a second timestamp value of the second timestamp of the PTP message received by each lane and a second timestamp value of the second timestamp of the PTP message received by the destination lane.

The stamping processing method can be also suitable for various Ethernet port combination (comb) scenes, at the moment, all the Ethernet ports share resources such as MAC/PCS/Forward Error Correction (FEC), and the like, the working clock frequency (the internal clock frequency of the Ethernet ports) of all the Ethernet ports is different from the clock frequency (such as the serdes clock frequency at the PMA position) of external PTP message input, but the stamping processing method is to stamp the PTP messages across clocks and before, so the stamping processing method is also suitable for various Ethernet port comb scenes.

Based on the foregoing embodiments, as shown in fig. 5, an embodiment of the present application provides a stamping processing method, which includes the specific steps of:

s501: the network node respectively inputs a first timestamp to a plurality of PTP messages received by the Ethernet port. The ethernet port has a plurality of lanes, and the plurality of PTP messages are received by the network node through the plurality of lanes.

S502: and after the plurality of PTP messages cross the clock domain, the network node respectively inputs first time stamp values of first time stamps into the plurality of PTP messages and updates the first time stamp values into target time stamp values corresponding to target PTP messages in the plurality of PTP messages. The target PTP message is a PTP message received by a target lane in the plurality of lanes, and the target lane is the lane with the shortest delay or the lane with the longest delay;

s503: and the network node determines the time delay between the network node and the network node for sending the plurality of PTP messages according to the difference value between the timestamp value of the target and the timestamp values of the sending timestamps of the plurality of PTP messages.

Based on the same concept, fig. 6 is a network node 600 provided by the present application, including: a processor 601 and a transceiver 602;

before a plurality of PTP messages received by an Ethernet port are written into deskew fifo of the Ethernet port through a transceiver 602, a processor 601 respectively stamps a first timestamp into the plurality of PTP messages; the Ethernet port is provided with a plurality of lanes, and the plurality of PTP messages are received by the network node through the plurality of lanes;

the processor 601 is further configured to, when the deskew fifo outputs the plurality of PTPs, respectively enter first timestamp values of first timestamps into the plurality of PTP messages, and update the PTP messages to target timestamp values corresponding to target PTP messages in the plurality of PTP messages; the target PTP message is a PTP message received by a target lane in the plurality of lanes, and the target lane is the lane with the shortest delay or the lane with the longest delay;

the processor 601 is further configured to determine a delay between the network node and the network node that sends the plurality of PTP messages according to a difference between the timestamp value of the target and the timestamp values of the sending timestamps of the plurality of PTP messages. .

Optionally, the processor 601 is specifically configured to, by the transceiver 602, before a plurality of PTP messages received by an ethernet port are written into the deskew fifo of the ethernet port, enter first timestamps into first bits of the plurality of PTP messages respectively.

Optionally, the processor 601 is specifically configured to, before a plurality of PTP messages received by an ethernet port are written into the deskew fifo of the ethernet port through the transceiver 602, enter first timestamps into the set bits of the plurality of PTP messages respectively; determining first transmission time lengths from the first bit to the set bit corresponding to the plurality of PTP messages respectively based on the distances between the set bit and the first bit corresponding to the plurality of PTP messages respectively; and respectively inputting first time stamp values of first time stamps into the PTP messages, and correcting the first time stamp values into the difference value between the first time stamp values and first transmission time corresponding to the PTP messages.

Optionally, the processor 601 is specifically configured to, according to a measurement cycle, based on respective corresponding stamping times of multiple lanes of an ethernet port in a current measurement cycle, respectively enter first timestamps into multiple PTP messages received by the ethernet port through the transceiver 602 before the multiple PTP messages are written into deskew fifo of the ethernet port; determining second transmission time lengths from the time when the plurality of PTP messages respectively correspond to the first bit to the time when the target bit with the first timestamp is embedded into the PTP messages respectively and correspondingly based on the distance between the target bit with the first timestamp embedded into the PTP messages and the first bit; and respectively inputting first time stamp values of first time stamps into the plurality of PTP messages, and correcting the first time stamp values to be the difference value between the first time stamp values and second transmission time lengths corresponding to the PTP messages.

Optionally, the processor 601 is specifically configured to update the first time stamp values of the first time stamps respectively entered in the multiple PTP messages according to a sum of the first time stamp values of the first time stamps respectively entered in the multiple PTP messages and a delay difference between the lane receiving the PTP message and the target lane; the delay difference of each land relative to the target land is determined according to the difference between a second timestamp value obtained by adding a second timestamp to the set bit of the PTP message received by the target land before the deskew fifo of the Ethernet port is written in and the second timestamp value obtained by adding the second timestamp to the set bit of the PTP message received by each land.

Optionally, the processor 601 is specifically configured to determine, when the ethernet port establishes a link, a lane corresponding to a target PTP message with a maximum timestamp value or a lane corresponding to a target PTP message with a minimum timestamp value among third timestamp values of third timestamps entered into the multiple PTP messages received by the ethernet port, as a target lane.

Based on the same conception, the embodiment of the application also provides a network node.

As shown in fig. 7, the network node 700 comprises a memory 701, a processor 702 and a transceiver 703. The memory 701, the processor 702, and the transceiver 703 are linked by a bus. The memory 701 is configured to store a computer execution instruction, and when the network node 700 runs, the processor 702 executes the computer execution instruction stored in the memory 701 through the transceiver 703, so that the network node 700 implements any one of the foregoing stamping processing methods, which may refer to the description above and the related description of the drawings, and is not described herein again.

The embodiment of the application provides a computer storage medium, which stores a computer program, wherein the computer program comprises instructions for executing the stamping processing method described in the embodiment of the method.

Embodiments of the present application provide a computer program product containing instructions that, when run on a network node, cause the network node to implement the stamping processing method described in the above method embodiments.

The embodiment of the present application provides a chip, where the chip is connected to a memory, and is configured to read and execute a software program stored in the memory, so as to implement the stamping processing method described in the above method embodiment.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims

PCT domestic application, the claims have been published.